Thanks for applying it, I'll skip the reせend then.
Thanks for applying it, I'll skip the reせend then.
On Thu, Jul 21, 2016 at 04:02:23PM -0500, Bjorn Helgaas wrote:
> Hi Christoph,
>
> This thread looks like it might be a typo. It doesn't use any of the
> new PCI MSI stuff. Looks like the cover letter from the PCI MSI
> patches, but the actual patches are from a different series?
Ah, sorry.
On Thu, Jul 21, 2016 at 04:02:23PM -0500, Bjorn Helgaas wrote:
> Hi Christoph,
>
> This thread looks like it might be a typo. It doesn't use any of the
> new PCI MSI stuff. Looks like the cover letter from the PCI MSI
> patches, but the actual patches are from a different series?
Ah, sorry.
On Tue, Jul 12, 2016 at 06:20:13PM +0900, Christoph Hellwig wrote:
> This series adds a new set of functions that transparently use the right
> type of interrupt (MSI-X, MSI, legacy interrupt line) for a PCI device,
> and if multiple vectors are supported automatically spreads the irq
> routing to
On Tue, Jul 12, 2016 at 06:20:13PM +0900, Christoph Hellwig wrote:
> This series adds a new set of functions that transparently use the right
> type of interrupt (MSI-X, MSI, legacy interrupt line) for a PCI device,
> and if multiple vectors are supported automatically spreads the irq
> routing to
Hi Christoph,
This thread looks like it might be a typo. It doesn't use any of the
new PCI MSI stuff. Looks like the cover letter from the PCI MSI
patches, but the actual patches are from a different series?
On Thu, Jul 21, 2016 at 04:30:20PM +0200, Christoph Hellwig wrote:
> This series adds
Hi Christoph,
This thread looks like it might be a typo. It doesn't use any of the
new PCI MSI stuff. Looks like the cover letter from the PCI MSI
patches, but the actual patches are from a different series?
On Thu, Jul 21, 2016 at 04:30:20PM +0200, Christoph Hellwig wrote:
> This series adds
This series adds a new set of functions that transparently use the right
type of interrupt (MSI-X, MSI, legacy interrupt line) for a PCI device,
and if multiple vectors are supported automatically spreads the irq
routing to different CPUs. This will allow the block layer (and hopefully
other
This series adds a new set of functions that transparently use the right
type of interrupt (MSI-X, MSI, legacy interrupt line) for a PCI device,
and if multiple vectors are supported automatically spreads the irq
routing to different CPUs. This will allow the block layer (and hopefully
other
This series adds a new set of functions that transparently use the right
type of interrupt (MSI-X, MSI, legacy interrupt line) for a PCI device,
and if multiple vectors are supported automatically spreads the irq
routing to different CPUs. This will allow the block layer (and hopefully
other
This series adds a new set of functions that transparently use the right
type of interrupt (MSI-X, MSI, legacy interrupt line) for a PCI device,
and if multiple vectors are supported automatically spreads the irq
routing to different CPUs. This will allow the block layer (and hopefully
other
On Tue, Jun 14, 2016 at 09:58:53PM +0200, Christoph Hellwig wrote:
> This series enhances the irq and PCI code to allow spreading around MSI and
> MSI-X vectors so that they have per-cpu affinity if possible, or at least
> per-node. For that it takes the algorithm from blk-mq, moves it to
> a
On Tue, Jun 14, 2016 at 09:58:53PM +0200, Christoph Hellwig wrote:
> This series enhances the irq and PCI code to allow spreading around MSI and
> MSI-X vectors so that they have per-cpu affinity if possible, or at least
> per-node. For that it takes the algorithm from blk-mq, moves it to
> a
On Thu, Jun 16, 2016 at 11:45:55AM +0200, Bart Van Assche wrote:
> Is my interpretation correct that for an adapter that supports two
> interrupts and on a system with eight CPU cores and no hyperthreading this
> patch series will assign interrupt vector 0 to CPU 0 and interrupt vector 1
> to
On Thu, Jun 16, 2016 at 11:45:55AM +0200, Bart Van Assche wrote:
> Is my interpretation correct that for an adapter that supports two
> interrupts and on a system with eight CPU cores and no hyperthreading this
> patch series will assign interrupt vector 0 to CPU 0 and interrupt vector 1
> to
On 06/14/2016 09:58 PM, Christoph Hellwig wrote:
This series enhances the irq and PCI code to allow spreading around MSI and
MSI-X vectors so that they have per-cpu affinity if possible, or at least
per-node. For that it takes the algorithm from blk-mq, moves it to
a common place, and makes it
On 06/14/2016 09:58 PM, Christoph Hellwig wrote:
This series enhances the irq and PCI code to allow spreading around MSI and
MSI-X vectors so that they have per-cpu affinity if possible, or at least
per-node. For that it takes the algorithm from blk-mq, moves it to
a common place, and makes it
This series enhances the irq and PCI code to allow spreading around MSI and
MSI-X vectors so that they have per-cpu affinity if possible, or at least
per-node. For that it takes the algorithm from blk-mq, moves it to
a common place, and makes it available through a vastly simplified PCI
interrupt
This series enhances the irq and PCI code to allow spreading around MSI and
MSI-X vectors so that they have per-cpu affinity if possible, or at least
per-node. For that it takes the algorithm from blk-mq, moves it to
a common place, and makes it available through a vastly simplified PCI
interrupt
20 matches
Mail list logo
