On Wed, Dec 19, 2012 at 02:49:25PM +0800, Chao Xie wrote:
> On Tue, Dec 18, 2012 at 3:47 PM, Sascha Hauer wrote:
> >> There is already a flag to do it.
> >> CLK_SET_RATE_PARENT
> >
> > That flag has another meaning. It means that a clock is allowed to
> > change the parents rate when a rate
On Wed, Dec 19, 2012 at 02:49:25PM +0800, Chao Xie wrote:
On Tue, Dec 18, 2012 at 3:47 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
There is already a flag to do it.
CLK_SET_RATE_PARENT
That flag has another meaning. It means that a clock is allowed to
change the parents rate when a
On Tue, Dec 18, 2012 at 3:47 PM, Sascha Hauer wrote:
> On Tue, Dec 18, 2012 at 10:19:21AM +0800, Chao Xie wrote:
>> On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer wrote:
>> > On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
>> >> hi
>> >> When develop the clk drivers for SOCs based on
On Tue, Dec 18, 2012 at 3:47 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Dec 18, 2012 at 10:19:21AM +0800, Chao Xie wrote:
On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
hi
When develop the
On Tue, Dec 18, 2012 at 10:19:21AM +0800, Chao Xie wrote:
> On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer wrote:
> > On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
> >> hi
> >> When develop the clk drivers for SOCs based on common clock framework.
> >> I met a issue.
> >> For example
On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer wrote:
> On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
>> hi
>> When develop the clk drivers for SOCs based on common clock framework.
>> I met a issue.
>> For example there is a uart device, it's function clock comes from a
>> divider,
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
> hi
> When develop the clk drivers for SOCs based on common clock framework.
> I met a issue.
> For example there is a uart device, it's function clock comes from a
> divider, and the divider's parent is a mux. It means
>
> MUX --> DIV
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
hi
When develop the clk drivers for SOCs based on common clock framework.
I met a issue.
For example there is a uart device, it's function clock comes from a
divider, and the divider's parent is a mux. It means
MUX -- DIV -- UART
On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
hi
When develop the clk drivers for SOCs based on common clock framework.
I met a issue.
For example there is a uart device, it's function clock comes from a
On Tue, Dec 18, 2012 at 10:19:21AM +0800, Chao Xie wrote:
On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
hi
When develop the clk drivers for SOCs based on common clock framework.
I met a issue.
For
hi
When develop the clk drivers for SOCs based on common clock framework.
I met a issue.
For example there is a uart device, it's function clock comes from a
divider, and the divider's parent is a mux. It means
MUX --> DIV --> UART
As we know that UART can work at low baudrate for a terminal,
hi
When develop the clk drivers for SOCs based on common clock framework.
I met a issue.
For example there is a uart device, it's function clock comes from a
divider, and the divider's parent is a mux. It means
MUX -- DIV -- UART
As we know that UART can work at low baudrate for a terminal,
12 matches
Mail list logo
