Yi Y20GA is an IP camera with QG2101A chip (a rebranded Allwinner V831).
Add a device tree for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts | 53 +++
2 files changed, 55 insertions(+), 1
ARM: dts: openbmc-flash-layout: Fix a typo of rofs offset
Signed-off-by: Kun Zhao
---
arch/arm/boot/dts/openbmc-flash-layout.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi
b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
index
Certain platforms require different settings in the
SDCC_HC_REG_DLL_CONFIG register. This setting can change from platform
to platform. So the driver should check whether a particular platform
require a different setting by reading the DT file and use it.
Also use msm_cm_dll_set_freq only when
Certain platforms require different settings in the
SDCC_HC_REG_DDR_CONFIG register. This setting can change from platform
to platform. So the driver should check whether a particular platform
require a different setting by reading the device tree file and use it.
Signed-off-by: Bao D. Nguyen
Certain platforms require different settings in the
SDCC_HC_REG_DLL_CONFIG register. This setting can change from platform
to platform. So the driver should check whether a particular platform
require a different setting by reading the DT file and use it.
Also use msm_cm_dll_set_freq only when
Certain platforms require different settings in the
SDCC_HC_REG_DDR_CONFIG register. This setting can change from platform
to platform. So the driver should check whether a particular platform
require a different setting by reading the device tree file and use it.
Signed-off-by: Bao D. Nguyen
just because some legacy boards seem to require changes in the gpio-lib
which make our so far correct DTS/DTB being wrongly interpreted.
A better solution seems to make the legacy handler optional so that DTS/DTB
developed without legacy modes are not harmed.
Signed-off-by: H. Nikolaus Schaller
On Fri, May 25, 2018 at 11:27:46AM +0200, Geert Uytterhoeven wrote:
> Hi Michel,
>
> On Thu, May 24, 2018 at 11:28 AM, Michel Pollet
> wrote:
> > This adds the Renesas R9A06G032 bare bone support.
> >
> > This currently only handles generic parts (gic, architected
On Fri, May 25, 2018 at 11:27:46AM +0200, Geert Uytterhoeven wrote:
> Hi Michel,
>
> On Thu, May 24, 2018 at 11:28 AM, Michel Pollet
> wrote:
> > This adds the Renesas R9A06G032 bare bone support.
> >
> > This currently only handles generic parts (gic, architected timer)
> > and a UART.
> >
> >
Hi Michel,
On Thu, May 24, 2018 at 11:28 AM, Michel Pollet
wrote:
> This adds the Renesas R9A06G032 bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
>
> Signed-off-by: Michel Pollet
Hi Michel,
On Thu, May 24, 2018 at 11:28 AM, Michel Pollet
wrote:
> This adds the Renesas R9A06G032 bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
>
> Signed-off-by: Michel Pollet
Thanks for your patch!
> --- /dev/null
> +++
This adds the Renesas R9A06G032 bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 86
1 file changed, 86
This adds the Renesas R9A06G032 bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 86
1 file changed, 86 insertions(+)
create mode
Hi Geert,
On Wed, 23 May 2018 at 12:18, Geert Uytterhoeven
wrote:
> Hi Michel,
> On Wed, May 23, 2018 at 11:20 AM, M P wrote:
> > On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
> > wrote:
> >> On Tue, May 22, 2018 at 12:01 PM,
Hi Geert,
On Wed, 23 May 2018 at 12:18, Geert Uytterhoeven
wrote:
> Hi Michel,
> On Wed, May 23, 2018 at 11:20 AM, M P wrote:
> > On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
> > wrote:
> >> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> >> wrote:
> >> > + #address-cells = <1>;
Hi Michel,
On Wed, May 23, 2018 at 11:20 AM, M P wrote:
> On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
> wrote:
>> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
>> wrote:
>> > + #address-cells = <1>;
>> > +
Hi Michel,
On Wed, May 23, 2018 at 11:20 AM, M P wrote:
> On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
> wrote:
>> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
>> wrote:
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > +
>> > + cpus {
>> > +
Hi Geert,
On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
wrote:
> Hi Michel,
> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> wrote:
> > This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> > bone support.
> >
> > This currently
Hi Geert,
On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
wrote:
> Hi Michel,
> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> wrote:
> > This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> > bone support.
> >
> > This currently only handles generic parts (gic, architected timer)
>
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
>
On Tue, May 22, 2018 at 11:01:24AM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
>
On Tue, May 22, 2018 at 11:01:24AM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
>
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
On Tue, Apr 17, 2018 at 12:04:19PM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
>
On Tue, Apr 17, 2018 at 12:04:19PM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
>
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
Hi Simon, Michel,
On Fri, Mar 30, 2018 at 09:25:16AM +0200, Simon Horman wrote:
> On Thu, Mar 29, 2018 at 01:04:50PM +0200, jacopo mondi wrote:
> > Hi Michel
> >
> > The subject of all your patches for arch/arm should start with:
> >
> > ARM: dts:
> >
> > A git log on that directory clearly shows
Hi Simon, Michel,
On Fri, Mar 30, 2018 at 09:25:16AM +0200, Simon Horman wrote:
> On Thu, Mar 29, 2018 at 01:04:50PM +0200, jacopo mondi wrote:
> > Hi Michel
> >
> > The subject of all your patches for arch/arm should start with:
> >
> > ARM: dts:
> >
> > A git log on that directory clearly shows
Hi Michel,
On Thu, Mar 29, 2018 at 9:47 AM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also
Hi Michel,
On Thu, Mar 29, 2018 at 9:47 AM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set
On Thu, Mar 29, 2018 at 01:04:50PM +0200, jacopo mondi wrote:
> Hi Michel
>
> The subject of all your patches for arch/arm should start with:
>
> ARM: dts:
>
> A git log on that directory clearly shows that's the preferred one.
>
> I would also say that you are missing a symbol definition in
>
On Thu, Mar 29, 2018 at 01:04:50PM +0200, jacopo mondi wrote:
> Hi Michel
>
> The subject of all your patches for arch/arm should start with:
>
> ARM: dts:
>
> A git log on that directory clearly shows that's the preferred one.
>
> I would also say that you are missing a symbol definition in
>
Hi Michel
The subject of all your patches for arch/arm should start with:
ARM: dts:
A git log on that directory clearly shows that's the preferred one.
I would also say that you are missing a symbol definition in
arch/arm/mach-shmobile/Kconfig
(even if you got rid of any board file)
I would
Hi Michel
The subject of all your patches for arch/arm should start with:
ARM: dts:
A git log on that directory clearly shows that's the preferred one.
I would also say that you are missing a symbol definition in
arch/arm/mach-shmobile/Kconfig
(even if you got rid of any board file)
I would
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
Hi Michel,
On Thu, Mar 22, 2018 at 12:44 PM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also
Hi Michel,
On Thu, Mar 22, 2018 at 12:44 PM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
ee based kernels with
U-boots that does not support device trees.
What they do is to reserve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux bin
that does not support device trees.
What they do is to reserve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, c
he U-boot
>> is broken...
>>
>>
>>>
>>>>> Not my choice of H/W, so I cannot change it.
>>>>>
>>>>>
>>>>> ===
>>>>> OPENWRT:
>>>>
.
>>
>>
>>>
>>>>> Not my choice of H/W, so I cannot change it.
>>>>>
>>>>>
>>>>> =======
>>>>> OPENWRT:
>>>>> I noticed when chec
oot device tree based kernels with
U-boots that does not support device trees.
What they do is to reserve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, c
oot device tree based kernels with
U-boots that does not support device trees.
What they do is to reserve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, c
that does not support device trees.
What they do is to reserve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, c
that does not support device trees.
What they do is to reserve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, c
erve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, copying in the
device tree file.
===
It would be usefu
erve 16 kB of kernel space, and tag it with
an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, copying in the
device tree file.
===
It would be usefu
;> I noticed when checking out the OpenWRT support for the board that
>>>> they have a method to avoid having to pass the device tree address
>>>> to the kernel, and can thus boot device tree based kernels with
>>>> U-boots that does not support device trees.
;> I noticed when checking out the OpenWRT support for the board that
>>>> they have a method to avoid having to pass the device tree address
>>>> to the kernel, and can thus boot device tree based kernels with
>>>> U-boots that does not support device trees.
nel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, copying in the
device tree file.
===
It would be useful to me, and I could of course patch the
mainstream kernel, but first I would like to check if this
nel and dtb is built, a
utility "patch-dtb" will update the vmlinux binary, copying in the
device tree file.
===
It would be useful to me, and I could of course patch the
mainstream kernel, but first I would like to check if this
Ulf,
On 11/20/17 06:44, Mark Rutland wrote:
> On Sun, Nov 19, 2017 at 11:23:42PM -0500, Frank Rowand wrote:
>> adding devicetree list, devicetree maintainers
>>
>> On 11/18/17 12:59, Ulf Samuelsson wrote:
>>> I noticed when checking out the OpenWRT support for the board that they
>>> have a
Ulf,
On 11/20/17 06:44, Mark Rutland wrote:
> On Sun, Nov 19, 2017 at 11:23:42PM -0500, Frank Rowand wrote:
>> adding devicetree list, devicetree maintainers
>>
>> On 11/18/17 12:59, Ulf Samuelsson wrote:
>>> I noticed when checking out the OpenWRT support for the board that they
>>> have a
On Sun, Nov 19, 2017 at 11:23:42PM -0500, Frank Rowand wrote:
> adding devicetree list, devicetree maintainers
>
> On 11/18/17 12:59, Ulf Samuelsson wrote:
> > I noticed when checking out the OpenWRT support for the board that they
> > have a method to avoid having to pass the device tree
On Sun, Nov 19, 2017 at 11:23:42PM -0500, Frank Rowand wrote:
> adding devicetree list, devicetree maintainers
>
> On 11/18/17 12:59, Ulf Samuelsson wrote:
> > I noticed when checking out the OpenWRT support for the board that they
> > have a method to avoid having to pass the device tree
;> to the kernel, and can thus boot device tree based kernels with
>> U-boots that does not support device trees.
>>
>> What they do is to reserve 16 kB of kernel space, and tag it with
>> an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
>&g
;> to the kernel, and can thus boot device tree based kernels with
>> U-boots that does not support device trees.
>>
>> What they do is to reserve 16 kB of kernel space, and tag it with
>> an ASCII string "OWRTDTB:". After the kernel and dtb is built, a
>&g
tag it with an ASCII
> string "OWRTDTB:".
> After the kernel and dtb is built, a utility "patch-dtb" will update the
> vmlinux binary, copying in the device tree file.
>
> ===
> It would be
tag it with an ASCII
> string "OWRTDTB:".
> After the kernel and dtb is built, a utility "patch-dtb" will update the
> vmlinux binary, copying in the device tree file.
>
> ===
> It would be
vice trees.
What they do is to reserve 16 kB of kernel space, and tag it with an
ASCII string "OWRTDTB:".
After the kernel and dtb is built, a utility "patch-dtb" will update the
vmlinux binary, copying in the device tree file.
==
vice trees.
What they do is to reserve 16 kB of kernel space, and tag it with an
ASCII string "OWRTDTB:".
After the kernel and dtb is built, a utility "patch-dtb" will update the
vmlinux binary, copying in the device tree file.
==
Hi,
Can someone point me to a specific device tree file for Intel Atom processor
for reference ?
Thanks in advance,
Karthik Balaguru
Disclaimer :
This email communication may contain privileged and confidential information
and is intended for the use of the addressee only. If you
Hi,
Can someone point me to a specific device tree file for Intel Atom processor
for reference ?
Thanks in advance,
Karthik Balaguru
Disclaimer :
This email communication may contain privileged and confidential information
and is intended for the use of the addressee only. If you
From: Tom Lendacky
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 117
2 files changed, 118 insertions
From: Tom Lendacky <thomas.lenda...@amd.com>
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-
From: Tom Lendacky
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 117
2 files changed, 118 insertions
From: Tom Lendacky <thomas.lenda...@amd.com>
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-
From: Tom Lendacky
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 117
2 files changed, 118 insertions
From: Tom Lendacky <thomas.lenda...@amd.com>
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/amd/amd-seattle-xgbe-
On Mon, Sep 28, 2015 at 03:19:05PM -0500, Li Yang wrote:
> On Mon, Sep 28, 2015 at 2:29 PM, Russell King - ARM Linux
> wrote:
> > However, we can't dictate to people what license they wish to submit
> > their work under; though, we can make the decision whether to accept
> > it under the license
On Mon, Sep 28, 2015 at 2:29 PM, Russell King - ARM Linux
wrote:
> On Mon, Sep 28, 2015 at 07:14:30PM +, Li Leo wrote:
>> I saw some discussion going on last year about the permissive license
>> to be used in ARM device tree files. I know a lot of files have been
>> changed to use GPLv2/X11
On Mon, Sep 28, 2015 at 07:14:30PM +, Li Leo wrote:
> I saw some discussion going on last year about the permissive license
> to be used in ARM device tree files. I know a lot of files have been
> changed to use GPLv2/X11 license. But may I know if GPLv2/BSD 3-clause
> dual license is still
Hi All,
I saw some discussion going on last year about the permissive license to be
used in ARM device tree files. I know a lot of files have been changed to use
GPLv2/X11 license. But may I know if GPLv2/BSD 3-clause dual license is still
a valid license to use in ARM device tree files. It
On Mon, Sep 28, 2015 at 07:14:30PM +, Li Leo wrote:
> I saw some discussion going on last year about the permissive license
> to be used in ARM device tree files. I know a lot of files have been
> changed to use GPLv2/X11 license. But may I know if GPLv2/BSD 3-clause
> dual license is still
Hi All,
I saw some discussion going on last year about the permissive license to be
used in ARM device tree files. I know a lot of files have been changed to use
GPLv2/X11 license. But may I know if GPLv2/BSD 3-clause dual license is still
a valid license to use in ARM device tree files. It
On Mon, Sep 28, 2015 at 03:19:05PM -0500, Li Yang wrote:
> On Mon, Sep 28, 2015 at 2:29 PM, Russell King - ARM Linux
> wrote:
> > However, we can't dictate to people what license they wish to submit
> > their work under; though, we can make the decision whether to accept
>
On Mon, Sep 28, 2015 at 2:29 PM, Russell King - ARM Linux
wrote:
> On Mon, Sep 28, 2015 at 07:14:30PM +, Li Leo wrote:
>> I saw some discussion going on last year about the permissive license
>> to be used in ARM device tree files. I know a lot of files have been
>>
> new file mode 100644
> index ..aa01c2610c6d
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
> @@ -0,0 +1,308 @@
> +/*
> + * sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
> + *
> + * Copyright (C) 2014 Atmel,
> + *
100644
index ..aa01c2610c6d
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ * Copyright (C) 2014 Atmel,
+ *2014 Nicolas Ferre nicolas.fe...@atmel.com
-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts
b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index ..aa01c2610c6d
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file
From: Nicolas Ferre
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre
Signed-off-by: Josh Wu
Signed-off-by: Bo Shen
Signed-off-by: Boris BREZILLON
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/sama5d4.dtsi | 1239
1 file changed, 1239
From: Nicolas Ferre nicolas.fe...@atmel.com
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Josh Wu josh...@atmel.com
Signed-off-by: Bo Shen voice.s...@atmel.com
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by:
/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ * Copyright (C) 2014 Atmel,
+ *2014 Nicolas Ferre nicolas.fe...@atmel.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts
b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index ..aa01c2610c6d
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file
From: Nicolas Ferre
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre
Signed-off-by: Josh Wu
Signed-off-by: Boris BREZILLON
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/sama5d4.dtsi | 1233
1 file changed, 1233 insertions(+)
create
From: Nicolas Ferre nicolas.fe...@atmel.com
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Josh Wu josh...@atmel.com
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Alexandre Belloni
/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ * Copyright (C) 2014 Atmel,
+ *2014 Nicolas Ferre nicolas.fe...@atmel.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts
b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index ..aa01c2610c6d
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file
From: Nicolas Ferre
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre
Signed-off-by: Josh Wu
Signed-off-by: Boris BREZILLON
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/sama5d4.dtsi | 1233
1 file changed, 1233 insertions(+)
create
From: Nicolas Ferre nicolas.fe...@atmel.com
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Josh Wu josh...@atmel.com
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Alexandre Belloni
/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ * Copyright (C) 2014 Atmel,
+ *2014 Nicolas Ferre nicolas.fe...@atmel.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
On 12/03/2013 06:16 AM, Laxman Dewangan wrote:
> Signed-off-by: Laxman Dewangan
Patch description? Why convert only 1 board DT file?
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