Re: oz6812, yenta_socket and madwifi
On Monday 25 July 2005 21.38, Peter Staubach wrote:
> Daniel Ritz wrote:
[...]
>
> Shouldn't the two pairs of calls to config_writeb() be using
> "O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST" instead of
> "O2_RES_READ_PREFETCH | O2_RES_READ_PREFETCH"?
>
yes, of course. thanks for noticing. updated patch attached.
dominik/akpm, please drop the other and use this one instead...
thx, rgds
-daniel
-
[PATCH 11/11] pcmcia: disable read prefetch/write burst on old O2Micro bridges
From: Daniel Ritz <[EMAIL PROTECTED]>
older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card. safest
is to disable read prefetch and write burst on those old bridges.
Signed-off-by: Daniel Ritz <[EMAIL PROTECTED]>
Signed-off-by: Dominik Brodowski <[EMAIL PROTECTED]>
--
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
#define O2_MODE_E_LED_OUT 0x08
#define O2_MODE_E_SKTA_ACTV 0x10
+#define O2_RESERVED1 0x94
+#define O2_RESERVED2 0xD4
+#define O2_RES_READ_PREFETCH 0x02
+#define O2_RES_WRITE_BURST 0x08
+
static int o2micro_override(struct yenta_socket *socket)
{
/*
-* 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-* read prefetching which for example makes the RME Hammerfall DSP
+* 'reserved' register at 0x94/D4. allows setting read prefetch and
write
+* bursting. read prefetching for example makes the RME Hammerfall DSP
* working. for some bridges it is at 0x94, for others at 0xD4. it's
* ok to write to both registers on all O2 bridges.
* from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta
u8 a, b;
if (PCI_FUNC(socket->dev->devfn) == 0) {
- a = config_readb(socket, 0x94);
- b = config_readb(socket, 0xD4);
+ a = config_readb(socket, O2_RESERVED1);
+ b = config_readb(socket, O2_RESERVED2);
printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a,
b);
switch (socket->dev->device) {
+ /*
+* older bridges have problems with both read prefetch and write
+* bursting depending on the combination of the chipset, bridge
+* and the cardbus card. so disable them to be on the safe side.
+*/
+ case PCI_DEVICE_ID_O2_6729:
+ case PCI_DEVICE_ID_O2_6730:
+ case PCI_DEVICE_ID_O2_6812:
case PCI_DEVICE_ID_O2_6832:
- printk(KERN_INFO "Yenta O2: old bridge, not enabling
read prefetch / write burst\n");
+ case PCI_DEVICE_ID_O2_6836:
+ printk(KERN_INFO "Yenta O2: old bridge, disabling read
prefetch/write burst\n");
+ config_writeb(socket, O2_RESERVED1,
+ a & ~(O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST));
+ config_writeb(socket, O2_RESERVED2,
+ b & ~(O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST));
break;
default:
printk(KERN_INFO "Yenta O2: enabling read
prefetch/write burst\n");
- config_writeb(socket, 0x94, a | 0x0a);
- config_writeb(socket, 0xD4, b | 0x0a);
+ config_writeb(socket, O2_RESERVED1,
+ a | O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST);
+ config_writeb(socket, O2_RESERVED2,
+ b | O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST);
}
}
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Re: oz6812, yenta_socket and madwifi
Daniel Ritz wrote:
hi
since i'm the one that put that code there in the first place i guess
i have to comment on it :)
the attached patch should also fix your problem. and it cleans up the
magic numbers a bit.
rgds
-daniel
-
[PATCH] disable read prefetch/write burst on old O2Micro bridges
older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card. safest
is to disable read prefetch and write burst on those old bridges.
Signed-off-by: Daniel Ritz <[EMAIL PROTECTED]>
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
#define O2_MODE_E_LED_OUT 0x08
#define O2_MODE_E_SKTA_ACTV0x10
+#define O2_RESERVED1 0x94
+#define O2_RESERVED2 0xD4
+#define O2_RES_READ_PREFETCH 0x02
+#define O2_RES_WRITE_BURST 0x08
+
static int o2micro_override(struct yenta_socket *socket)
{
/*
-* 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-* read prefetching which for example makes the RME Hammerfall DSP
+* 'reserved' register at 0x94/D4. allows setting read prefetch and
write
+* bursting. read prefetching for example makes the RME Hammerfall DSP
* working. for some bridges it is at 0x94, for others at 0xD4. it's
* ok to write to both registers on all O2 bridges.
* from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta
u8 a, b;
if (PCI_FUNC(socket->dev->devfn) == 0) {
- a = config_readb(socket, 0x94);
- b = config_readb(socket, 0xD4);
+ a = config_readb(socket, O2_RESERVED1);
+ b = config_readb(socket, O2_RESERVED2);
printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a,
b);
switch (socket->dev->device) {
+ /*
+* older bridges have problems with both read prefetch and write
+* bursting depending on the combination of the chipset, bridge
+* and the cardbus card. so disable them to be on the safe side.
+*/
+ case PCI_DEVICE_ID_O2_6729:
+ case PCI_DEVICE_ID_O2_6730:
+ case PCI_DEVICE_ID_O2_6812:
case PCI_DEVICE_ID_O2_6832:
- printk(KERN_INFO "Yenta O2: old bridge, not enabling read
prefetch / write burst\n");
+ case PCI_DEVICE_ID_O2_6836:
+ printk(KERN_INFO "Yenta O2: old bridge, disabling read
prefetch/write burst\n");
+ config_writeb(socket, O2_RESERVED1,
+ a & ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
+ config_writeb(socket, O2_RESERVED2,
+ b & ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
break;
default:
printk(KERN_INFO "Yenta O2: enabling read prefetch/write
burst\n");
- config_writeb(socket, 0x94, a | 0x0a);
- config_writeb(socket, 0xD4, b | 0x0a);
+ config_writeb(socket, O2_RESERVED1,
+ a | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
+ config_writeb(socket, O2_RESERVED2,
+ b | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
}
}
Shouldn't the two pairs of calls to config_writeb() be using
"O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST" instead of
"O2_RES_READ_PREFETCH | O2_RES_READ_PREFETCH"?
Thanx...
ps
-
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Re: oz6812, yenta_socket and madwifi
Daniel Ritz wrote:
hi
since i'm the one that put that code there in the first place i guess
i have to comment on it :)
the attached patch should also fix your problem. and it cleans up the
magic numbers a bit.
rgds
-daniel
-
[PATCH] disable read prefetch/write burst on old O2Micro bridges
older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card. safest
is to disable read prefetch and write burst on those old bridges.
Signed-off-by: Daniel Ritz [EMAIL PROTECTED]
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
#define O2_MODE_E_LED_OUT 0x08
#define O2_MODE_E_SKTA_ACTV0x10
+#define O2_RESERVED1 0x94
+#define O2_RESERVED2 0xD4
+#define O2_RES_READ_PREFETCH 0x02
+#define O2_RES_WRITE_BURST 0x08
+
static int o2micro_override(struct yenta_socket *socket)
{
/*
-* 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-* read prefetching which for example makes the RME Hammerfall DSP
+* 'reserved' register at 0x94/D4. allows setting read prefetch and
write
+* bursting. read prefetching for example makes the RME Hammerfall DSP
* working. for some bridges it is at 0x94, for others at 0xD4. it's
* ok to write to both registers on all O2 bridges.
* from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta
u8 a, b;
if (PCI_FUNC(socket-dev-devfn) == 0) {
- a = config_readb(socket, 0x94);
- b = config_readb(socket, 0xD4);
+ a = config_readb(socket, O2_RESERVED1);
+ b = config_readb(socket, O2_RESERVED2);
printk(KERN_INFO Yenta O2: res at 0x94/0xD4: %02x/%02x\n, a,
b);
switch (socket-dev-device) {
+ /*
+* older bridges have problems with both read prefetch and write
+* bursting depending on the combination of the chipset, bridge
+* and the cardbus card. so disable them to be on the safe side.
+*/
+ case PCI_DEVICE_ID_O2_6729:
+ case PCI_DEVICE_ID_O2_6730:
+ case PCI_DEVICE_ID_O2_6812:
case PCI_DEVICE_ID_O2_6832:
- printk(KERN_INFO Yenta O2: old bridge, not enabling read
prefetch / write burst\n);
+ case PCI_DEVICE_ID_O2_6836:
+ printk(KERN_INFO Yenta O2: old bridge, disabling read
prefetch/write burst\n);
+ config_writeb(socket, O2_RESERVED1,
+ a ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
+ config_writeb(socket, O2_RESERVED2,
+ b ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
break;
default:
printk(KERN_INFO Yenta O2: enabling read prefetch/write
burst\n);
- config_writeb(socket, 0x94, a | 0x0a);
- config_writeb(socket, 0xD4, b | 0x0a);
+ config_writeb(socket, O2_RESERVED1,
+ a | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
+ config_writeb(socket, O2_RESERVED2,
+ b | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
}
}
Shouldn't the two pairs of calls to config_writeb() be using
O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST instead of
O2_RES_READ_PREFETCH | O2_RES_READ_PREFETCH?
Thanx...
ps
-
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Please read the FAQ at http://www.tux.org/lkml/
Re: oz6812, yenta_socket and madwifi
On Monday 25 July 2005 21.38, Peter Staubach wrote:
Daniel Ritz wrote:
[...]
Shouldn't the two pairs of calls to config_writeb() be using
O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST instead of
O2_RES_READ_PREFETCH | O2_RES_READ_PREFETCH?
yes, of course. thanks for noticing. updated patch attached.
dominik/akpm, please drop the other and use this one instead...
thx, rgds
-daniel
-
[PATCH 11/11] pcmcia: disable read prefetch/write burst on old O2Micro bridges
From: Daniel Ritz [EMAIL PROTECTED]
older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card. safest
is to disable read prefetch and write burst on those old bridges.
Signed-off-by: Daniel Ritz [EMAIL PROTECTED]
Signed-off-by: Dominik Brodowski [EMAIL PROTECTED]
--
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
#define O2_MODE_E_LED_OUT 0x08
#define O2_MODE_E_SKTA_ACTV 0x10
+#define O2_RESERVED1 0x94
+#define O2_RESERVED2 0xD4
+#define O2_RES_READ_PREFETCH 0x02
+#define O2_RES_WRITE_BURST 0x08
+
static int o2micro_override(struct yenta_socket *socket)
{
/*
-* 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-* read prefetching which for example makes the RME Hammerfall DSP
+* 'reserved' register at 0x94/D4. allows setting read prefetch and
write
+* bursting. read prefetching for example makes the RME Hammerfall DSP
* working. for some bridges it is at 0x94, for others at 0xD4. it's
* ok to write to both registers on all O2 bridges.
* from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta
u8 a, b;
if (PCI_FUNC(socket-dev-devfn) == 0) {
- a = config_readb(socket, 0x94);
- b = config_readb(socket, 0xD4);
+ a = config_readb(socket, O2_RESERVED1);
+ b = config_readb(socket, O2_RESERVED2);
printk(KERN_INFO Yenta O2: res at 0x94/0xD4: %02x/%02x\n, a,
b);
switch (socket-dev-device) {
+ /*
+* older bridges have problems with both read prefetch and write
+* bursting depending on the combination of the chipset, bridge
+* and the cardbus card. so disable them to be on the safe side.
+*/
+ case PCI_DEVICE_ID_O2_6729:
+ case PCI_DEVICE_ID_O2_6730:
+ case PCI_DEVICE_ID_O2_6812:
case PCI_DEVICE_ID_O2_6832:
- printk(KERN_INFO Yenta O2: old bridge, not enabling
read prefetch / write burst\n);
+ case PCI_DEVICE_ID_O2_6836:
+ printk(KERN_INFO Yenta O2: old bridge, disabling read
prefetch/write burst\n);
+ config_writeb(socket, O2_RESERVED1,
+ a ~(O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST));
+ config_writeb(socket, O2_RESERVED2,
+ b ~(O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST));
break;
default:
printk(KERN_INFO Yenta O2: enabling read
prefetch/write burst\n);
- config_writeb(socket, 0x94, a | 0x0a);
- config_writeb(socket, 0xD4, b | 0x0a);
+ config_writeb(socket, O2_RESERVED1,
+ a | O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST);
+ config_writeb(socket, O2_RESERVED2,
+ b | O2_RES_READ_PREFETCH |
O2_RES_WRITE_BURST);
}
}
-
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Re: oz6812, yenta_socket and madwifi
hi
since i'm the one that put that code there in the first place i guess
i have to comment on it :)
the attached patch should also fix your problem. and it cleans up the
magic numbers a bit.
rgds
-daniel
-
[PATCH] disable read prefetch/write burst on old O2Micro bridges
older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card. safest
is to disable read prefetch and write burst on those old bridges.
Signed-off-by: Daniel Ritz <[EMAIL PROTECTED]>
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
#define O2_MODE_E_LED_OUT 0x08
#define O2_MODE_E_SKTA_ACTV 0x10
+#define O2_RESERVED1 0x94
+#define O2_RESERVED2 0xD4
+#define O2_RES_READ_PREFETCH 0x02
+#define O2_RES_WRITE_BURST 0x08
+
static int o2micro_override(struct yenta_socket *socket)
{
/*
-* 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-* read prefetching which for example makes the RME Hammerfall DSP
+* 'reserved' register at 0x94/D4. allows setting read prefetch and
write
+* bursting. read prefetching for example makes the RME Hammerfall DSP
* working. for some bridges it is at 0x94, for others at 0xD4. it's
* ok to write to both registers on all O2 bridges.
* from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta
u8 a, b;
if (PCI_FUNC(socket->dev->devfn) == 0) {
- a = config_readb(socket, 0x94);
- b = config_readb(socket, 0xD4);
+ a = config_readb(socket, O2_RESERVED1);
+ b = config_readb(socket, O2_RESERVED2);
printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a,
b);
switch (socket->dev->device) {
+ /*
+* older bridges have problems with both read prefetch and write
+* bursting depending on the combination of the chipset, bridge
+* and the cardbus card. so disable them to be on the safe side.
+*/
+ case PCI_DEVICE_ID_O2_6729:
+ case PCI_DEVICE_ID_O2_6730:
+ case PCI_DEVICE_ID_O2_6812:
case PCI_DEVICE_ID_O2_6832:
- printk(KERN_INFO "Yenta O2: old bridge, not enabling
read prefetch / write burst\n");
+ case PCI_DEVICE_ID_O2_6836:
+ printk(KERN_INFO "Yenta O2: old bridge, disabling read
prefetch/write burst\n");
+ config_writeb(socket, O2_RESERVED1,
+ a & ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
+ config_writeb(socket, O2_RESERVED2,
+ b & ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
break;
default:
printk(KERN_INFO "Yenta O2: enabling read
prefetch/write burst\n");
- config_writeb(socket, 0x94, a | 0x0a);
- config_writeb(socket, 0xD4, b | 0x0a);
+ config_writeb(socket, O2_RESERVED1,
+ a | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
+ config_writeb(socket, O2_RESERVED2,
+ b | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
}
}
-
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Re: oz6812, yenta_socket and madwifi
hi
since i'm the one that put that code there in the first place i guess
i have to comment on it :)
the attached patch should also fix your problem. and it cleans up the
magic numbers a bit.
rgds
-daniel
-
[PATCH] disable read prefetch/write burst on old O2Micro bridges
older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card. safest
is to disable read prefetch and write burst on those old bridges.
Signed-off-by: Daniel Ritz [EMAIL PROTECTED]
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
#define O2_MODE_E_LED_OUT 0x08
#define O2_MODE_E_SKTA_ACTV 0x10
+#define O2_RESERVED1 0x94
+#define O2_RESERVED2 0xD4
+#define O2_RES_READ_PREFETCH 0x02
+#define O2_RES_WRITE_BURST 0x08
+
static int o2micro_override(struct yenta_socket *socket)
{
/*
-* 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-* read prefetching which for example makes the RME Hammerfall DSP
+* 'reserved' register at 0x94/D4. allows setting read prefetch and
write
+* bursting. read prefetching for example makes the RME Hammerfall DSP
* working. for some bridges it is at 0x94, for others at 0xD4. it's
* ok to write to both registers on all O2 bridges.
* from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta
u8 a, b;
if (PCI_FUNC(socket-dev-devfn) == 0) {
- a = config_readb(socket, 0x94);
- b = config_readb(socket, 0xD4);
+ a = config_readb(socket, O2_RESERVED1);
+ b = config_readb(socket, O2_RESERVED2);
printk(KERN_INFO Yenta O2: res at 0x94/0xD4: %02x/%02x\n, a,
b);
switch (socket-dev-device) {
+ /*
+* older bridges have problems with both read prefetch and write
+* bursting depending on the combination of the chipset, bridge
+* and the cardbus card. so disable them to be on the safe side.
+*/
+ case PCI_DEVICE_ID_O2_6729:
+ case PCI_DEVICE_ID_O2_6730:
+ case PCI_DEVICE_ID_O2_6812:
case PCI_DEVICE_ID_O2_6832:
- printk(KERN_INFO Yenta O2: old bridge, not enabling
read prefetch / write burst\n);
+ case PCI_DEVICE_ID_O2_6836:
+ printk(KERN_INFO Yenta O2: old bridge, disabling read
prefetch/write burst\n);
+ config_writeb(socket, O2_RESERVED1,
+ a ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
+ config_writeb(socket, O2_RESERVED2,
+ b ~(O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH));
break;
default:
printk(KERN_INFO Yenta O2: enabling read
prefetch/write burst\n);
- config_writeb(socket, 0x94, a | 0x0a);
- config_writeb(socket, 0xD4, b | 0x0a);
+ config_writeb(socket, O2_RESERVED1,
+ a | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
+ config_writeb(socket, O2_RESERVED2,
+ b | O2_RES_READ_PREFETCH |
O2_RES_READ_PREFETCH);
}
}
-
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oz6812, yenta_socket and madwifi
Hi,
for some time I was unable to use Atheros based cards on my
notebook (O2Micro oz6812 Cardbus controller) because of lots
of rx packets getting dropped by frame errors. running ping I got
this: (~1m from access point)
PING 192.168.67.1 (192.168.67.1): 56 data bytes
64 bytes from 192.168.67.1: icmp_seq=0 ttl=64 time=1.5 ms
wrong data byte #20 should be 0x14 but was 0x0
0 10 18 1 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29
2a 2b 2c 2d 2e 2f 30 31 32 33
34 35 36 37 0 0 0 0 84 dc 5 8 ff ff ff ff
64 bytes from 192.168.67.1: icmp_seq=4 ttl=64 time=1.3 ms
wrong data byte #20 should be 0x14 but was 0x0
0 10 18 1 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29
2a 2b 2c 2d 2e 2f 30 31 32 33
34 35 36 37 0 0 0 0 84 dc 5 8 ff ff ff ff
after playing a bit with yenta_socket I came to this patch which
makes both cards work flawlessly:
--- 2.6.orig/drivers/pcmcia/o2micro.h 2005-07-15 23:43:42.556540296 -0400
+++ 2.6/drivers/pcmcia/o2micro.h2005-07-16 00:23:16.552638032 -0400
@@ -138,6 +138,8 @@
printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a,
b);
switch (socket->dev->device) {
+ case PCI_DEVICE_ID_O2_6812:
+ config_writeb(socket, 0xD4, 0);
case PCI_DEVICE_ID_O2_6832:
printk(KERN_INFO "Yenta O2: old bridge, not enabling
read prefetch / write burst\n");
break;
in oz6812 datasheet there's nothing about read prefetch and write burst
which o2micro_override() enables (and hey, if 6832 is an old bridge, I
guess 6812 is even older :).
while playing with the only control2 register bit described in datasheet
(14th, SCLK_ENABLE) I discovered that zeroing the first byte made the
driver work with both cards (the first 13 bits are described as reserved
for diagnostic test mode).
anyone (perhaps from O2Micro) knows what those bits are exactly or has a
better clue of what's going on here?
(if anyone finds useful, dmesg, ifconfig, /proc/interrupts, lspci -vvv
are attached)
--
Aristeu
Linux version 2.6.11.6-pinguim2 ([EMAIL PROTECTED]) (gcc version 3.3.5 (Debian
1:3.3.5-8)) #6 Sun Apr 3 17:34:27 GMT+2 2005
BIOS-provided physical RAM map:
BIOS-e820: - 0009fc00 (usable)
BIOS-e820: 0009fc00 - 000a (reserved)
BIOS-e820: 000f - 0010 (reserved)
BIOS-e820: 0010 - 0fff (usable)
BIOS-e820: 0fff - 0fff8000 (ACPI data)
BIOS-e820: 0fff8000 - 1000 (ACPI NVS)
BIOS-e820: - 0001 (reserved)
255MB LOWMEM available.
On node 0 totalpages: 65520
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 61424 pages, LIFO batch:14
HighMem zone: 0 pages, LIFO batch:1
DMI 2.1 present.
ACPI: RSDP (v000 Acer ) @ 0x000fe030
ACPI: RSDT (v001 Acer AN3400x0001 Acer 0x) @ 0x0fff
ACPI: FADT (v001 Acer AN3400x0001 Acer 0x) @ 0x0fff0054
ACPI: BOOT (v001 Acer AN3400x0001 Acer 0x) @ 0x0fff002c
ACPI: DSDT (v001 Acer AN340 0x1000 MSFT 0x010c) @ 0x
Allocating PCI resources starting at 1000 (gap: 1000:efff)
Built 1 zonelists
Kernel command line: root=/dev/hda2 ro vga=787 resume=/dev/hda3
__iounmap: bad address c00fffd9
Local APIC disabled by BIOS -- you can enable it with "lapic"
mapped APIC to d000 (01201000)
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 16384 bytes)
Detected 499.589 MHz processor.
Using tsc for high-res timesource
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 255172k/262080k available (2076k kernel code, 6336k reserved, 1159k
data, 264k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay loop... 985.08 BogoMIPS (lpj=492544)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
CPU: After generic identify, caps: 0383f9ff
CPU: After vendor identify, caps: 0383f9ff
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 256K
CPU: After all inits, caps: 0383f9ff 0040
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU: Intel Pentium III (Coppermine) stepping 03
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0620)
NET: Registered protocol family 16
EISA bus registered
PCI: PCI BIOS revision 2.10 entry at 0xf0200, last bus=1
PCI: Using configuration type 1
mtrr: v2.0 (20020519)
ACPI: Subsystem revision 20050211
oz6812, yenta_socket and madwifi
Hi,
for some time I was unable to use Atheros based cards on my
notebook (O2Micro oz6812 Cardbus controller) because of lots
of rx packets getting dropped by frame errors. running ping I got
this: (~1m from access point)
PING 192.168.67.1 (192.168.67.1): 56 data bytes
64 bytes from 192.168.67.1: icmp_seq=0 ttl=64 time=1.5 ms
wrong data byte #20 should be 0x14 but was 0x0
0 10 18 1 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29
2a 2b 2c 2d 2e 2f 30 31 32 33
34 35 36 37 0 0 0 0 84 dc 5 8 ff ff ff ff
64 bytes from 192.168.67.1: icmp_seq=4 ttl=64 time=1.3 ms
wrong data byte #20 should be 0x14 but was 0x0
0 10 18 1 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29
2a 2b 2c 2d 2e 2f 30 31 32 33
34 35 36 37 0 0 0 0 84 dc 5 8 ff ff ff ff
after playing a bit with yenta_socket I came to this patch which
makes both cards work flawlessly:
--- 2.6.orig/drivers/pcmcia/o2micro.h 2005-07-15 23:43:42.556540296 -0400
+++ 2.6/drivers/pcmcia/o2micro.h2005-07-16 00:23:16.552638032 -0400
@@ -138,6 +138,8 @@
printk(KERN_INFO Yenta O2: res at 0x94/0xD4: %02x/%02x\n, a,
b);
switch (socket-dev-device) {
+ case PCI_DEVICE_ID_O2_6812:
+ config_writeb(socket, 0xD4, 0);
case PCI_DEVICE_ID_O2_6832:
printk(KERN_INFO Yenta O2: old bridge, not enabling
read prefetch / write burst\n);
break;
in oz6812 datasheet there's nothing about read prefetch and write burst
which o2micro_override() enables (and hey, if 6832 is an old bridge, I
guess 6812 is even older :).
while playing with the only control2 register bit described in datasheet
(14th, SCLK_ENABLE) I discovered that zeroing the first byte made the
driver work with both cards (the first 13 bits are described as reserved
for diagnostic test mode).
anyone (perhaps from O2Micro) knows what those bits are exactly or has a
better clue of what's going on here?
(if anyone finds useful, dmesg, ifconfig, /proc/interrupts, lspci -vvv
are attached)
--
Aristeu
Linux version 2.6.11.6-pinguim2 ([EMAIL PROTECTED]) (gcc version 3.3.5 (Debian
1:3.3.5-8)) #6 Sun Apr 3 17:34:27 GMT+2 2005
BIOS-provided physical RAM map:
BIOS-e820: - 0009fc00 (usable)
BIOS-e820: 0009fc00 - 000a (reserved)
BIOS-e820: 000f - 0010 (reserved)
BIOS-e820: 0010 - 0fff (usable)
BIOS-e820: 0fff - 0fff8000 (ACPI data)
BIOS-e820: 0fff8000 - 1000 (ACPI NVS)
BIOS-e820: - 0001 (reserved)
255MB LOWMEM available.
On node 0 totalpages: 65520
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 61424 pages, LIFO batch:14
HighMem zone: 0 pages, LIFO batch:1
DMI 2.1 present.
ACPI: RSDP (v000 Acer ) @ 0x000fe030
ACPI: RSDT (v001 Acer AN3400x0001 Acer 0x) @ 0x0fff
ACPI: FADT (v001 Acer AN3400x0001 Acer 0x) @ 0x0fff0054
ACPI: BOOT (v001 Acer AN3400x0001 Acer 0x) @ 0x0fff002c
ACPI: DSDT (v001 Acer AN340 0x1000 MSFT 0x010c) @ 0x
Allocating PCI resources starting at 1000 (gap: 1000:efff)
Built 1 zonelists
Kernel command line: root=/dev/hda2 ro vga=787 resume=/dev/hda3
__iounmap: bad address c00fffd9
Local APIC disabled by BIOS -- you can enable it with lapic
mapped APIC to d000 (01201000)
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 16384 bytes)
Detected 499.589 MHz processor.
Using tsc for high-res timesource
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 255172k/262080k available (2076k kernel code, 6336k reserved, 1159k
data, 264k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay loop... 985.08 BogoMIPS (lpj=492544)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
CPU: After generic identify, caps: 0383f9ff
CPU: After vendor identify, caps: 0383f9ff
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 256K
CPU: After all inits, caps: 0383f9ff 0040
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU: Intel Pentium III (Coppermine) stepping 03
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0620)
NET: Registered protocol family 16
EISA bus registered
PCI: PCI BIOS revision 2.10 entry at 0xf0200, last bus=1
PCI: Using configuration type 1
mtrr: v2.0 (20020519)
ACPI: Subsystem revision 20050211
ACPI:
