[PATCH v3 10/20] mtd: nand: qcom: erased codeword detection configuration

The NAND controller returns ECC failure during read of completely erased codeword. The NAND controller has hardware functionality to detect erased codeword in case of BCH ECC algorithm. The NAND_ERASED_CW_DETECT_CFG register controls the erased codeword/page detection controller. This register

[PATCH v3 04/20] mtd: nand: qcom: add and initialize QPIC DMA resources

1. QPIC NAND controller uses 3 BAM channels: command, data tx and data rx while EBI2 NAND controller uses only single ADM channel. 2. CRCI is only required for ADM DMA and it's not required for BAM DMA. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu

[PATCH v3 12/20] mtd: nand: qcom: QPIC data descriptors handling

1. Add the data descriptor preparation function which will be used only by BAM DMA for forming the data SGL’s 2. Add clear BAM transaction and call it before every new request 3. Check DMA mode for ADM or BAM and call the appropriate descriptor formation function. Signed-off-by: Abhishek

[PATCH v3 11/20] mtd: nand: qcom: enable BAM or ADM mode

1. DM_EN is only required for EBI2 NAND controller which uses ADM 2. BAM mode will be disabled after power on reset which needs to be enabled before starting any BAM transfers. Signed-off-by: Abhishek Sahu --- drivers/mtd/nand/qcom_nandc.c | 17 ++--- 1

[PATCH v3 15/20] mtd: nand: qcom: support for command descriptor formation

1. Add the function for command descriptor preparation which will be used only by BAM DMA and it will form the DMA descriptors containing command elements 2. DMA_PREP_CMD flag should be used for forming command DMA descriptors Signed-off-by: Abhishek Sahu ---

Re: [PATCH] Enable reset attack mitigation

On Sat, Aug 05, 2017 at 09:35:22AM -0700, Matthew Garrett wrote: > On Sat, Aug 5, 2017 at 2:50 AM, Ard Biesheuvel > wrote: > > On 4 August 2017 at 22:20, Matthew Garrett wrote: > > > If a machine is reset while secrets are present in RAM, it may be >

Re: [PATCH 3.18 00/50] 3.18.64-stable review

On 08/05/2017 08:43 AM, Greg Kroah-Hartman wrote: On Sat, Aug 05, 2017 at 08:02:17AM +0200, Willy Tarreau wrote: On Sat, Aug 05, 2017 at 07:55:11AM +0200, Willy Tarreau wrote: On Fri, Aug 04, 2017 at 07:51:07PM -0700, Greg Kroah-Hartman wrote: On Fri, Aug 04, 2017 at 07:46:57PM -0700, Greg

Re: [PATCH 2/2] mm,fork: introduce MADV_WIPEONFORK

Hi Rik, [auto build test ERROR on linus/master] [also build test ERROR on v4.13-rc3 next-20170804] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

[PATCH 3/4] thermal: exynos: constify thermal_zone_of_device_ops structures

The thermal_zone_of_device_ops structure is only passed as the fourth argument to thermal_zone_of_sensor_register, which is declared as const. Thus the thermal_zone_of_device_ops structure itself can be const. Done with the help of Coccinelle. // @r disable optional_qualifier@ identifier i;

[PATCH 2/4] thermal: zx2967: constify thermal_zone_of_device_ops structures

The thermal_zone_of_device_ops structure is only passed as the fourth argument to thermal_zone_of_sensor_register, which is declared as const. Thus the thermal_zone_of_device_ops structure itself can be const. Done with the help of Coccinelle. // @r disable optional_qualifier@ identifier i;

[PATCH 1/4] thermal: qoriq: constify thermal_zone_of_device_ops structures

The thermal_zone_of_device_ops structure is only passed as the fourth argument to thermal_zone_of_sensor_register, which is declared as const. Thus the thermal_zone_of_device_ops structure itself can be const. Done with the help of Coccinelle. // @r disable optional_qualifier@ identifier i;

[PATCH 4/4] thermal: bcm2835: constify thermal_zone_of_device_ops structures

The thermal_zone_of_device_ops structure is only passed as the fourth argument to thermal_zone_of_sensor_register, which is declared as const. Thus the thermal_zone_of_device_ops structure itself can be const. Done with the help of Coccinelle. // @r disable optional_qualifier@ identifier i;

[PATCH 0/4] constify thermal_zone_of_device_ops structures

The thermal_zone_of_device_ops structures are only passed as the fourth argument to thermal_zone_of_sensor_register, which is declared as const. Thus the thermal_zone_of_device_ops structures themselves can be const. Done with the help of Coccinelle. ---

[PATCH] ipmi: bt-i2c: fix call_kern.cocci warnings

Function handle_request called from bt_i2c_slave_cb with bt_slave->lock held but uses GFP_KERNEL. Replace GFP_KERNEL by GFP_ATOMIC. Generated by: scripts/coccinelle/locks/call_kern.cocci Fixes: acd0208e3557 ("ipmi: bt-i2c: added IPMI Block Transfer over I2C BMC side") CC: Brendan Higgins

Re: [PATCH] Enable reset attack mitigation

On Sat, Aug 5, 2017 at 10:34 AM, Lukas Wunner wrote: > Just an innocent question from a bystander, what's the downside of > unconditionally requesting that memory be overwritten? Does it > prolong reboot noticeably? Yes, it's just to avoid stalling reboot for as long as it

fs/binfmt_flat.c:828:9: error: void value not ignored as it ought to be

Hi Al, FYI, the error/warning still remains. tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 0fdd951c9bef93637d5af036851e7a5632fbd6c3 commit: 468138d78510688fb5476f98d23f11ac6a63229a binfmt_flat: flat_{get,put}_addr_from_rp() should be able to fail

Hello dear,its me Titi

Hello and good evening,my name is Titi,i am a young and single girl looking for friends, and i will like to be your pen friend. Please get back to me through ( kambo4t...@gmail.com ),so that we can get to know each other with picture exchange and introduction.

[PATCH 2/4] parse-maintainers: Use perl hash references and specific filenames

Instead of reading STDIN and writing STDOUT, use specific filenames of MAINTAINERS and MAINTAINERS.new. Use hash references instead of global hash %hash so future modifications can read and write specific hashes to split up MAINTAINERS into multiple files using a script. Signed-off-by: Joe

[PATCH 1/4] parse-maintainers: Add section pattern sorting

Section [A-Z]: patterns are not currently in any required sorting order. Add a specific sorting sequence to MAINTAINERS entries. Sort F: and X: patterns in alphabetic order. The preferred section ordering is: SECTION HEADER M: Maintainers R: Reviewers P: Named persons without

[PATCH 4/4] scripts/move_maintainer_sections.bash

Move MAINTAINERS into a separate directory and reorder it. Separate various blocks of MAINTAINER sections into separate files. Signed-off-by: Joe Perches --- scripts/move_maintainer_sections.bash | 87 +++ 1 file changed, 87 insertions(+)

[PATCH 0/4] Scripted update of the MAINTAINERS files

MAINTAINERS is a very large file. Update the parse-maintainer script to use specific filenames to allow scripting of the moving of various bits into separate files. Add a bash script to move various bits into multiple files. Joe Perches (4): parse-maintainers: Add section pattern sorting

[PATCH 3/4] parse-maintainers: Move matching sections from MAINTAINERS

Allow any number of command line arguments to match either the section header or the section contents and create new files. Create MAINTAINERS.new and SECTION.new. This allows scripting of the movement of various sections from MAINTAINERS. Signed-off-by: Joe Perches ---

Re: [linux-sunxi] [PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote: > The configuration struct of A64 EMMC(MMC2) compatible used to > have the needs_new_timings variable missing, which lead to NULL > pointer dereference now when trying to set up the old timings mode, as > the old timings mode doesn't

[PATCH 1/2] reset: uniphier: remove sLD3 SoC support

This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada --- .../devicetree/bindings/reset/uniphier-reset.txt | 2 - drivers/reset/reset-uniphier.c | 48 -- 2 files changed, 16

[PATCH 2/2] reset: uniphier: do not use per-SoC macro for system reset block

This macro turned out not so useful as I had expected. Hardware engineers said they would change reset bit assignments for every SoC going forward. This means we can not share the macros among SoCs. Just use primitive macros. Signed-off-by: Masahiro Yamada ---

[PATCH 0/2] reset: uniphier: UniPhier reset data update for v4.14

Hi Philipp, Here are UniPhier SoCs updates for v4.14. - Remove old SoC support - Remove useless macros Masahiro Yamada (2): reset: uniphier: remove sLD3 SoC support reset: uniphier: do not use per-SoC macro for system reset block .../devicetree/bindings/reset/uniphier-reset.txt | 2

Re: [PATCH v2] mmc: mmci_qcom_dml: include mmci_qcom_dml.h and fix #ifdef

Hi Arnd, 2017-08-05 7:10 GMT+09:00 Arnd Bergmann : > On Fri, Aug 4, 2017 at 3:34 PM, Masahiro Yamada > wrote: >> Include mmci_qcom_dml.h from mmci_qcom_dml.c to fix the following >> sparse warnings: >> >> CHECK drivers/mmc/host/mmci_qcom_dml.c

Re: [PATCH v2 0/4] ipmi: bt-i2c: added IPMI Block Transfer over I2C

On 08/04/2017 08:18 PM, Brendan Higgins wrote: This patchset introduces IPMI Block Transfer over I2C (BT-I2C), which has the same semantics as IPMI Block Transfer except it done over I2C. For the OpenBMC people, this is based on an RFC:

Re: [PATCH] intel-vbtn: match power button on press rather than release

On Saturday, August 5, 2017 10:57:53 PM CEST Darren Hart wrote: > On Sat, Aug 05, 2017 at 01:30:20AM +0200, Rafael Wysocki wrote: > > On Friday, August 4, 2017 7:29:53 PM CEST Darren Hart wrote: > > > On Fri, Aug 04, 2017 at 12:00:06PM -0500, Mario Limonciello wrote: > > > > This fixes a problem

Re: [PATCH 1/2] ext4: fix warning about stack corruption

On Tue, Aug 01, 2017 at 02:04:03PM +0200, Arnd Bergmann wrote: > There is one remaining issue with the function that I'm not addressing > here: With s_blocksize_bits==16, we don't actually print the last two > members of the array, as we loop though just the first 14 members. > This could be

Re: [PATCH 0/2] Updated SPCR quirks for Moonshot/Mustang

On Fri, 2017-08-04 at 22:49 +0100, Graeme Gregory wrote: > A couple of patches to build on the SPCR quirks support already upstreamed. > > 1 - Moonshot m400 cartridge has the same soc but ACPI tables have different > HPe specific headers so extend quirk to understand those too. > > 2 - Relevant

Re: [PATCH] ext4: inplace xattr block update fails to deduplicate blocks

On Sat, Jul 15, 2017 at 02:49:05AM -0700, Andreas Dilger wrote: > On Jul 14, 2017, at 5:25 PM, Tahsin Erdogan wrote: > > > > When an xattr block has a single reference, block is updated inplace > > and it is reinserted to the cache. Later, a cache lookup is performed > > to

Re: [linux-sunxi] [PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

于 2017年8月6日 GMT+08:00 上午10:39:54, Chen-Yu Tsai 写到: >On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote: >> The configuration struct of A64 EMMC(MMC2) compatible used to >> have the needs_new_timings variable missing, which lead to NULL >> pointer dereference now when

Re: [PATCH] lib/mpi: fix build with clang

Hi Herbert, This still applies fine on 4.13-rc3, any chance to get it merged through one of your trees? -- Stefan On 2017-04-19 20:40, Stefan Agner wrote: > Use just @ to denote comments which works with gcc and clang. > Otherwise clang reports an escape sequence error: > error: invalid %

Re: [PATCH 2/2] io_getevents: Use timespec64 to represent timeouts

> I guess these two functions are small enough that they could be merged > into one, saving a few lines. Then again, fs/aio.c seems to generally use > fairly short functions doing not too much at once, so your approach maybe > fits better with the style of the subsystem. I don't see a problem

Re: [PATCH] ext4: backward compatibility support for Lustre ea_inode implementation

Andreas, Emoly, I'd appreciate your thoughts; what do you think about Tahsin's patch. Could you give it a try on a file system created with Lustre and let me know how it works for you? Many thanks!! - Ted On Mon, Jul 24, 2017 at 01:13:08PM -0700, Tahsin

Re: [PATCH v3 5/6] PCI: mediatek: Add new generation controller support

Hi Honghui, If you plan to send next version, then I would suggest some minor changes. On Fri, 2017-08-04 at 20:06 +0800, honghui.zh...@mediatek.com wrote: > +#define PCIE_CRSTB BIT(3) > +#define PCIE_PERSTB BIT(8) > +#define PCI_LINKDOWN_RST_EN GENMASK(15, 13)

Re: [linux-sunxi] [PATCH 1/2] mmc: sunxi: fix support for new timings mode only SoCs

On Sat, Aug 5, 2017 at 5:35 AM, Icenowy Zheng wrote: > The A83T MMC support code introduces the timings mode switch, however > such a switch doesn't exist on new SoCs with only new timings mode. > > Only execute the switch if the SoC really have the timings mode switch, > to fix

Re: [PATCH] ext4: remove unused mode parameter

On Thu, Jul 20, 2017 at 02:40:37AM -0700, Tahsin Erdogan wrote: > ext4_alloc_file_blocks() does not use its mode parameter. Remove it. > > Signed-off-by: Tahsin Erdogan Thanks, applied. - Ted

Re: [RFC 01/16] NOVA: Documentation

There is nothing impossible COW for mapped files, but it is not a good match for the expected usage model for DAX. The idea is that programs can mmap files and the build interesting data structures in them, just like they do in DRAM. This means lots of small updatEs, and that would be very

Re: [PATCH v3 3/6] dt-bindings: add binding for Sitronix ST7586 display panels

On 08/04/2017 02:39 PM, Laurent Pinchart wrote: Hi David, On Friday 04 Aug 2017 10:51:37 David Lechner wrote: On 08/04/2017 09:54 AM, Laurent Pinchart wrote: On Thursday 03 Aug 2017 17:33:47 David Lechner wrote: This adds a new binding for Sitronix ST7586 display panels. Using lego as the

[PATCH] staging: olpc_dcon: Fix coding style issue caught bycheckpatch.pl related to function name in debug print

Replace hard-coded function names in strings with "%s", __func__ in the olpc_dcon.c file. Issue found by checkpatch.pl. Signed-off-by: Marvin Zhang --- drivers/staging/olpc_dcon/olpc_dcon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH] sched: debug: use task_pid_vnr in /proc/$pid/sched

On 2017-08-06 02:52, Aleksa Sarai wrote: It appears as though the addition of the PID namespace did not update the output code for /proc/$pid/sched, which made it trivial to figure out whether a process was inside _pid_ns from userspace (making container detection trivial[1]). This lead to

Re: [PATCH 2/2] mm,fork: introduce MADV_WIPEONFORK

Hi Rik, [auto build test ERROR on linus/master] [also build test ERROR on v4.13-rc3 next-20170804] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH] samples/bpf: Fix cross compiler error with bpf sample

Hi Daniel, >>> >>> So the only arch that sets __ARCH_WANT_SYSCALL_DEPRECATED >>> is score: >>> >>>$ git grep -n __ARCH_WANT_SYSCALL_DEPRECATED >>>arch/score/include/uapi/asm/unistd.h:7:#define >>> __ARCH_WANT_SYSCALL_DEPRECATED >>>include/uapi/asm-generic/unistd.h:837:#ifdef >>>

[PATCH net-next v2 1/3] net: dsa: remove useless argument in legacy setup

dsa_switch_alloc() already assigns ds-dev, which can be used in dsa_switch_setup_one and dsa_cpu_dsa_setups instead of requiring an additional struct device argument. Signed-off-by: Vivien Didelot --- net/dsa/legacy.c | 16 1 file changed, 8

[PATCH net-next v2 2/3] net: dsa: remove useless args of dsa_cpu_dsa_setup

dsa_cpu_dsa_setup currently takes 4 arguments but they are all available from the dsa_port argument. Remove all others. Signed-off-by: Vivien Didelot --- net/dsa/dsa.c | 10 +- net/dsa/dsa2.c | 4 ++-- net/dsa/dsa_priv.h | 3 +--

[PATCH v3 02/20] mtd: nand: qcom: support for NAND controller properties

Currently driver data is being assigned directly with ECC modes. Now, the plan is to add more NAND controller versions which will have different properties. This patch reorganizes the current driver data assignment by creating NAND controller properties structure which will contain all properties

[PATCH v3 03/20] mtd: nand: qcom: add bam property for QPIC NAND controller

The current driver only supports EBI2 NAND controller which uses ADM DMA. The latest QCOM SoC uses QPIC NAND controller with BAM DMA. NAND registers and programming sequence are same for EBI2 and QPIC NAND so the same driver can support QPIC NAND also by adding the BAM DMA support. This patch adds

kvm_intel fails to load on Conroe CPUs running Linux 4.12

Dear linux developers, since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module does not load correctly anymore. "Modprobing" the kernel module gives an Input/Output error. It seems to be related to the CPU architecture and (to my knowledge) affects Conroe CPUs. I did a bisect and

Re: [PATCH 2/2] io_getevents: Use timespec64 to represent timeouts

On Sat, Aug 5, 2017 at 6:12 AM, Deepa Dinamani wrote: > struct timespec is not y2038 safe. Use y2038 safe > struct timespec64 to represent timeouts. > The system call interface itself will be changed as > part of different series. > > Timeouts will not really need more

Re: [PATCH net-next 1/3] net: dsa: assign switch device in legacy code

Hi Andrew, Andrew Lunn writes: >> @@ -251,8 +251,9 @@ dsa_switch_setup(struct dsa_switch_tree *dst, struct >> net_device *master, >> ds->cd = cd; >> ds->ops = ops; >> ds->priv = priv; >> +ds->dev = parent; > > Is this even needed? dsa_switch_alloc() does

Re: [PATCH] intel-vbtn: match power button on press rather than release

On Sat, Aug 05, 2017 at 01:30:20AM +0200, Rafael Wysocki wrote: > On Friday, August 4, 2017 7:29:53 PM CEST Darren Hart wrote: > > On Fri, Aug 04, 2017 at 12:00:06PM -0500, Mario Limonciello wrote: > > > This fixes a problem where the system gets stuck in a loop > > > unable to wakeup via power

[PATCH v3 00/20] Add QCOM QPIC NAND support

* v3: 1. Removed the patches already applied to linux-next and rebased the remaining patches on [1] 2. Reordered the patches and put the BAM DMA changes [2] dependent patches and compatible string patches in last 3. Removed the register offsets array and used the dev_cmd offsets 4. Changed

[PATCH v3 09/20] mtd: nand: qcom: support for read location registers

In EBI2, all codeword data will be read in FLASH_BUF_ACC buffer and ADM will copy the data from source (FLASH_BUF_ACC) to destination (memory for data read). In QPIC, there is no FLASH_BUF_ACC and all the codeword data will held in QPIC BAM FIFO buffers. It provides multiple READ_LOCATION

[PATCH v3 14/20] mtd: nand: qcom: add command elements in BAM transaction

All the QPIC register read/write through BAM DMA requires command descriptor which contains the array of command elements. Signed-off-by: Abhishek Sahu --- drivers/mtd/nand/qcom_nandc.c | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git

[PATCH v3 06/20] mtd: nand: qcom: allocate BAM transaction

- The BAM transaction is the core data structure which will be used for all the data transfers in QPIC NAND. Since the core framework in nand_base.c is serializing all the NAND requests so allocating BAM transaction before every transfer will be overhead. The memory for it be allocated during

[PATCH v3 08/20] mtd: nand: qcom: support for passing flags in transfer functions

The BAM has multiple flags to control the transfer. This patch adds flags parameter in register and data transfer functions and modifies all these functions call with appropriate flags using following rule 1. Read and write can’t go in single command descriptor so separate SGL should be used.

[PATCH v3 07/20] mtd: nand: qcom: add BAM DMA descriptor handling

1. prepare_bam_async_desc is the function which will call all the DMA API’s. It will fetch the outstanding scatter gather list for passed channel and will do the DMA descriptor formation. The DMA flag is dependent upon the type of channel. 2. For ADM DMA, the descriptor is being formed

[PATCH v3 05/20] mtd: nand: qcom: DMA mapping support for register read buffer

The EBI2 NAND controller directly remaps register read buffer with dma_map_sg and DMA address of this buffer will be passed to DMA API’s. While, on QPIC NAND controller, which uses BAM DMA, we read the controller registers by preparing a BAM command descriptor. This command descriptor requires the

[PATCH v3 13/20] mtd: nand: qcom: support for different DEV_CMD register offsets

The FLASH_DEV_CMD registers starting offset is not same in different QPIC NAND controller versions. This patch adds the starting offset in NAND controller properties and uses the same for calculating the actual offset of these registers. Signed-off-by: Abhishek Sahu ---

[PATCH v3 17/20] dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation

1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0 which uses BAM DMA Engine while IPQ806x uses EBI2 NAND which uses ADM DMA Engine. 2. QPIC NAND will 3 BAM channels: command, data tx and data rx while EBI2 NAND uses only single ADM channel. 3. CRCI is only required for ADM

[PATCH v3 20/20] mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller

Add the compatible string for IPQ8074 QPIC NAND controller version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers starting offset is 0x7000. Signed-off-by: Abhishek Sahu --- drivers/mtd/nand/qcom_nandc.c | 10 ++ 1 file changed, 10 insertions(+) diff

[PATCH v3 19/20] mtd: nand: qcom: Support for IPQ4019 QPIC NAND controller

Add the compatible string for IPQ4019 QPIC NAND controller version 1.4.0 which uses BAM DMA. Signed-off-by: Abhishek Sahu --- drivers/mtd/nand/qcom_nandc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/nand/qcom_nandc.c

[PATCH v3 16/20] dt-bindings: qcom_nandc: fix the ipq806x device tree example

1. Correct the compatible string for IPQ806x 2. Change the NAND controller and NAND chip nodes name for more clarity. Signed-off-by: Abhishek Sahu --- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH v3 18/20] dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation

Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0 which uses BAM DMA Engine. Signed-off-by: Abhishek Sahu --- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH] sched: debug: use task_pid_vnr in /proc/$pid/sched

It appears as though the addition of the PID namespace did not update the output code for /proc/$pid/sched, which made it trivial to figure out whether a process was inside _pid_ns from userspace (making container detection trivial[1]). This lead to situations such as: % unshare -pf head -n1

Brauchen sie schnell Geld? Ich helfe ihnen weiter!

Ich bin reich und fühle mich verpflichtet Menschen in Not eine zweite Chance zu geben. Sie werden keine Überraschungen erleben, es ist kein Betrug. Kontaktieren sie mich, geben sie an wieviel Geld sie leihen möchten. Ich übersende ihnen sofort welche Möglichkeiten sie haben.

Re: [PATCH v3 4/6] drm/tinydrm: add support for LEGO MINDSTORMS EV3 LCD

Den 04.08.2017 00.33, skrev David Lechner: LEGO MINDSTORMS EV3 has an LCD with a ST7586 controller. This adds a new module for the ST7586 controller with parameters for the LEGO MINDSTORMS EV3 LCD display. Signed-off-by: David Lechner --- MAINTAINERS

Re: [PATCH v3 4/6] drm/tinydrm: add support for LEGO MINDSTORMS EV3 LCD

Den 05.08.2017 20.19, skrev Noralf Trønnes: Den 04.08.2017 00.33, skrev David Lechner: LEGO MINDSTORMS EV3 has an LCD with a ST7586 controller. This adds a new module for the ST7586 controller with parameters for the LEGO MINDSTORMS EV3 LCD display. Signed-off-by: David Lechner

Re: [PATCH 1/2] select: Use get/put_timespec64

On Sat, Aug 5, 2017 at 6:12 AM, Deepa Dinamani wrote: > Usage of these apis and their compat versions makes > the syscalls: select family of syscalls and their > compat implementations simpler. > > This is a preparatory patch to isolate data conversions to > struct

[PATCH] Fix compat_sys_sigpending breakage introduced by v4.13-rc1~6^2~12

The latest change of compat_sys_sigpending has broken it in two ways. First, it tries to write 4 bytes more than userspace expects: sizeof(old_sigset_t) == sizeof(long) == 8 instead of sizeof(compat_old_sigset_t) == sizeof(u32) == 4. Second, on big endian architectures these bytes are being

Re: [PATCH v1 2/3] ipmi: bt-i2c: added IPMI Block Transfer over I2C host side

Hi Brendan, [auto build test ERROR on char-misc/char-misc-testing] [also build test ERROR on v4.13-rc3 next-20170804] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

[PATCH v3 01/20] mtd: nand: qcom: program NAND_DEV_CMD_VLD register

The NAND page read fails without complete boot chain since NAND_DEV_CMD_VLD value is not proper. The default power on reset value for this register is 0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID The READ_START_VALID should be enabled for sending PAGE_READ command.

Re: [PATCH] Enable reset attack mitigation

On Sat, Aug 5, 2017 at 2:50 AM, Ard Biesheuvel wrote: > On 4 August 2017 at 22:20, Matthew Garrett wrote: >> If a machine is reset while secrets are present in RAM, it may be >> possible for code executed after the reboot to extract those secrets >>

[PATCH net-next v2 3/3] net: dsa: remove useless args of dsa_slave_create

dsa_slave_create currently takes 4 arguments while it only needs the related dsa_port and its name. Remove all other arguments. Signed-off-by: Vivien Didelot --- net/dsa/dsa2.c | 2 +- net/dsa/dsa_priv.h | 3 +-- net/dsa/legacy.c | 2 +-

[PATCH net-next v2 0/3] net: dsa: remove useless arguments

Several DSA core setup functions take many arguments, mostly because of the legacy code. This patch series removes the useless args of these functions, where either the dsa_switch or dsa_port argument is enough. Changes in v2: - ds->dev is already assigned by dsa_switch_alloc Vivien Didelot

Re: linux-next: Signed-off-by missing for commit in the drivers-x86 tree

On Thu, Aug 03, 2017 at 08:50:06AM -0700, Darren Hart wrote: > On Wed, Aug 02, 2017 at 06:06:20PM -0700, Linus Torvalds wrote: > > On Wed, Aug 2, 2017 at 5:28 PM, Stephen Rothwell > > wrote: > > > > > > I would say that if you rebase someone's commit(s), then you are on

Re: [PATCH v2] ext4: make xattr inode reads faster

On Sun, Jul 16, 2017 at 11:20:12PM -0700, Tahsin Erdogan wrote: > ext4_xattr_inode_read() currently reads each block sequentially while > waiting for io operation to complete before moving on to the next > block. This prevents request merging in block layer. > > Add a ext4_bread_batch() function

Re: [PATCH 1/5] edac: synopsys: Add platform specific structures ddrc controller

On Fri, Aug 04, 2017 at 02:00:23PM +0200, Michal Simek wrote: > From: Naga Sureshkumar Relli That subject: Subject: [PATCH 1/5] edac: synopsys: Add platform specific structures ddrc controller doesn't read like a proper sentence to me. > This patch adds

Re: [PATCH] sched: debug: use task_pid_vnr in /proc/$pid/sched

Aleksa Sarai writes: > On 2017-08-06 02:52, Aleksa Sarai wrote: >> It appears as though the addition of the PID namespace did not update >> the output code for /proc/$pid/sched, which made it trivial to figure >> out whether a process was inside _pid_ns from userspace (making >>

drivers/clocksource/timer-of.h:35:28: error: field 'clkevt' has incomplete type

Hi Daniel, FYI, the error/warning still remains. tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 0fdd951c9bef93637d5af036851e7a5632fbd6c3 commit: dc11bae78529526605c5c45c369c9512fd012093 clocksource/drivers: Add timer-of common init routine date: 8

[PATCH v2] sched: debug: use task_pid_nr_ns in /proc/$pid/sched

It appears as though the addition of the PID namespace did not update the output code for /proc/*/sched, which resulted in it providing PIDs that were not self-consistent with the /proc mount. This additionally made it trivial to detect whether a process was inside _pid_ns from userspace (making

include/linux/kernel.h:860:32: error: dereferencing pointer to incomplete type 'struct clock_event_device'

Hi Ian, FYI, the error/warning still remains. tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 0fdd951c9bef93637d5af036851e7a5632fbd6c3 commit: c7acec713d14c6ce8a20154f9dfda258d6bcad3b kernel.h: handle pointers to arrays better in container_of() date:

Re: [PATCH v3 3/5] ACPI: Introduce DMA ranges parsing

Hi Lorenzo, [auto build test ERROR on pm/linux-next] [also build test ERROR on v4.13-rc3 next-20170804] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH] ARM64: dts: meson-gx: Use correct mmc clock source 0

Hi Jerome, [auto build test ERROR on robh/for-next] [also build test ERROR on v4.13-rc3 next-20170804] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH 1/1] ext4: correcting copy paste error.

On Mon, Jul 17, 2017 at 11:37:44AM +0530, Maninder Singh wrote: > Error reported by static tool for copy paste > issue, fixing the same. > > Signed-off-by: Maninder Singh > Signed-off-by: Vaneet Narang Thanks, applied.

Re: [PATCH 3/3] drm: Add CRTC_GET_SEQUENCE and CRTC_QUEUE_SEQUENCE ioctls [v2]

Daniel Vetter writes: > Since I missed all the details Michel spotted, so I'll defer to his r-b. > Also, before merging we need the userspace user. Do we have e.g. > -modesetting patch for this, fully reviewed for merging, just as > demonstration? Well, given that we'll have to

Re: [PATCH 3/3] drm: Add CRTC_GET_SEQUENCE and CRTC_QUEUE_SEQUENCE ioctls [v2]

Michel Dänzer writes: > [...] > >> +#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x0002 /* Use >> next sequence if we've missed */ > > Do you have userspace making use of DRM_CRTC_SEQUENCE_NEXT_ON_MISS? If > not, drop it. I added this so that the new ioctl

hotplug support for arch/arc/plat-eznps platform

I'm adding hot-plug support for the above arch and ran into performance issue with execution of partition_sched_domains () - About 0.5 sec per cpu, which is unacceptable with the arch supported 4k cpus. To my limited understanding, on the plat-eznps arch, where each cpu is always running a

[PATCH] s390/crypto: make cca_public_sec and cca_token_hdr const

Declare cca_public_sec and cca_token_hdr structures as const as they are only used during copy operations. Signed-off-by: Bhumika Goyal --- drivers/s390/crypto/zcrypt_cca_key.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

Re: [ANNOUNCE] v4.11.12-rt9

On Fri, 2017-08-04 at 19:38 +0200, Sebastian Andrzej Siewior wrote: > Dear RT folks! > > I'm pleased to announce the v4.11.12-rt9 patch set. > > Changes since v4.11.12-rt8: > > - CPU hotplug could be rock solid now. Yes. The rewrite of the hotplug > related parts for RT including

Re: [PATCH 4.4 00/91] 4.4.80-stable review

On 08/04/2017 04:14 PM, Greg Kroah-Hartman wrote: This is the start of the stable review cycle for the 4.4.80 release. There are 91 patches in this series, all will be posted as a response to this one. If anyone has any issues with these being applied, please let me know. Responses should be

[PATCH 00/10] PCI: pci resource allocation test module

Read from data file and mask file, to build simulated data structure, and have pci_ops to use them. Extract calling for pci_create_root_bus, scan_child_bus, resource survey and resource assign ... to see if those functions work as expected with simulated data. mask is with rw bits on pci

[PATCH 01/10] PCI: avoid arch_remove_reservations() for PCI_TEST

arch_remove_reservations will clip out with e820 from host that kernel running, that will cause failure from PCI_TEST from simulated data. PCI_TEST has different iomem resource instead iomem_resource, so check if iomem_resource is related to avoid calling arch_remove_reservations()

Re: [PATCH v8 1/4] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING

On 2017/8/5 5:06, Casey Leedom wrote: > | From: Ding Tianhong > | Sent: Thursday, August 3, 2017 6:44 AM > | > | diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > | index 6967c6b..1e1cdbe 100644 > | --- a/drivers/pci/quirks.c > | +++ b/drivers/pci/quirks.c > |

[PATCH 03/10] PCI: export symbol for PCI_TEST module

We need to use them from pci_test module, so expose them. Signed-off-by: Yinghai Lu --- arch/x86/pci/i386.c | 1 + drivers/pci/setup-bus.c | 1 + kernel/resource.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c

Re: [PATCH] turbostat: Running on virtual machine is not supported

> Len, can you add an entry to RHMAINTAINERS for that? done. thx. Len 0001-MAINTAINERS-add-turbostat-utility.patch Description: Binary data

[PATCH 04/10] PCI: extend pci device match_driver state

Change it from false/true to -1/0/1. If it is set from -1, then it will never get change to 1 later. For PCI_TEST, the simulated device does not have realy function support except bus number and BAR setting. Signed-off-by: Yinghai Lu --- drivers/iommu/amd_iommu_init.c | 2

[PATCH 06/10] PCI: PCI_TEST simple data

Signed-off-by: Yinghai Lu --- drivers/pci/pci_test_data.txt | 24 drivers/pci/pci_test_mask.txt | 5 + 2 files changed, 29 insertions(+) create mode 100644 drivers/pci/pci_test_data.txt create mode 100644 drivers/pci/pci_test_mask.txt diff

  1   2   3   4   >