On 25/08/2017 18:53, Brijesh Singh wrote:
>>
>
> Thanks for the tip, I have expanded the patch to cover tdp cases and
> have verified
> that it works fine with SME enabled KVM. If you are okay with this then
> I can
> send patch.
>
> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
> index
From: Markus Elfring
Date: Fri, 25 Aug 2017 22:06:59 +0200
Fix a word in this description.
Signed-off-by: Markus Elfring
---
drivers/scsi/sg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/sg.c
On Fri, Aug 25, 2017 at 10:01:58AM -0500, Josh Poimboeuf wrote:
> On Fri, Aug 25, 2017 at 03:54:12PM +0200, Jiri Slaby wrote:
> > So now, there are two things:
> > 1) how to fix orc_find & unwind_init properly?
> > 2) how to generate an EMPTY hint for secondary_startup_64 and maybe
> > later REGS
On Fri, Aug 25, 2017 at 11:55 AM, John Stultz wrote:
> I'll look over the code again to see if I can catch anything by
> review. Worse case if we can't get any traction on this in a day or so
> I'll submit a revert.
I think I found the issue. In tk_update_ktime_data() I
On Thu, 24 Aug 2017 10:55:53 +0200 Michal Hocko wrote:
> > If we assume that the number of VMAs is going to increase over time,
> > then doing anything we can do to reduce the overhead of each VMA
> > during PSS collection seems like the right way to go, and that means
> >
On Thu, 17 Aug 2017 18:20:17 -0700 Shakeel Butt wrote:
> +linux-mm, linux-kernel
>
> On Thu, Aug 17, 2017 at 6:10 PM, Shakeel Butt wrote:
> > The fadvise() manpage is silent on fadvise()'s effect on
> > memory-based filesystems (shmem, hugetlbfs &
On Fri, Aug 25, 2017 at 05:41:13PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Fri, 25 Aug 2017 13:15:43 +0200
>
> Several update suggestions were taken into account
> from static source code analysis.
>
> Markus Elfring (14):
> Delete 11
The irq work interrupt vector is only installed when CONFIG_X86_LOCAL_APIC is
enabled, but the interrupt handler is compiled in unconditionally.
Compile the cruft out when the APIC is disabled.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/irq_work.h |8
The union inside of desc_struct which allows access to the raw u32 parts of
the descriptors. This raw access part is about to go away.
Replace the few code parts which access those fields.
Signed-off-by: Thomas Gleixner
Cc: Boris Ostrovsky
Cc:
IDT related code lives in different places. Create a new source file to
hold it.
Move the idt_tables and descriptors to it for a start. Follow up patches
will gradually move more code over.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/Makefile |2 +-
The GDT entry related code uses partially bitfields and macros which
initialize the two 16 bit parts of the entry by magic shift and mask
operations.
Clean it up and use the bitfields to initialize and access entries.
Signed-off-by: Thomas Gleixner
---
The platform IPI vector is only installed when the local APIC is enabled. All
users of it depend on the local APIC anyway.
Make the related code conditional on CONFIG_X86_LOCAL_APIC.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/entry_arch.h |3 +--
It's worth to avoid the extra irq_enter()/irq_exit() pair in the case that
the reschedule interrupt tracepoints are disabled.
Use the static key which indicates that exception tracing is enabled. For
now this key is global. It will be optimized in a later step.
Signed-off-by: Thomas Gleixner
Like the IDT descriptors the LDT/TSS descriptors are pointlessly different
on 32 and 64 bit.
Unify them and get rid of the duplicated code.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h | 26 +++---
On Thu, Aug 24, 2017 at 02:19:07PM +0530, Oza Pawandeep wrote:
> Host drivers have the requirement of implementing PCI hotplug
> based on the how their SOC supports PCI hotplug.
>
> Couple of properties have been added. the one to enable
> the hotplug feature itself, and the other caters to
> the
The first 32bits of gate struct are the same for 32 and 64 bit. The 32bit
version uses desc_struct and no designated data structure, so we need
different accessors for 32 and 64 bit. Aside of that the macros which are
necessary to build the 32bit gate descriptor are horrible to read.
Unify the
9a51544774a57fcb94994a61860a17f9e63a8d7b:
mtd: blkdevs: Fix mtd block write failure (2017-08-12 14:53:24 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mtd.git tags/for-linus-20170825
for you to fetch changes up to be3e83e3471cd0faff2c2d88fe9cfc73d9a9745a:
mtd: nand
On Wed, 23 Aug 2017, Pavel Tatashin wrote:
>
> - Use weak sched_clock_early() interface to determine time from boot in
> arch specific read_boot_clock64()
weak sched_clock_early() is not an interface. The weak implementation is
merily a place holder which can be overridden by a real
On Thu, Aug 17, 2017 at 12:03 PM, John Stultz wrote:
> In the earlier commit dad3f793f20f ("usb: dwc2: Make sure we
> disconnect the gadget state"), I was trying to fix up the
> fact that we somehow weren't disconnecting the gadget state,
> so that when the OTG port was
On Fri, Aug 25, 2017 at 2:49 PM, Andrew Morton
wrote:
> On Thu, 17 Aug 2017 18:20:17 -0700 Shakeel Butt wrote:
>
>> +linux-mm, linux-kernel
>>
>> On Thu, Aug 17, 2017 at 6:10 PM, Shakeel Butt wrote:
>> > The fadvise() manpage
Hi Will,
On 2017-08-15 11:40, Will Deacon wrote:
Hi Vikram,
On Thu, Aug 03, 2017 at 04:25:12PM -0700, Vikram Mulukutla wrote:
On 2017-07-31 06:13, Will Deacon wrote:
>On Fri, Jul 28, 2017 at 12:09:38PM -0700, Vikram Mulukutla wrote:
>>On 2017-07-28 02:28, Will Deacon wrote:
>>>On Thu, Jul
On Fri, Aug 25, 2017 at 9:19 AM, Helge Deller wrote:
> On 25.08.2017 18:16, Kirill A. Shutemov wrote:
>> On Fri, Aug 25, 2017 at 09:02:36AM -0700, Christoph Hellwig wrote:
>>> On Fri, Aug 25, 2017 at 06:58:03PM +0300, Kirill A. Shutemov wrote:
Not all archs are ready for this:
From: Markus Elfring
Date: Fri, 25 Aug 2017 21:48:11 +0200
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
On 25/08/2017 22:41, Brijesh Singh wrote:
>
>> Neither my version nor yours is correct. :) The right one has [0][i]
>> and [1][i] (I inverted the indices by mistake).
>>
>> With that change, you can include my
>>
>> Acked-by: Paolo Bonzini
>>
>
> Ingo,
>
> I assuming
On 08/25/2017 03:05 PM, Paolo Bonzini wrote:
On 25/08/2017 18:53, Brijesh Singh wrote:
Neither my version nor yours is correct. :) The right one has [0][i]
and [1][i] (I inverted the indices by mistake).
With that change, you can include my
Acked-by: Paolo Bonzini
On Fri, 25 Aug 2017, Thomas Gleixner wrote:
> On Fri, 25 Aug 2017, Vineet Gupta wrote:
> > On 06/15/2017 01:43 AM, Noam Camus wrote:
> > > From: Noam Camus
> > >
> > > Working with NPS400 we noticed that there is a possibility of L1
> > > interrupt nesting that may run out
If the worker thread continues getting work, it will hog the cpu and rcu
stall complains. Make it a good citizen. This is triggered in a loop
block device test.
Signed-off-by: Shaohua Li
---
kernel/kthread.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/kthread.c
No modular users.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/traps.c |1 -
1 file changed, 1 deletion(-)
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -83,7 +83,6 @@ gate_desc debug_idt_table[NR_VECTORS] __
gate_desc idt_table[NR_VECTORS]
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h | 37 ++---
arch/x86/kernel/idt.c | 42 +-
2 files changed, 35 insertions(+), 44 deletions(-)
--- a/arch/x86/include/asm/desc.h
set_intr_gate() is an internal function of the IDT code. The only user left
is the KVM code which replaces the pagefault handler eventually.
Provide an explicit update_intr_gate() function and make set_intr_gate()
static. While at it replace the magic number 14 in the KVM code with the
proper
The tracepoint macro magic emits code for all tracepoints in a event header
file. That code stays around even if the tracepoint is not used at all. The
linker does not discard it.
Build the various irq_vector tracepoints dependent on the appropriate CONFIG
switches.
Signed-off-by: Thomas
Replace the APIC/SMP vector gate initialization with the table based
mechanism.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h |1
arch/x86/kernel/idt.c | 48 ++
arch/x86/kernel/irqinit.c | 69
The error and the spurious interrupt are really rare events and not at all
so performance sensitive that two NOP5s can not be tolerated when tracing
is disabled.
Remove the nonsense.
Signed-off-by: Thomas Gleixner
Reviewed-by: Steven Rostedt (VMware)
Some of the entry function defines for i386 were explictely using the
BUILD_INTERRUPT3() macro to prevent that the extra trace entry got added
via BUILD_INTERRUPT(). No that the trace cruft is gone, the file can be
cleaned up and converted to use BUILD_INTERRUPT() which avoids the ugly
line
The pagefault and the resched IPI handler are the only ones where it is
worth to optimize the code further in case tracepoints are disabled. But it
makes no sense to have a single static key for both.
Seperate the static keys so the facilities are handled seperately.
Signed-off-by: Thomas
Two NOP5 are really a good tradeoff vs. the unholy IDT switching mess,
which duplicates code all over the place. The rescheduling interrupt gets
optimized in a later step.
Make the ordering of function call and statistics increment the same as in
other places. stats first, then function call.
No more users of the tracing idt. All exception tracepoints have been moved
into the regular handlers. Get rid of the mess which shouldn't have been
created in the first place.
Signed-off-by: Thomas Gleixner
---
arch/x86/entry/entry_32.S | 12 +-
On the 2nd generation Lenovo Tablet only clickpad is working; the
trackpoint and three mouse buttons do not work.
hid_multitouch must export all inputs in order to get trackpoint and
buttons to function.
Signed-off-by: Pavel Tatashin
---
drivers/hid/hid-ids.h
On 08/25, Zhang Rui wrote:
> On Thu, 2017-08-17 at 13:12 +0530, kgu...@codeaurora.org wrote:
> > On 2017-08-16 17:53, kgu...@codeaurora.org wrote:
> > >
> > > On 2017-08-08 13:42, Zhang Rui wrote:
> > > >
> > > > On Thu, 2017-07-13 at 17:39 +0530, Kiran Gunda wrote:
> > > > >
> > > > > From:
On Mon, 2017-08-21 at 10:24 +0800, Huacai Chen wrote:
> 3.16 doesn't need this, because 3.16 doesn't support Loongson-3 R2/R3.
Thanks, I'll drop this.
Ben.
> Huacai
>
> > On Fri, Aug 18, 2017 at 9:13 PM, Ben Hutchings wrote:
> > 3.16.47-rc1 review patch. If anyone has
On Fri, 2017-08-18 at 06:53 -0700, Eric Dumazet wrote:
> > On Fri, Aug 18, 2017 at 6:13 AM, Ben Hutchings wrote:
> > 3.16.47-rc1 review patch. If anyone has any objections, please let me know.
> >
> > --
> >
> > From: WANG Cong
>
Commit-ID: d56593eb5eda8f593db92927059697bbf89bc4b3
Gitweb: http://git.kernel.org/tip/d56593eb5eda8f593db92927059697bbf89bc4b3
Author: Tony Luck
AuthorDate: Thu, 24 Aug 2017 09:26:52 -0700
Committer: Thomas Gleixner
CommitDate: Fri, 25 Aug 2017
Commit-ID: 1d9807fc64c131a83a96917f2b2da1c9b00cf127
Gitweb: http://git.kernel.org/tip/1d9807fc64c131a83a96917f2b2da1c9b00cf127
Author: Tony Luck
AuthorDate: Thu, 24 Aug 2017 09:26:51 -0700
Committer: Thomas Gleixner
CommitDate: Fri, 25 Aug 2017
From: Markus Elfring
Date: Fri, 25 Aug 2017 21:55:14 +0200
Replace the specification of a data type by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style
On 2017-08-25 12:48, Vikram Mulukutla wrote:
If I understand the code correctly, the upper 32 bits of an ARM64
virtual
address will overflow when 1 is added to it, and so we'll keep WFE'ing
on
every subsequent cpu_relax invoked from the same PC, until we cross the
hard-coded threshold,
On Thu, 24 Aug 2017, Will Deacon wrote:
> On Thu, Aug 24, 2017 at 09:31:05AM +0200, Jiri Slaby wrote:
> > +static int futex_atomic_op_inuser(unsigned int encoded_op, u32 __user
> > *uaddr)
> > +{
> > + unsigned int op = (encoded_op & 0x7000) >> 28;
> > + unsigned int cmp =
On 24 August 2017 at 14:20, Arnd Bergmann wrote:
> On Thu, Aug 24, 2017 at 6:45 PM, Joe Stringer wrote:
>> Recent changes[0] to make use of __compiletime_assert() from container_of()
>> increased the scope of this macro, resulting in a wider set of
>> situations
Setting the PLL involves the calculation of a fixed point ratio
with 4 decimal digits fraction, referred to as "J.D". The
fraction "D" is stored separately from the integer part "J"
and is limited to 0...
The current algorithm uses integer registers to calculate the
fraction part, but failed
The early IDT setup can be done in C code like it's done on 64 bit. Reuse
the 64 bit version.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/segment.h |1 +
arch/x86/kernel/head32.c |4
arch/x86/kernel/head_32.S | 36
Initialize the regular traps with a table.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h |1
arch/x86/kernel/idt.c | 51
arch/x86/kernel/traps.c | 42 +---
3
The IDT related inlines are not longer used. Remove them.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h | 36
1 file changed, 36 deletions(-)
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@
Add the initialization table for the early trap setup and replace the early
trap init code.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/idt.c | 52
arch/x86/kernel/setup.c |4 +--
arch/x86/kernel/traps.c | 27
Move the gate intialization from interrupt init to the IDT code so all IDT
related operations are at a single place.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/idt.c | 18 ++
arch/x86/kernel/irqinit.c | 18 --
2 files changed,
The IDT cleanup is about to remove pack_descriptor(). The GDT setup for the
percpu storage can be achieved with the static initializer as well. Replace
it.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/setup_percpu.c |9 +++--
1 file changed, 3 insertions(+), 6
The only users of alloc_intr_gate() are hypervisors, which both check the
used_vectors bitmap whether they have allocated the gate already. Move that
check into alloc_intr_gate() and simplify the users.
Signed-off-by: Thomas Gleixner
Reviewed-by: Juergen Gross
Add the debug_idt init table and make use of it.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h |2 ++
arch/x86/kernel/idt.c | 23 +++
arch/x86/kernel/traps.c |6 +-
3 files changed, 26 insertions(+), 5 deletions(-)
Initialize the IST based traps via a table
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h |2 ++
arch/x86/kernel/idt.c | 22 ++
arch/x86/kernel/traps.c |9 +
3 files changed, 25 insertions(+), 8 deletions(-)
The early IDT handler setup is done in C entry code for 64 bit and in ASM
entry code for 32 bit. Move the 64bit variant to the IDT code so it can be
shared with 32bit in the next step.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h |9 +
The two NOP5 are noise in the rest of the work which is done by the timer
interrupt and modern CPUs are pretty good in optimizing nops.
Get rid of the interrupt handler duplication and move the tracepoints into
the regular handler.
Signed-off-by: Thomas Gleixner
Reviewed-by:
Two NOP5 are a reasonable tradeoff to avoid duplicated code and the
requirement to switch the IDT.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |2 +-
arch/x86/kernel/irq_work.c| 16 ++--
2 files changed, 3 insertions(+), 15
Machine checks are not really high frequency events. The extra two NOP5 for
the disabled tracepoints are noise vs. the heavy lifting which needs to be
done in the MCE handler.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h|6 +++---
Make use of the new irqvector tracing static key and remove the duplicated
trace_do_pagefault() implementation.
If irq vector tracing is disabled, then the overhead of this is a single
NOP5, which is a reasonable tradeoff to avoid duplicated code and the
unholy macro mess.
Signed-off-by: Thomas
Accessing the per cpu data via per_cpu(, smp_processor_id()) is
pointless. Use this_cpu_ptr() instead.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/apic/apic.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/x86/kernel/apic/apic.c
+++
Two NOP5 are really a good tradeoff vs. the unholy IDT switching mess,
which duplicates code all over the place.
Signed-off-by: Thomas Gleixner
Reviewed-by: Steven Rostedt (VMware)
---
arch/x86/include/asm/hw_irq.h |2 +-
arch/x86/kernel/irq.c
Switching the IDT just for avoiding tracepoints creates a complete
impenetrable macro/inline/ifdef mess.
There is no point in avoiding tracepoints for most of the traps/exceptions.
For the more expensive tracepoints, like pagefaults, this can be handled with
an explicit static key.
Preparatory
Remove the unparseable comment in the other place while at it.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/desc.h |1 -
arch/x86/include/asm/irq.h |3 ---
2 files changed, 4 deletions(-)
--- a/arch/x86/include/asm/desc.h
+++
EISA has absolutely nothing to do with traps. The EISA bus detection does
not need to run in the very early boot. It's good enough to run it before
the EISA bus and drivers are initialized.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/Makefile |1 +
The mm-of-the-moment snapshot 2017-08-25-15-50 has been uploaded to
http://www.ozlabs.org/~akpm/mmotm/
mmotm-readme.txt says
README for mm-of-the-moment:
http://www.ozlabs.org/~akpm/mmotm/
This is a snapshot of my -mm patch queue. Uploaded at random hopefully
more than once a week.
You
On Fri, Aug 25, 2017 at 3:19 PM, Tim Chen wrote:
>
> Also I think patch 1 is still a good idea for a fail safe mechanism
> in case there are other long wait list.
Yeah, I don't hate patch #1.
But that other patch is just nasty.
> That said, I do think your suggested
Mike Kravetz wrote:
> On 08/25/2017 03:02 PM, Nadav Amit wrote:
>> Michal Hocko wrote:
>>
>>> Hmm, I do not see this neither in linux-mm nor LKML. Strange
>>>
>>> On Wed 23-08-17 14:41:21, Andrew Morton wrote:
From: Eric Biggers
On Fri, Aug 25, 2017 at 3:51 PM, Linus Torvalds
wrote:
>
> So take it as that: example pseudo-code that happens to pass a
> compiler, but is meant as a RFD rather than actually working.
Oh, and after I sent it out, I wanted to look once again, and realized
that the
On Sat, 2017-08-19 at 09:29 +0300, Maksim Salau wrote:
> On Fri, 18 Aug 2017 14:13:20 +0100
> Ben Hutchings wrote:
>
> > 3.16.47-rc1 review patch. If anyone has any objections, please let me know.
> >
> > --
> >
> > From: Maksim Salau
On 08/25/2017 12:58 PM, Linus Torvalds wrote:
> On Fri, Aug 25, 2017 at 9:13 AM, Tim Chen wrote:
>> Now that we have added breaks in the wait queue scan and allow bookmark
>> on scan position, we put this logic in the wake_up_page_bit function.
>
> Oh, _this_ is the
Arnd,
> The only reference to lpfc_nvmet_replenish_context() is inside of an
> #ifdef, leading to a harmless warning when CONFIG_NVME_TARGET_FC is
> disabled:
Applied to 4.14/scsi-queue. Thanks!
--
Martin K. Petersen Oracle Linux Engineering
Arnd,
> This is an interesting regression with gcc-8, showing a harmless
> warning for correct code:
Applied to 4.14/scsi-queue. Thanks!
--
Martin K. Petersen Oracle Linux Engineering
On 08/25/2017 03:02 PM, Nadav Amit wrote:
> Michal Hocko wrote:
>
>> Hmm, I do not see this neither in linux-mm nor LKML. Strange
>>
>> On Wed 23-08-17 14:41:21, Andrew Morton wrote:
>>> From: Eric Biggers
>>> Subject: mm/madvise.c: fix freeing of locked
> On Aug 9, 2017, at 2:26 PM, Khalid Aziz wrote:
>
> ADI is a new feature supported on SPARC M7 and newer processors to allow
> hardware to catch rogue accesses to memory. ADI is supported for data
> fetches only and not instruction fetches. An app can enable ADI on its
On Sat, Aug 26, 2017 at 02:36:47AM +0900, Sergey Senozhatsky wrote:
> If add_preferred_console() returns error then we must free a
> copy of `of_stdout_options' that we create right before the
> console registration.
>
> Signed-off-by: Sergey Senozhatsky
> ---
>
On Fri, Aug 25, 2017 at 04:48:12PM +0200, Antoine Tenart wrote:
> The link mode (speed, duplex) was forced based on what the phylib
> returns. This should not be the case, and only forced by ethtool
> functions manually. This patch removes the link mode enforcement from
> the phylib link_event
Hi All,
I am trying to use the latest (4.13-rc6) kernel in my android device
(Intel APL SOC, running Android O). But sometimes, during the boot
process, when MMC partition is getting mounted, I hit the following
kernel panic. Its not 100% reproducible. But I hit it twice in 10
cycles. Copied
On Fri, Aug 25, 2017 at 4:03 PM, Linus Torvalds
wrote:
>
> Let this be a lesson in just *how* little tested, and *how* crap that
> patch probably still is.
I haven't had time to look at it any more (trying to merge the pull
requests that came in today instead), but
On Thu, Aug 24, 2017 at 11:00 PM, Dan Williams wrote:
> On Thu, Aug 24, 2017 at 9:13 AM, Christoph Hellwig wrote:
>> I'm still very unhappy about the get/set flag state. What is the
>> reason you can't use/extend leases? (take a look at the fcntl
>> man
On Fri, Aug 25, 2017 at 9:13 AM, Tim Chen wrote:
> Now that we have added breaks in the wait queue scan and allow bookmark
> on scan position, we put this logic in the wake_up_page_bit function.
Oh, _this_ is the other patch you were talking about. I thought it was
+CC Peter, Tglx, Steven
On 06/15/2017 01:43 AM, Noam Camus wrote:
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once
Commit-ID: 20c4d49c0f304f3f945bbd560b26afa98f75a0c4
Gitweb: http://git.kernel.org/tip/20c4d49c0f304f3f945bbd560b26afa98f75a0c4
Author: Dan Carpenter
AuthorDate: Fri, 25 Aug 2017 15:14:09 +0300
Committer: Thomas Gleixner
CommitDate: Fri, 25
On Fri, Aug 25, 2017 at 06:15:08PM +0200, SF Markus Elfring wrote:
> @@ -2363,5 +2364,5 @@ static int tsi148_probe(struct pci_dev *pdev, const
> struct pci_device_id *id)
> master_num--;
>
> tsi148_device->flush_image =
> -
On Tue, 8/8/17, Arvind Yadav wrote:
Subject: [PATCH 31/35] wireless: realtek: rtl8187: constify usb_device_id
To: kv...@codeaurora.org, her...@canonical.com, ht...@users.sourceforge.net,
larry.fin...@lwfinger.net
Cc:
On Fri, 25 Aug 2017 22:07:33 +0200 (CEST)
Thomas Gleixner wrote:
> Fixed up version below.
>
Reviewed-by: Steven Rostedt (VMware)
-- Steve
> Thanks,
>
> tglx
> 8<-
> --- a/arch/x86/include/asm/hw_irq.h
> +++
On Fri, 25 Aug 2017, Thomas Gleixner wrote:
> On Fri, 25 Aug 2017, Steven Rostedt wrote:
> > On Fri, 25 Aug 2017 12:31:18 +0200
> > Thomas Gleixner wrote:
> >
> > > No more users of the tracing idt. All exception tracepoints have been
> > > moved
> > > into the regular
On Wed, Aug 23, 2017 at 01:16:41AM +0900, Masahiro Yamada wrote:
> This GPIO controller device is used on UniPhier SoCs.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v3:
> - Add .irq_set_affinity() hook
> - Use irq_domain_create_hierarchy() instead
On Fri, 25 Aug 2017 19:50:25 +0200
Andrea Adami wrote:
> On Fri, Aug 25, 2017 at 6:53 AM, Brian Norris
> wrote:
> > On Thu, Aug 24, 2017 at 01:27:10PM +0200, Boris Brezillon wrote:
> >> On Thu, 24 Aug 2017 12:30:02 +0200
> >> Andrea Adami
In commit fc6eead7c1e2 ("time: Clean up CLOCK_MONOTONIC_RAW time
handling"), I mistakenly added the following:
/* Update the monotonic raw base */
seconds = tk->raw_sec;
nsec = (u32)(tk->tkr_raw.xtime_nsec >> tk->tkr_raw.shift);
tk->tkr_raw.base = ns_to_ktime(seconds * NSEC_PER_SEC + nsec);
On 08/25/2017 03:51 PM, Nadav Amit wrote:
> Mike Kravetz wrote:
>
>> On 08/25/2017 03:02 PM, Nadav Amit wrote:
>>> Michal Hocko wrote:
>>>
Hmm, I do not see this neither in linux-mm nor LKML. Strange
On Wed 23-08-17 14:41:21, Andrew
Am 22.08.2017 um 04:14 schrieb Rob Herring:
> On Thu, Aug 17, 2017 at 12:11:38PM +0200, Andreas Färber wrote:
>> Add binding for Realtek RTD1295 IRQ mux.
>>
>> Signed-off-by: Andreas Färber
>> ---
>> .../interrupt-controller/realtek,rtd119x-mux.txt | 28
>>
Commit-ID: 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8
Gitweb: http://git.kernel.org/tip/0576113a387e0c8a5d9e24b4cd62605d1c9c0db8
Author: Tony Luck
AuthorDate: Thu, 24 Aug 2017 09:26:50 -0700
Committer: Thomas Gleixner
CommitDate: Fri, 25 Aug 2017
On Fri, 25 Aug 2017, Steven Rostedt wrote:
> On Fri, 25 Aug 2017 12:31:17 +0200
> Thomas Gleixner wrote:
>
>
> > -__visible void __irq_entry smp_trace_reschedule_interrupt(struct pt_regs
> > *regs)
> > -{
> > - /*
> > -* Need to call irq_enter() before calling the
From: Markus Elfring
Date: Fri, 25 Aug 2017 22:20:02 +0200
A few update suggestions were taken into account
from static source code analysis.
Markus Elfring (3):
Delete an error message for a failed memory allocation in sg_alloc()
Improve a size determination
On 08/25/2017 07:22 AM, Alexey Brodkin wrote:
From: Alexey Brodkin
ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty hardware blocks may trigger an interrupt that Linux
On 25 August 2017 at 03:52, Luca Abeni wrote:
> On Fri, 25 Aug 2017 08:02:43 +0200
> luca abeni wrote:
> [...]
>> > The above demonstrate that even if we have two CPUsets new task belong
>> > to the "default" CPUset and as such can use all
Commit-ID: ce8bdd6957202a38d67038e5ec940eed50f9f3eb
Gitweb: http://git.kernel.org/tip/ce8bdd6957202a38d67038e5ec940eed50f9f3eb
Author: kbuild test robot
AuthorDate: Tue, 22 Aug 2017 15:50:53 +0800
Committer: Thomas Gleixner
CommitDate: Fri,
1 - 100 of 1622 matches
Mail list logo