schema violation was detected by the dtbs_check
Signed-off-by: Oleksij Rempel
---
arch/mips/boot/dts/qca/ar9331.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi
b/arch/mips/boot/dts/qca/ar9331.dtsi
index 6e1e17cbc1ee0..9267bc9e4cc09
Fit led nodes to the latest naming schema.
Signed-off-by: Oleksij Rempel
---
arch/mips/boot/dts/qca/ar9331_dpt_module.dts | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/qca/ar9331_dpt_module.dts
b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts
index
Coding style issue
Signed-off-by: John Oldman
---
v1: Initial attempt.
V2: Resubmitted with shorter comment line, as suggested by Greg KH.
This patch clears the checkpatch.pl "Block comments should align the * on each
line" warning.
.../interface/vchiq_arm/vchiq_connected.c | 32
On Sat, May 09, 2020 at 04:35:39PM +0800, Chen Zhou wrote:
> snprintf() returns the number of bytes that would be written,
> which may be greater than the the actual length to be written.
>
> show() methods should return the number of bytes printed into the
> buffer. This is the return value of
On Sat, May 09, 2020 at 03:10:54AM +, Luis Chamberlain wrote:
> Commit dc9edc44de6c ("block: Fix a blk_exit_rl() regression") merged on
> v4.12 moved the work behind blk_release_queue() into a workqueue after a
> splat floated around which indicated some work on blk_release_queue()
> could
On Sat, May 09, 2020 at 03:10:56AM +, Luis Chamberlain wrote:
> On commit 6ac93117ab00 ("blktrace: use existing disk debugfs directory")
> merged on v4.12 Omar fixed the original blktrace code for request-based
> drivers (multiqueue). This however left in place a possible crash, if you
>
On Fri, May 8, 2020 at 12:05 AM kajoljain wrote:
> On 5/7/20 9:58 PM, Paul A. Clarke wrote:
> > From: "Paul A. Clarke"
> >
> > Add the following metrics to the POWER9 'cpi_breakdown' metricgroup:
> > - ict_noslot_br_mpred_cpi
> > - ict_noslot_br_mpred_icmiss_cpi
> > - ict_noslot_cyc_other_cpi
>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: e99332e7b4cda6e60f5b5916cf9943a79dbef902
commit: 5a4b9fe7fece62ecab6fb28fe92362f83b41c33e cxgb4/chcr: complete record tx
handling
date: 9 weeks ago
config: alpha-randconfig-r036-20200510 (attached
On 5/10/20 12:47 PM, Greg KH wrote:
> On Sun, May 10, 2020 at 09:55:57AM +0700, Dio Putra wrote:
>> Hi, it's first time for me to report user-space breakage in here, so
>> i'm begging your pardon.
>>
>> I want to report that Linux 5.4 breaking my USB mount workflow due
>> udevadm monitor report
On Sat, May 09, 2020 at 06:30:56PM -0700, rana...@codeaurora.org wrote:
> On 2020-05-06 02:48, Greg KH wrote:
> > On Mon, Apr 27, 2020 at 08:26:01PM -0700, Raghavendra Rao Ananta wrote:
> > > Potentially, hvc_open() can be called in parallel when two tasks calls
> > > open() on /dev/hvcX. In such
On Sun, May 10, 2020 at 01:48:24PM +0700, Dio Putra wrote:
> On 5/10/20 12:47 PM, Greg KH wrote:
> > On Sun, May 10, 2020 at 09:55:57AM +0700, Dio Putra wrote:
> >> Hi, it's first time for me to report user-space breakage in here, so
> >> i'm begging your pardon.
> >>
> >> I want to report that
On Sun, May 10, 2020 at 07:06:45AM +0100, John Oldman wrote:
> Coding style issue
>
> Signed-off-by: John Oldman
> ---
> v1: Initial attempt.
> V2: Resubmitted with shorter comment line, as suggested by Greg KH.
>
> This patch clears the checkpatch.pl "Block comments should align the * on
>
On Sun, May 10, 2020 at 12:45:41AM +0100, Al Viro wrote:
> From: Al Viro
>
> we use copy_to_user() on that thing anyway (and always had).
I already have this patch in this series:
https://lore.kernel.org/linux-fsdevel/20200507145924.ga28...@lst.de/T/#t
which is waiting to be picked up [1],
ext4_mb_discard_preallocations() only checks for grp->bb_prealloc_list
of every group to discard the group's PA to free up the space if
allocation request fails. Consider below race:-
Process A Process B
1. allocate blocks
1.
Currently while doing block allocation grp->bb_free may be getting
modified if discard is happening in parallel.
For e.g. consider a case where there are lot of threads who have
preallocated lot of blocks and there is a thread which is trying
to discard all of this group's PA. Now it could happen
ext4_mb_good_group() definition was changed some time back
and now it even initializes the buddy cache (via ext4_mb_init_group()),
if in case the EXT4_MB_GRP_NEED_INIT() is true for a group.
Note that ext4_mb_init_group() could sleep and so should not be called
under a spinlock held.
This is fine
Hello All,
v3 -> v4:
1. Splitted code cleanups and debug improvements as a separate patch series.
2. Dropped rcu_barrier() approach since it did cause some latency
in my testing of ENOSPC handling.
3. This patch series takes a different approach to improve the multi-threaded
ENOSPC handling in
There could be a race in function ext4_mb_discard_group_preallocations()
where the 1st thread may iterate through group's bb_prealloc_list and
remove all the PAs and add to function's local list head.
Now if the 2nd thread comes in to discard the group preallocations,
it will see that the
Implement ext4_mb_discard_preallocations_should_retry()
which we will need in later patches to add more logic
like check for sequence number match to see if we should
retry for block allocation or not.
There should be no functionality change in this patch.
Signed-off-by: Ritesh Harjani
---
Currently in case if EXT4_MB_GRP_NEED_INIT(grp) is true, then we first
check for few things like grp->bb_free etc with spinlock (ext4_lock_group)
held. Then we drop the lock only to initialize the group's buddy cache
and then again take the lock and check for ext4_mb_good_group().
Once this step
On 5/10/20 1:54 PM, Greg KH wrote:
> On Sun, May 10, 2020 at 01:48:24PM +0700, Dio Putra wrote:
>> On 5/10/20 12:47 PM, Greg KH wrote:
>>> On Sun, May 10, 2020 at 09:55:57AM +0700, Dio Putra wrote:
Hi, it's first time for me to report user-space breakage in here, so
i'm begging your
On Sat, 9 May 2020 12:43:30 +0900, Akira Yokosawa wrote:
> Hi Joel,
>
> Sorry for the late response but I've noticed some glitches.
>
> On Sun, 22 Mar 2020 21:57:32 -0400, Joel Fernandes (Google) wrote:
>> Move MP+onceassign+derefonce to the new Documentation/litmus-tests/rcu/
>> directory.
>
>From c171026a697d401ea5d2ad6656d0481944604b14 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa
Date: Sun, 10 May 2020 13:37:14 +0900
Subject: [PATCH 1/3] tools/memory-model: Fix reference to litmus test in
recipes.txt
The name of litmus test doesn't match the one described below.
Fix the name of
>From 898051fee51913f5b9bd01cab98beb8944ec50b2 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa
Date: Sun, 10 May 2020 13:43:34 +0900
Subject: [PATCH 2/3] Revert "Documentation: LKMM: Move MP+onceassign+derefonce
to new litmus-tests/rcu/"
This reverts commit
>From 1aa2c25f0ad16382a5bc597cdbdcc817645e01cd Mon Sep 17 00:00:00 2001
From: Akira Yokosawa
Date: Sun, 10 May 2020 15:12:57 +0900
Subject: [PATCH 3/3] Documentation/litmus-tests: Merge atomic's README into
top-level one
Where Documentation/litmus-tests/README lists RCU litmus tests,
On Sun, May 10, 2020 at 02:10:04PM +0700, Dio Putra wrote:
> On 5/10/20 1:54 PM, Greg KH wrote:
> > On Sun, May 10, 2020 at 01:48:24PM +0700, Dio Putra wrote:
> >> On 5/10/20 12:47 PM, Greg KH wrote:
> >>> On Sun, May 10, 2020 at 09:55:57AM +0700, Dio Putra wrote:
> Hi, it's first time for me
On Sat, May 09, 2020 at 01:15:48PM +0530, Naresh Kamboju wrote:
> On Fri, 8 May 2020 at 18:25, Greg Kroah-Hartman
> wrote:
> >
> > This is the start of the stable review cycle for the 5.6.12 release.
> > There are 49 patches in this series, all will be posted as a response
> > to this one. If
On Sat, May 09, 2020 at 06:17:05AM -0700, Guenter Roeck wrote:
> On 5/8/20 11:51 PM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.4.223 release.
> > There are 306 patches in this series, all will be posted as a response
> > to this one. If anyone has any
On Sat, May 9, 2020 at 5:47 AM Stephen Rothwell wrote:
>
> Hi Sage,
>
> On Sat, 9 May 2020 01:03:14 + (UTC) Sage Weil wrote:
> >
> > Jeff Layton
>
> Done.
> > On Sat, 9 May 2020, Stephen Rothwell wrote:
> > >
> > > I noticed commit
> > >
> > > 3a5ccecd9af7 ("MAINTAINERS: remove myself as
Colin King writes:
> From: Colin Ian King
>
> The variable status is being initializeed with a value that is never read
> and it is being updated later with a new value. The initialization
> is redundant and can be removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian
On Thu, Apr 16, 2020 at 2:19 AM wrote:
>
> From: "Paul E. McKenney"
>
> This code-movement-only commit is in preparation for adding an additional
> flavor of Tasks RCU, which relies on workqueues to detect grace periods.
>
> Signed-off-by: Paul E. McKenney
> ---
> kernel/rcu/tasks.h | 370
>
You're mostly correct. This is exactly why an I/O scheduler may be
applicable here IMO. Mostly because I/O schedulers tend to optimize for
something specific and always present tradeoffs. Users need to
understand what they are optimizing for.
Hence I'd say this functionality can definitely be
On Sat, 9 May 2020 16:33:55 +0800
Shaokun Zhang wrote:
> Fix up one typo: CONFIG_BOOTCONFIG -> CONFIG_BOOT_CONFIG
>
> Cc: Jiri Kosina
> Cc: Steven Rostedt
> Cc: Masami Hiramatsu
> Signed-off-by: Shaokun Zhang
Good catch! Thanks!
Acked-by: Masami Hiramatsu
> ---
> init/main.c | 2 +-
>
The arguments passed look bogus, try to fix them to something that seems
to make sense.
Signed-off-by: Christoph Hellwig
---
arch/arm/kernel/fiq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index
flush_icache_page is only used by mm/memory.c.
Signed-off-by: Christoph Hellwig
---
arch/nds32/mm/cacheflush.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
index 254703653b6f5..8f168b33065fa 100644
--- a/arch/nds32/mm/cacheflush.c
Hi all,
flush_icache_range is mostly used for kernel address, except for the following
cases:
- the nommu brk and mmap implementations,
- the read_code helper that is only used for binfmt_flat, binfmt_elf_fdpic,
and binfmt_aout including the broken ia32 compat version
- binfmt_flat itself,
The second argument is the end "pointer", not the length.
Signed-off-by: Christoph Hellwig
---
arch/arm64/kernel/machine_kexec.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/machine_kexec.c
b/arch/arm64/kernel/machine_kexec.c
index 8e9c924423b4e..a0b144cfaea71 100644
flush_cache_user_range is an ARMism not used by any generic or unicore32
specific code.
Signed-off-by: Christoph Hellwig
---
arch/unicore32/include/asm/cacheflush.h | 8
1 file changed, 8 deletions(-)
diff --git a/arch/unicore32/include/asm/cacheflush.h
This seems to lead to some crazy include loops when using
asm-generic/cacheflush.h on more architectures, so leave it
to the arch header for now.
Signed-off-by: Christoph Hellwig
---
arch/um/include/asm/tlb.h | 2 ++
arch/x86/include/asm/cacheflush.h | 2 ++
__flush_icache_user_range is not used in modular code, so unexport it.
Signed-off-by: Christoph Hellwig
---
arch/mips/mm/cache.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 33b409391ddb6..ad6df1cea866f 100644
--- a/arch/mips/mm/cache.c
There is a magic ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE cpp symbol that
guards non-stub availability of flush_dcache_pagge. Use that to
check if flush_dcache_pagg is implemented.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 6 +++---
1 file changed, 3 insertions(+), 3
cacheflush.h uses a somewhat to generic include guard name that clashes
with various arch files. Use a more specific one.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
ARM64 needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/arm64/include/asm/cacheflush.h | 46 -
1 file changed, 5 insertions(+), 41 deletions(-)
diff --git
IA64 needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/ia64/include/asm/cacheflush.h | 28 +++-
1 file changed, 3 insertions(+), 25 deletions(-)
diff --git
RISC-V needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Also remove the pointless __KERNEL__ ifdef while we're at it.
---
arch/riscv/include/asm/cacheflush.h | 62 ++---
1 file changed, 3 insertions(+), 59
The SuperH implementation of flush_icache_range seems to be able to
cope with user addresses. Just define flush_icache_user_range to
flush_icache_range.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/cacheflush.h | 1 +
1 file changed, 1 insertion(+)
diff --git
The function currently known as flush_icache_user_range only operates
on a single page. Rename it to flush_icache_user_page as we'll need
the name flush_icache_user_range for something else soon.
Signed-off-by: Christoph Hellwig
---
arch/alpha/include/asm/cacheflush.h| 10 +-
Define flush_icache_user_range to flush_icache_range unless the
architecture provides its own implementation.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/asm-generic/cacheflush.h
The Xtensa implementation of flush_icache_range seems to be able to
cope with user addresses. Just define flush_icache_user_range to
flush_icache_range.
Signed-off-by: Christoph Hellwig
---
arch/xtensa/include/asm/cacheflush.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
flush_icache_user_range is only used by , so
remove it from the architectures that implement it, but don't use
.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/cacheflush.h | 3 ---
arch/sparc/include/asm/cacheflush_32.h | 2 --
arch/sparc/include/asm/cacheflush_64.h | 1 -
Power needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Also remove the pointless __KERNEL__ ifdef while we're at it.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/include/asm/cacheflush.h | 42 +++
1 file
read_code operates on user addresses.
Signed-off-by: Christoph Hellwig
---
fs/exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/exec.c b/fs/exec.c
index a4f766f296f8f..c541867316a63 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1033,7 +1033,7 @@ ssize_t read_code(struct
flush_icache_range generally operates on kernel addresses, but for some
reason m68k needed a set_fs override. Move that into the m68k code
insted of keeping it in the module loader.
Signed-off-by: Christoph Hellwig
---
arch/m68k/mm/cache.c | 4
kernel/module.c | 8
2 files
OpenRISC needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/openrisc/include/asm/cacheflush.h | 31 +-
1 file changed, 6 insertions(+), 25 deletions(-)
diff --git
C6x needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/c6x/include/asm/cacheflush.h | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git
load_flat_file works on user addresses.
Signed-off-by: Christoph Hellwig
---
fs/binfmt_flat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c
index 831a2b25ba79f..6f0aca5379da2 100644
--- a/fs/binfmt_flat.c
+++ b/fs/binfmt_flat.c
@@ -854,7
Only build read_code when binary formats that use it are built into the
kernel.
Signed-off-by: Christoph Hellwig
---
fs/exec.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/fs/exec.c b/fs/exec.c
index 06b4c550af5d9..a4f766f296f8f 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1027,6
These obviously operate on user addresses.
Signed-off-by: Christoph Hellwig
---
mm/nommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mm/nommu.c b/mm/nommu.c
index 318df4e236c99..aed7acaed2383 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -443,7 +443,7 @@
flush_icache_user_range will be the name for a generic primitive.
Move the arm name so that arm already has an implementation.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/cacheflush.h | 4 ++--
arch/arm/kernel/traps.c | 2 +-
2 files changed, 3 insertions(+), 3
Rename the current flush_icache_range to flush_icache_user_range as
per commit ae92ef8a4424 ("PATCH] flush icache in correct context") there
seems to be an assumption that it operates on user addresses. Add a
flush_icache_range around it that for now is a no-op.
Signed-off-by: Christoph Hellwig
Hexagon needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/hexagon/include/asm/cacheflush.h | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git
Microblaze needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/microblaze/include/asm/cacheflush.h | 29 ++--
1 file changed, 2 insertions(+), 27 deletions(-)
diff --git
m68knommu needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/m68k/include/asm/cacheflush_no.h | 19 ++-
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git
flush_icache_user_range is only used by copy_to_user_page, which is
only used by core VM code.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/mm/mem.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 041ed7cfd341a..f0d1bf0a8e14f 100644
Alpha needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/alpha/include/asm/cacheflush.h | 28 ++--
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git
On 4/24/20 1:21 AM, Sasha Levin wrote:
Benefits:
Currently a user process that wishes to read or write the FS/GS base must
make a system call. But recent X86 processors have added new instructions
for use in 64-bit mode that allow direct access to the FS and GS segment
base addresses. The
On Sat, May 09, 2020 at 10:05:43PM -0700, Andy Lutomirski wrote:
> On Sat, May 9, 2020 at 2:57 PM Joerg Roedel wrote:
> I spent some time looking at the code, and I'm guessing you're talking
> about the 3-level !SHARED_KERNEL_PMD case. I can't quite figure out
> what's going on.
>
> Can you
On Sun, 10 May 2020, Markus Elfring wrote:
> Christophe Jaillet proposed to complete the exception handling also for this
> function implementation.
> I find that such a software correction is qualified for this tag.
>
On 5/10/20 10:09 AM, Vegard Nossum wrote:
On 4/24/20 1:21 AM, Sasha Levin wrote:
Benefits:
Currently a user process that wishes to read or write the FS/GS base must
make a system call. But recent X86 processors have added new instructions
for use in 64-bit mode that allow direct access to
Thanks for the feedback Greg.
Will resubmit the patch as you suggest.
Thanks
john
On Sun, 10 May 2020 at 07:55, Greg KH wrote:
>
> On Sun, May 10, 2020 at 07:06:45AM +0100, John Oldman wrote:
> > Coding style issue
> >
> > Signed-off-by: John Oldman
> > ---
> > v1: Initial attempt.
> > V2:
On 5/10/20 2:32 PM, Greg KH wrote:
> On Sun, May 10, 2020 at 02:10:04PM +0700, Dio Putra wrote:
>> On 5/10/20 1:54 PM, Greg KH wrote:
>>> On Sun, May 10, 2020 at 01:48:24PM +0700, Dio Putra wrote:
On 5/10/20 12:47 PM, Greg KH wrote:
> On Sun, May 10, 2020 at 09:55:57AM +0700, Dio Putra
On Sat, 09 May 2020 03:49:31 -0700
Srinivas Pandruvada wrote:
> On Fri, 2020-04-24 at 07:34 +0300, Alexandru Ardelean wrote:
> > The main intent here is to get rid of the iio_buffer_set_attrs()
> > helper, or
> > at least rework it's usage a bit.
> > The problem with that helper is that it needs
On 9 May 2020 11:38:46 BST, Ivan Mikhaylov wrote:
>On Fri, 2020-05-08 at 15:51 +0100, Jonathan Cameron wrote:
>> On Thu, 7 May 2020 16:25:59 +0300
>> Ivan Mikhaylov wrote:
>>
>> > Mostly standard i2c driver with some additional led-current option
>> > for vcnl3020.
>> >
>> > Signed-off-by:
On Sat, Mar 28, 2020 at 09:43:06AM -0700, Yu-cheng Yu wrote:
> The signal return code is responsible for taking an XSAVE buffer present
> in user memory and loading it into the hardware registers. This
> operation only affects user XSAVE state and never affects supervisor state.
>
> The fast
Hello
On Sat, May 09, 2020 at 02:30:45AM +0200, Sebastian Reichel wrote:
> Hi,
>
> On Fri, May 08, 2020 at 02:38:44AM +0300, Serge Semin wrote:
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with dt-schema. This commit replaces SYSCON reboot-mode
> >
On Sun, May 10, 2020 at 03:35:34PM +0700, Dio Putra wrote:
> On 5/10/20 2:32 PM, Greg KH wrote:
> > On Sun, May 10, 2020 at 02:10:04PM +0700, Dio Putra wrote:
> >> On 5/10/20 1:54 PM, Greg KH wrote:
> >>> On Sun, May 10, 2020 at 01:48:24PM +0700, Dio Putra wrote:
> On 5/10/20 12:47 PM, Greg
On Sat, Mar 28, 2020 at 09:43:07AM -0700, Yu-cheng Yu wrote:
> v3:
> - Change copy_xregs_to_kernel() to copy_supervisor_to_kernel(), which is
> introduced in a previous patch.
> - Update commit log.
>
> Signed-off-by: Yu-cheng Yu
> Reviewed-by: Dave Hansen
> ---
>
Le samedi 09 mai 2020 à 19:26 -0700, Randy Dunlap a écrit :
> > +
> > +/*--Structs---
> > --*/
> > +
> > +/**
> > + * struct w1_therm_family_converter
> > + * \brief Used to bind standard function call
> > + * to device specific function
Hi Wei,
On Sun, 10 May 2020 05:41:57 +0800
Wei Li wrote:
> PSTATE.I and PSTATE.D are very important for single-step working.
>
> Without disabling interrupt on local CPU, there is a chance of
> interrupt occurrence in the period of exception return and start of
> out-of-line single-step, that
>> https://lore.kernel.org/lkml/20200427061803.53857-1-christophe.jail...@wanadoo.fr/
>
> Do you know when these bugs were introduced?
I suggest to take another look at a provided tag “Fixes”.
To which commit would you like to refer to for the proposed adjustment of
the function
In the start of the "vnt_rf_set_txpower" function the "power" variable
is set at most to VNT_RF_MAX_POWER (hex = 0x3f, dec = 63). Then, in the
switch statement there are four comparisons with the "power" variable
against AL7230_PWR_IDX_LEN (dec = 64), VT3226_PWR_IDX_LEN (dec = 64),
On 15/04/2020 18:25, deven.de...@linux.microsoft.com wrote:
> From: Deven Bowers
>
> Overview:
>
>
> IPE is a Linux Security Module which allows for a configurable
> policy to enforce integrity requirements on the whole system. It
> attempts to solve the
On Mon, 4 May 2020 14:55:41 +0200
Hans de Goede wrote:
> Switch to the new style i2c-driver probe_new probe function and drop the
> unnecessary i2c_device_id table (we do not have any old style board files
> using this).
>
> This is a preparation patch for adding ACPI binding support.
>
>
On 5/10/20 3:48 PM, Greg KH wrote:
> On Sun, May 10, 2020 at 03:35:34PM +0700, Dio Putra wrote:
>> On 5/10/20 2:32 PM, Greg KH wrote:
>>> On Sun, May 10, 2020 at 02:10:04PM +0700, Dio Putra wrote:
On 5/10/20 1:54 PM, Greg KH wrote:
> On Sun, May 10, 2020 at 01:48:24PM +0700, Dio Putra
DW APB I2C slave code in fact depends on the DW I2C driver core, but not
on the platform code. Yes, the I2C slave interface is currently supported
by the platform version of the IP core, but it doesn't make it dependent
on it. So make sure the DW APB I2C slave config is only available if the
Since commit 4f8272802739 ("Documentation: update kbuild loadable modules
goals & examples") `-objs` is fitted for building host programs, lets
change DW I2C core, platform and PCI driver kbuild directives to using
`-y`, which more straightforward for device drivers. By doing so we can
discard the
Recently the I2C-controllers slave interface support was added to the
kernel I2C subsystem. In this case Linux can be used as, for example,
a I2C EEPROM machine. See [1] for details. Other than instantiating
the EEPROM-slave device from user-space there is a way to declare the
device in dts. In
Add the "baikal,bt1-sys-i2c" compatible string to the DW I2C binding and
make sure the reg property isn't required in this case because the
controller is embedded into the Baikal-T1 System Controller. The rest of
the DW APB I2C properties are compatible and can be freely used to describe
the
Currently Intel Baytrail I2C semaphore is a feature of the DW APB I2C
platform driver. It's a bit confusing to see it's config in the menu at
some separated place with no reference to the platform code. Lets move the
config definition under the if-I2C_DESIGNWARE_PLATFORM clause. By doing so
the
Since glue-layer drivers design is now supported by the DW APB I2C
platform code lets unpin MSCC Ocelot I2C driver at least. It won't be that
hard because the only difference between this controller and vanilly core
is in what the former sets the sda hold time in a dedicated configure
registers
Initially this has been a small patchset which embedded the Baikal-T1
System I2C support into the DW APB I2C driver as is by using a simplest
way. After a short discussion with Andy we decided to implement what he
suggested (introduce regmap-based accessors and create a glue driver) and
even more
Seeing the DW I2C platform driver is getting overcomplicated with a lot of
vendor-specific configs let's introduce a glue-layer interface so new
platforms which equipped with Synopsys Designware APB I2C IP-core would
be able to handle their peculiarities in the dedicated objects.
The generic
A PM workaround activated by the flag MODEL_CHERRYTRAIL has been removed
since commit 9cbeeca05049 ("i2c: designware: Remove Cherry Trail PMIC I2C
bus pm_disabled workaround"), but the flag most likely by mistake has been
left in the Dw I2C drivers. Lets remove it.
By doing so we get rid from the
Seeing the DW I2C driver is using flags-based accessors with two
conditional clauses it would be better to replace them with the regmap
API IO methods and to initialize the regmap object with read/write
callbacks specific to the controller registers map implementation. This
will be also handy for
Modern device tree bindings are supposed to be created as YAML-files
in accordance with dt-schema. This commit replaces Synopsys DW I2C
legacy bare text bindings with YAML file. As before the bindings file
states that the corresponding dts node is supposed to be compatible
either with generic DW
This is a preparation patch before adding a glue platform driver for the
Baikal-T1 I2C controller. Since the i2c controller registers are indirectly
accessed by means of the Baikal-T1 System Controller registers we need to
have a way to disable the default registers mapping setup procedure and
Baikal-T1 System Controller is equipped with a dedicated I2C Controller
which functionality is based on the DW APB I2C IP-core, the only
difference in a way it' registers are accessed. There are three access
register provided in the System Controller registers map, which
indirectly address the
On Mon, 4 May 2020 20:10:34 +0200
Andreas Klinger wrote:
> Limit the output of humidity compensation to the range between 0 and 100
> percent.
>
> Depending on the calibration parameters of the individual sensor it
> happens, that a humidity above 100 percent or below 0 percent is
> calculated,
In some error handling paths, a call to 'iio_channel_get()' is not balanced
by a corresponding call to 'iio_channel_release()'.
This can be achieved easily by using the devm_ variant of
'iio_channel_get()'.
This has the extra benefit to simplify the remove function.
Fixes: 19939860dcae
On Fri, 8 May 2020 14:02:21 +0100
Jonathan Cameron wrote:
> On Wed, 6 May 2020 19:31:38 +0200
> Marion & Christophe JAILLET wrote:
>
> > Le 06/05/2020 à 12:38, Andy Shevchenko a écrit :
> > > On Wed, May 6, 2020 at 6:55 AM Christophe JAILLET
> > > wrote:
> > >> This looks really unusual
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