Hi,
now the second, revised version of the patch set. I now tested loading
both drivers after each other in several combinations, after two bug
fixes this now works as expected.
I added a patch to move messages from powernow-k8 after the initialization
phase, so it remains silent if driver loading
From: Matthew Garrett
Some AMD systems may round the frequencies in ACPI tables to 100MHz
boundaries. We can obtain the real frequencies from MSRs, so add a quirk
to fix these frequencies up on AMD systems.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
arch/x86/include/asm
cpufreq modules are often loaded from init scripts that assume that
all recent AMD systems will use powernow-k8.
To inform the user of the change of support and ease the transition
to acpi-cpufreq, emit a warning message.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/Kconfig.x86 | 3
.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/acpi-cpufreq.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 067a61f..70e7173 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
cpufreq support
after the transition.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
drivers/cpufreq/Makefile | 2 +-
drivers/cpufreq/powernow-k8.c | 392 +++---
drivers/cpufreq/powernow-k8.h | 32
3 files changed, 29 insertions
fig switch
I'd like to consider this feature obsolete. Lets keep it around for
some kernel versions and then phase it out.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/Kconfig.x86| 12 +++
drivers/cpufreq/acpi-cpufreq.c | 46 --
2 fi
tionale and the usage.
A following patch will re-introduce the cpb knob for compatibility
reasons on AMD CPUs.
Per-CPU boost switching is possible, but not trivial and is thus
postponed to a later patch series.
Signed-off-by: Andre Przywara
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 11 +
control to acpi-cpufreq.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
arch/x86/include/asm/msr-index.h | 2 ++
drivers/cpufreq/Kconfig.x86 | 3 ++-
drivers/cpufreq/acpi-cpufreq.c | 43 ++--
3 files changed, 41 insertions(+), 7 deletions
not succeed.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/powernow-k8.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index 16c7fb6..8ff0621 100644
--- a/drivers/cpufreq/powernow-k8
The WAF may hurt the performance of some workloads, caused by
aliasing issues in the L1 cache.
Disable it on the affected CPUs.
Signed-off-by: Andre Przywara
---
arch/x86/kernel/cpu/amd.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86
On 10/24/2012 12:46 PM, Ingo Molnar wrote:
* Andre Przywara wrote:
The WAF may hurt the performance of some workloads, caused by
aliasing issues in the L1 cache.
Disable it on the affected CPUs.
Signed-off-by: Andre Przywara
---
arch/x86/kernel/cpu/amd.c | 14 ++
1 file
Hi guys,
in case there are any inquiries regarding code of mine (e.g. triggered
by git annotate or commit messages), feel free to contact me via my
private address:
o...@andrep.de
My AMD email address is no longer valid.
Regards,
André Przywara
--
To unsubscribe from this list: send the line "u
From: Andre Przywara
The Way Access Filter in recent AMD CPUs may hurt the performance of
some workloads, caused by aliasing issues in the L1 cache.
This patch disables it on the affected CPUs.
The issue is similar to that one of last year:
http://lkml.indiana.edu/hypermail/linux/kernel/1107.3
been mostly reworked and documentation for it
has been added. Also there was a need for (yet another) BIOS quirk
on AMD desktop boards.
Signed-off-by: Andre Przywara
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.
.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/acpi-cpufreq.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 067a61f..ea949b8 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq
From: Matthew Garrett
Some AMD systems may round the frequencies in ACPI tables to 100MHz
boundaries. We can obtain the real frequencies from MSRs, so add a quirk
to fix these frequencies up on AMD systems.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
arch/x86/include/asm
cpufreq support
after the transition.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
drivers/cpufreq/powernow-k8.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index c0e8164..6e35ed2
will re-introduce the cpb knob for compatibility
reasons on AMD CPUs.
Per-CPU boost switching is possible, but not trivial and is thus
postponed to a later patch series.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/acpi-cpufreq.c | 177
1 files chan
control to acpi-cpufreq.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
arch/x86/include/asm/msr-index.h |2 +
drivers/cpufreq/acpi-cpufreq.c | 43 -
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/msr
The new acpi-cpufreq driver supports a system global control switch
to disable the frequency boosting feature of some (x86) CPUs.
Provide documentation about the rationale and the usage.
Signed-off-by: Andre Przywara
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 12
From: Matthew Garrett
These chips are now supported by acpi-cpufreq, so we can delete all the
code handling them.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
---
drivers/cpufreq/Makefile |2 +-
drivers/cpufreq/powernow-k8.c | 385
fig switch
I'd like to consider this feature obsolete. Lets keep it around for
some kernel versions and then phase it out.
Signed-off-by: Andre Przywara
---
drivers/cpufreq/Kconfig.x86| 12 ++
drivers/cpufreq/acpi-cpufreq.c | 46 ++-
2 fi
On 09/05/2012 04:25 PM, Thomas Renninger wrote:
On Wednesday, September 05, 2012 03:46:22 PM Rafael J. Wysocki wrote:
On Tuesday, September 04, 2012, Andre Przywara wrote:
Hi,
I have applied the whole series to the linux-next branch of the linux-pm.git
Thanks!
tree, but I'm quite u
ufreq. So a dependency on the old driver does not help.
Are there still any problems with this patchset? Or are you only
wondering about the new config switch?
Thanks for testing!
Andre.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
--
To unsubscribe
] ---[ end trace a7919e7f17c0a725 ]---
The new code will change every of the 16 low bits read from the
register and tries to write and read-back that modified number
from the MSR.
Signed-off-by: Andre Przywara
---
arch/x86/kernel/cpu/perf_event.c | 10 ++
1 file changed, 6 insertions(+), 4
] ---[ end trace a7919e7f17c0a725 ]---
The new code will change every of the 16 low bits read from the
register and tries to write and read-back that modified number
from the MSR.
Signed-off-by: Andre Przywara
---
arch/x86/kernel/cpu/perf_event.c | 10 ++
1 file changed, 6 insertions(+), 4
On 10/09/2012 05:51 PM, Konrad Rzeszutek Wilk wrote:
On Tue, Oct 09, 2012 at 05:38:34PM +0200, Andre Przywara wrote:
In check_hw_exists() we try to detect non-emulated MSR accesses
by writing an arbitrary value into one of the PMU registers
and check if it's value after a readout is stil
On 08/22/2012 03:00 AM, Thomas Renninger wrote:
On Monday 20 August 2012 22:49:16 Rafael J. Wysocki wrote:
On Monday, August 20, 2012, Andre Przywara wrote:
On 08/05/2012 11:33 PM, Rafael J. Wysocki wrote:
On Thursday, July 26, 2012, Andre Przywara wrote:
...
If you insist, I can keep the
On 09/15/2012 01:20 PM, Konrad Rzeszutek Wilk wrote:
On Sep 4, 2012 4:26 AM, "Andre Przywara" mailto:andre.przyw...@amd.com>> wrote:
>
> To workaround some Windows specific behavior, the ACPI _PSD table
> on AMD desktop boards advertises all cores as dependent, mea
base)? Remember, this is Linux: If you want to shoot
yourself in the foot, we will not prevent you.
Regards,
Andre.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
th
to make this bullet-proof, preferably through the container
functionality. I see that you do already massive sysfs filtering and
also /proc/ filtering, so this maybe an option?
This approach does not need any kernel support (except for the
/proc/cpuinfo filtering). Does this address the issues you hav
write the same reply yesterday, but followed the hint in
Alan's previous mail:
# mount --bind /dev/shm/faked_cpuinfo /somepath/proc/cpuinfo
I checked it, it works even with chroots and is not visible from within.
Regards,
Andre.
--
Andre Przywara
AMD-Operating System Research Center
On 07/25/2012 01:02 PM, Vladimir Davydov wrote:
On 07/25/2012 02:58 PM, Andre Przywara wrote:
On 07/25/2012 12:31 PM, Vladimir Davydov wrote:
On 07/24/2012 04:44 PM, Alan Cox wrote:
This approach does not need any kernel support (except for the
/proc/cpuinfo filtering). Does this address the
On 08/05/2012 11:33 PM, Rafael J. Wysocki wrote:
On Thursday, July 26, 2012, Andre Przywara wrote:
From: Matthew Garrett
These chips are now supported by acpi-cpufreq, so we can delete all the
code handling them.
Signed-off-by: Matthew Garrett
Signed-off-by: Andre Przywara
Would it be
Hi,
On 25/07/16 20:54, Maxime Ripard wrote:
> On Wed, Jul 20, 2016 at 10:03:16AM +0200, LABBE Corentin wrote:
>> This patch add support for sun8i-emac ethernet MAC hardware.
>> It could be found in Allwinner H3/A83T/A64 SoCs.
>>
>> It supports 10/100/1000 Mbit/s speed with half/full duplex.
>> It
Hi Jean-Francois,
On 01/08/16 09:30, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 02:43:06 +0100
> André Przywara wrote:
>
>> As this became quite a long read, here a TL;DR:
>> - We consider using an SCPI based clock system for the A64, alongside
>> allwinner,simple-gates and fixed clocks. We
Hi Drew,
(CC:ing Dave)
On 01/08/16 13:50, Andrew Jones wrote:
>
> Hi Andre,
>
> I have a couple questions and a bug report regarding the SBSA UART.
>
> When AArch64 Linux is boot with QEMU and UEFI (AAVMF) we can enable
> the use of ACPI. When we do that the PL011 model QEMU provides is
> expo
s instead of _errata.
Yes, this makes sense.
Acked-by: Andre Przywara
Thanks!
Andre.
> Cc: Mark Rutland
> Cc: Andre Przywara
> Cc: Catalin Marinas
> Signed-off-by: Suzuki K Poulose
> ---
> arch/arm64/include/asm/cpufeature.h | 4 ++--
> arch/arm64/kernel/cpu_errata
che maintenance instructions trapping still works as expected.
Acked-by: Andre Przywara
Cheers,
Andre.
>
> Cc: Andre Przywara
> Cc: Mark Rutland
> Cc: Will Deacon
> Cc: Catalin Marinas
> Signed-off-by: Suzuki K Poulose
> ---
Hi Maxime,
On 26/07/16 21:30, Maxime Ripard wrote:
> From: Andre Przywara
>
> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> the p
each parent clock used. This allows
to specify any kind of relation efficiently and also keeps the very
same kernel driver for all SoCs at the same time.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/clock/sunxi.txt | 7 +++
1 file changed, 7
DT node
- use fixed-clocks for basic PLL clocks
- use clock names based on manual (periph0 & friends)
- move clocks out of their own subnode into a separate file
- add .dts for BananaPi-M64 (thanks to Nora Lee for a sample board)
Andre Przywara (7):
arm64: sunxi: Kconfig: add essential pinctrl
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1992aa9..492f92c
4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.
Signed-off-by: Andre Przywara
---
Hi,
I dropped Rob's previous AC
The BananaPi M64 is a single board computer with an Allwinner A64 SoC.
In addition to the usual suspects it contains Gigabit Ethernet, 2GB RAM,
an eMMC and a WiFi chip (which are not yet supported by this patch).
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile
adding a new driver or function for every new SoC.
Signed-off-by: Andre Przywara
Acked-by: Jean-Francois Moine
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-multi-gates.c | 105
2 files changed, 106 insertions(+)
create mode 100644
in the original pinctrl driver patch, but got removed
to avoid the dependency on the Kconfig patch [1].
Also add the general PINCTRL symbol, which isn't selected automatically
for the same reason.
Reported-by: Jeroen Dekien
Signed-off-by: Andre Przywara
[1]:
http://lists.infradead.org/piperm
n DTSI and include directly the pine64 DTS]
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/allwinner/Makefile | 5 ++
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 48 ++
.../arm64/boot/dts/allwinner/
Hi Philipp,
sorry for the delay, I was on holidays.
Thanks for putting together the series, this looks very good to me.
One comment below...
On 16/08/17 10:46, Philipp Zabel wrote:
> Split reusable parts out of the sunxi driver, to add a driver for simple
> reset controllers with reset lines tha
Hi,
On 16/08/17 13:52, Eugeniy Paltsev wrote:
> Hi Philipp,
>
> On Wed, 2017-08-16 at 11:46 +0200, Philipp Zabel wrote:
>> The reset-simple driver can be used without changes.
>>
>> Signed-off-by: Philipp Zabel
>> [snip]
>>
>> --- a/drivers/reset/reset-simple.c
>> +++ b/drivers/reset/reset-simpl
Hi,
On 16/08/17 16:11, Philipp Zabel wrote:
> On Wed, 2017-08-16 at 14:12 +0200, Andreas Färber wrote:
>> Hi Andre,
>>
>> Am 16.08.2017 um 13:30 schrieb Andre Przywara:
>>> On 16/08/17 10:46, Philipp Zabel wrote:
>>>> +/**
>>>> + * struct res
Hi,
On 16/08/17 17:41, Andreas Färber wrote:
> Am 16.08.2017 um 17:11 schrieb Philipp Zabel:
>> On Wed, 2017-08-16 at 14:12 +0200, Andreas Färber wrote:
>>> Am 16.08.2017 um 13:30 schrieb Andre Przywara:
>>>> On 16/08/17 10:46, Philipp Zabel wrote:
>>>>&g
Hi,
On 16/08/17 21:55, Alexandru Gagniuc wrote:
>
>
> On 08/16/2017 01:52 PM, Andreas Färber wrote:
>> Am 16.08.2017 um 22:50 schrieb Alexandru Gagniuc:
>>> On 08/16/2017 02:46 AM, Philipp Zabel wrote:
The reset-simple driver can be used without changes.
Signed-off-by: Philipp Zab
Hi,
(sorry for the delay, cleaning up my inbox after holidays)
On 01/08/17 11:50, Alexander Graf wrote:
> Hi Andre,
>
> On 24.07.17 01:23, Andre Przywara wrote:
>> This is a reworked version of my previous post. It addresses Jassi's
>> comments on the driver and als
Hi,
On 26/05/17 04:54, Chen-Yu Tsai wrote:
> On Fri, May 26, 2017 at 6:30 AM, André Przywara
> wrote:
>> On 25/05/17 20:26, Jagan Teki wrote:
>>> From: Jagan Teki
>>>
>>> Orangepi Win/WinPlus is an open-source single-board computer
>>> using the Allwinner A64 SOC.
>>>
>>> A64 Orangepi Win/WinPl
Hi,
On 17/10/17 14:03, Philipp Zabel wrote:
> Add reset line status readback, inverted status support, and socfpga
> device tree quirks to the simple reset driver, and use it to replace
> the socfpga driver.
>
> Signed-off-by: Philipp Zabel
> ---
> Changes since v3:
> - Rebased onto reset/next
Hi,
On 18/10/17 14:50, Philipp Zabel wrote:
> On Wed, 2017-10-18 at 14:00 +0100, Andre Przywara wrote:
>> Hi,
>
> Thank you for the review.
>
>> On 17/10/17 14:03, Philipp Zabel wrote:
>>> Add reset line status readback, inverted status support, and socfpga
>
ize [-Wint-to-pointer-cast]
if ((void *)port->mapbase != ser->iomem_base)
^
Fix that by using the cast on the right hand side instead, as similar
code already does in other drivers.
Signed-off-by: Andre Przywara
---
drivers/tty/serial/atmel_serial.c | 2 +-
1 file changed, 1 insertio
Recent commits made the GIC driver use EOImode=1 for all GICs
that advertise the proper GICC region size.
To let the model benefit from the blessings of that mode, increase
the GICC region to its actual size of 8K.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/arm/foundation-v8.dts | 2
.dts.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/arm/foundation-v8.dts | 223 +
.../arm/{foundation-v8.dts => foundation-v8.dtsi} | 12 --
2 files changed, 2 insertions(+), 233 deletions(-)
copy arch/arm64/boot/dts/arm/{foundation-v8.dts => foundat
Foundation model to run with a GICv3.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/arm/Makefile| 2 +-
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts | 30 +
2 files changed, 31 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot
/foundation-model.php
Andre Przywara (4):
arm64: dts: prepare foundation-v8.dts to cope with GICv3
arm64: dts: Foundation model: increate GICC region to allow EOImode=1
arm64: dts: split Foundation model dts to put the GIC separately
arm64: dts: add .dts for GICv3 Foundation model
arch/arm64
To prepare the ARM foundation model to support GICv3, we adjust
the #address-cells property of the current GICv2 node to be
compatible with the two cells required for GICv3 later.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/arm/foundation-v8.dts | 88 +++
1
Hi Marc,
On 13/10/15 11:44, Marc Zyngier wrote:
> On 13/10/15 10:37, Andre Przywara wrote:
>> The ARMv8 Foundation model sports a command line parameter to use
>> a GICv3 emulation instead of the default GICv2 interrupt controller.
>> Add a new .dts file which reuses most
Hi,
On 21/10/15 10:35, Borislav Petkov wrote:
> On Wed, Oct 21, 2015 at 09:55:43AM +0800, Hanjun Guo wrote:
>> So I think the meaning of those error register is the same, but the way
>> of handle it may different from SoCs, for single bit error:
>>
>> - SoC may trigger a interrupt;
>> - SoC may
On 21/10/15 21:41, Brijesh Singh wrote:
> Add support for Cortex A57 and A53 EDAC driver.
Hi Brijesh,
thanks for the quick update! Some comments below.
>
> Signed-off-by: Brijesh Singh
> CC: robh...@kernel.org
> CC: pawel.m...@arm.com
> CC: mark.rutl...@arm.com
> CC: ijc+devicet...@hellion.org
On 23/10/15 02:41, Hanjun Guo wrote:
> Hi Brijesh,
>
> On 2015/10/22 22:46, Brijesh Singh wrote:
>> Hi Andre,
>>
>> On 10/21/2015 06:52 PM, Andre Przywara wrote:
>>> On 21/10/15 21:41, Brijesh Singh wrote:
>>>> Add support for Cortex A57 and A53 EDA
Hi David,
On 21/09/15 18:17, Andre Przywara wrote:
> With DMA_ERROR_CODE now being dma_addr_t in most architectures, it
> turned out that iommu_tbl_range_alloc (defined in lib/iommu-common.c)
> is actually using a wrong return type.
> This was easily fixed in a previous patch, but n
Hi Linus,
On 11/05/17 15:01, Linus Walleij wrote:
> On Thu, May 4, 2017 at 1:57 AM, Andre Przywara wrote:
>
>> When a pinctrl driver gets interrupted during its probe process
>> (returning -EPROBE_DEFER), the devres system cleans up all allocated
>> resources. Duri
Hi,
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
>
> Add support for this kind of pin controllers.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 +
Hi,
On 11/01/18 10:14, Chen-Yu Tsai wrote:
> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
> wrote:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>>> have no bus gate cl
Hi,
On 11/01/18 10:15, Icenowy Zheng wrote:
>
>
> 于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara 写到:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>>> have no bus g
Hi,
On 11/01/18 10:41, Maxime Ripard wrote:
> On Thu, Jan 11, 2018 at 10:23:52AM +0000, Andre Przywara wrote:
>> Hi,
>>
>> On 11/01/18 10:14, Chen-Yu Tsai wrote:
>>> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
>>> wrote:
>>>> Hi,
>>
Hi,
another take to avoid this patch at all, I just remembered this from an
IRC discussion before:
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
I don't think this is true. The pin controller *needs* an
Hi,
On 20/03/18 14:13, Maxime Ripard wrote:
> On Mon, Mar 19, 2018 at 04:27:36PM +0100, Harald Geyer wrote:
>>> together with all the patches but the
>>> PWM (so I had to drop the backlight node as well).
>>>
>>> Please coordinate with Andre about who should send the PWM support.
>>
>> Seems the p
On Fri, 9 Nov 2018 13:15:47 -0600
Grygorii Strashko wrote:
Hi,
> On 11/8/18 12:14 PM, Grygorii Strashko wrote:
> >
> >
> > On 11/8/18 6:00 AM, Sebastian Andrzej Siewior wrote:
> >> On 2018-11-06 15:34:55 [-0600], Grygorii Strashko wrote:
> >>> Hi All,
> >> Hi,
> >>
> >>> Do anybody tri
auth_probe) {
^
This code was obviously using switch to make use of the fall-through
semantics (without the usual comment, though).
Rewrite that code using if statements to avoid the warning and make
the code a bit more readable on the way.
Signed-off-by: Andre Przywara
---
fs/nfs/nfs4pro
_typeof__(*(ptr)))__cmpxchg_mb((ptr), \
^
kernel/acct.c:174:2: note: in expansion of macro 'cmpxchg'
cmpxchg(&acct->ns->bacct, pin, NULL);
^
Rearrange the macro along the lines of a similar patch for arm64
60010e508111 ("arm64: cmpxchg: update macros to prevent warnings&quo
Hi,
On 26/02/18 15:54, Samuel Holland wrote:
> On 02/26/18 03:26, Maxime Ripard wrote:
>> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote:
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
Is it needed? The bootloader sho
Hi,
On 28/02/18 02:27, Samuel Holland wrote:
> If a reception IRQ is pending when a mailbox channel is shut down (for
> example, if the controller uses threaded interrupts), it is possible for
> mbox_chan_received_data to be called while chan->cl is NULL.
>
> This was found while developing a mai
Hi Samuel,
thank you very much for writing and posting this!
On 28/02/18 08:28, Maxime Ripard wrote:
> Hi,
>
> On Tue, Feb 27, 2018 at 08:27:12PM -0600, Samuel Holland wrote:
>> This mailbox hardware is present in several Allwinner sun8i and sun50i
>> SoCs. Add a device tree binding for it.
>>
>
Hi,
On 01/03/18 10:32, Maxime Ripard wrote:
> On Wed, Feb 28, 2018 at 11:19:11AM -0600, Samuel Holland wrote:
>> Hi,
>>
>> On 02/28/18 02:32, Maxime Ripard wrote:
>>> On Tue, Feb 27, 2018 at 08:27:14PM -0600, Samuel Holland wrote:
+ /*
+ * The failure path should not disable the clock
Hi,
On 26/04/18 15:07, Icenowy Zheng wrote:
> The new Allwinner H6 SoC have 3 MMC controllers. The first and second
> ones are similar to the ones on A64, but the third one adds EMCE
> (Embedded Crypto Engine) support which does hardware transparent crypto
> on the eMMC.
>
> As we still do not ha
Hi,
On 26/04/18 15:07, Icenowy Zheng wrote:
> The Allwinner H6 SoC have 3 MMC controllers.
>
> Add device tree nodes for them.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 56
>
> 1 file changed, 56 insertions(+)
>
> dif
Hi,
On 26/04/18 15:07, Icenowy Zheng wrote:
> The Pine H64 board have a MicroSD slot connected to MMC0 controller of
> the H6 SoC and a eMMC slot connected to MMC2.
>
> Enable them in the device tree.
>
> Signed-off-by: Icenowy Zheng
> ---
> .../boot/dts/allwinner/sun50i-h6-pine-h64.dts |
Hi,
On 27/04/18 09:36, Icenowy Zheng wrote:
>
>
> 于 2018年4月27日 GMT+08:00 上午12:45:38, Andre Przywara 写到:
>> Hi,
>>
>> On 26/04/18 15:07, Icenowy Zheng wrote:
>>> The Allwinner H6 SoC have 3 MMC controllers.
>>>
>>> Add device tre
Hi,
On 27/04/18 09:38, Icenowy Zheng wrote:
>
>
> 于 2018年4月27日 GMT+08:00 上午12:45:24, Andre Przywara 写到:
>> Hi,
>>
>> On 26/04/18 15:07, Icenowy Zheng wrote:
>>> The new Allwinner H6 SoC have 3 MMC controllers. The first and second
>>> ones are simil
Hi Icenowy,
On 27/04/18 08:12, Icenowy Zheng wrote:
>
>
> 于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara 写到:
>> Hi,
>>
>> On 26/04/18 15:07, Icenowy Zheng wrote:
>>> The Pine H64 board have a MicroSD slot connected to MMC0 controller
>> of
>&g
Hi,
On 30/04/18 10:51, Icenowy Zheng wrote:
>
>
> 于 2018年4月30日 GMT+08:00 下午5:47:35, Andre Przywara 写到:
>> Hi Icenowy,
>>
>> On 27/04/18 08:12, Icenowy Zheng wrote:
>>>
>>>
>>> 于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara
>> 写
Hi,
On 01/05/18 16:52, Chen-Yu Tsai wrote:
> On Mon, Apr 30, 2018 at 6:44 PM, Andre Przywara
> wrote:
>> Hi,
>>
>> On 30/04/18 10:51, Icenowy Zheng wrote:
>>>
>>>
>>> 于 2018年4月30日 GMT+08:00 下午5:47:35, Andre Przywara
>>> 写到:
>&
Hi,
On 02/05/18 10:36, Maxime Ripard wrote:
> On Mon, Apr 30, 2018 at 10:47:35AM +0100, Andre Przywara wrote:
>>>> I am just asking because I want to avoid running into the same problem
>>>> as with the A64 before: that future DTs become incompatible with older
>>
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
There are various reasons, including bencmarking, to disable spectrev2
mitigation on a machine. Provide a command-line to do so.
Signed-off-by: Jeremy Linton
Reviewed-by: Andre Przywara
Cheers,
Andre.
Cc: Jonathan Corbet
Cc: linux
cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
+ char *buf)
w/s issue, but it's not critical:
Reviewed-by: Andre Przywara
Cheers,
Andre
+{
+ return sprintf(buf, "Mitigation: __user pointer sanitization\n");
+}
es of that patch into this and move it earlier]
Signed-off-by: Jeremy Linton
Indeed a whitelist is much better.
Reviewed-by: Andre Przywara
Cheers,
Andre.
---
arch/arm64/kernel/cpu_errata.c | 108 +
1 file changed, 56 insertions(+), 52 deletions(-)
diff --
s use this information to our benefit.
Yes, that matches the firmware interface description.
Signed-off-by: Marc Zyngier
Signed-off-by: Jeremy Linton
Reviewed-by: Andre Przywara
Cheers,
Andre.
---
arch/arm64/kernel/cpu_errata.c | 32 +++-
1 file change
);
+
extra empty line
Apart from that picky and unimportant nit it looks alright and compiles
with and without CONFIG_HARDEN_BRANCH_PREDICTOR being defined.
Reviewed-by: Andre Przywara
Cheers,
Andre.
#ifdef CONFIG_KVM_INDIRECT_VECTORS
extern char __smccc_workaround_1_smc_start
_t cpu_show_spectre_v1(struct device *dev, struct
device_attribute *attr,
{
return sprintf(buf, "Mitigation: __user pointer sanitization\n");
}
+
+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
+ char *buf)
w/s issue
Anyway:
R
arm64_set_ssbd_mitigation(bool state)
+{
+ pr_info_once("SSBD, disabled by kernel configuration\n");
Is there a stray comma or is the continuation of some previous printout?
Regardless of that it looks good and compiles with both
CONFIG_ARM64_SSBD defined or not:
Reviewed
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
Return status based on ssbd_state and the arm64 SSBS feature. If
the mitigation is disabled, or the firmware isn't responding then
return the expected machine state based on a new blacklist of known
vulnerable cores.
Signed-off-by: Jeremy Linton
---
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
From: Mian Yousaf Kaukab
Enable CPU vulnerabilty show functions for spectre_v1, spectre_v2,
meltdown and store-bypass.
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Jeremy Linton
Reviewed-by: Andre Przywara
Thanks,
Andre.
---
arch
1 - 100 of 608 matches
Mail list logo
