Hi,
On Tuesday 27 August 2013 01:44 PM, Tomasz Figa wrote:
Hi Laurent,
On Tuesday 27 of August 2013 10:02:39 Laurent Pinchart wrote:
Add DT bindings for the pcf857x-compatible chips and parse the device
tree node in the driver.
Signed-off-by: Laurent Pinchart
---
.../devicetree/bindings/gp
Hi,
On Wednesday 10 July 2013 06:38 PM, Pali Rohár wrote:
* On RX-51 probing for acx565akm driver is later then for omapfb which cause
that omapfb probe fail and framebuffer is not working
* EPROBE_DEFER causing that kernel try to probe for omapfb later again which
fixing this problem
* Witho
Hi,
On Monday 17 June 2013 02:35 PM, Linus Walleij wrote:
On Thu, Jun 6, 2013 at 4:05 PM, Archit Taneja wrote:
Add code to parse the GPIO expander Device Tree node and extract platform data
out of it, and populate the struct 'pcf857x_platform_data' maintained by the
driver. Th
Hi,
On Wednesday 05 June 2013 10:59 PM, Emil Goode wrote:
It's not necessary to free memory allocated with devm_kzalloc
in a remove function and using kfree leads to a double free.
Looks fine to me. Tomi, could you take this for 3.11?
Archit
Signed-off-by: Emil Goode
---
drivers/video/o
ly
Signed-off-by: Archit Taneja
---
.../devicetree/bindings/gpio/gpio-pcf857x.txt | 44 +
drivers/gpio/gpio-pcf857x.c| 57 --
2 files changed, 97 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings
On 6/14/2016 5:15 PM, Yakir Yang wrote:
RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.
Also same misc fix to analogix_dp driver:
- Hotplug invalid which report by Dan Carpenter
- Make panel detect to an optional action
- co
Hi,
On 6/20/2016 12:44 PM, Nicolas Boichat wrote:
ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
that has an internal microcontroller.
The only reason a Linux kernel driver is necessary is to reject
resolutions that require more bandwidth than what is available on
the DP
On 6/22/2016 7:54 AM, Yakir Yang wrote:
Archit,
On 06/21/2016 09:46 PM, Archit Taneja wrote:
On 6/14/2016 5:15 PM, Yakir Yang wrote:
RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.
Also same misc fix to analogix_dp
On 6/22/2016 8:14 AM, Nicolas Boichat wrote:
Hi Archit,
Thanks for your reply.
On Tue, Jun 21, 2016 at 11:39 PM, Archit Taneja wrote:
Hi,
On 6/20/2016 12:44 PM, Nicolas Boichat wrote:
ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
that has an internal
On 09/17/2016 04:47 AM, John Stultz wrote:
This patch adds support to Audio for both adv7511 and adv7533
bridge chips.
This patch was originally from [1] by Lars-Peter Clausen
and was adapted by Archit Taneja and
Srinivas Kandagatla .
Then I heavily reworked it to use the hdmi-codec driver
On 09/17/2016 04:47 AM, John Stultz wrote:
From: Srinivas Kandagatla
This patch enables the Audio Data and Clock pads to the adv7533 bridge.
Without this patch audio can not be played.
Cc: David Airlie
Cc: Archit Taneja
Cc: Laurent Pinchart
Cc: Wolfram Sang
Cc: Srinivas Kandagatla
Cc
Hi Peter,
On 09/26/2016 01:57 PM, Peter Senna Tschudin wrote:
Patch 1/4 is already on linux-next, but what about this one? Ping?
I'd posted some queries a couple of times which you didn't answer to.
Could you please respond to them before we try to get this merged?
Archit
On Tuesday, Augus
Hi,
On 09/26/2016 02:28 PM, Peter Senna Tschudin wrote:
Hi Archit,
On Monday, September 26, 2016 10:31 CEST, Archit Taneja
wrote:
Hi Peter,
On 09/26/2016 01:57 PM, Peter Senna Tschudin wrote:
Patch 1/4 is already on linux-next, but what about this one? Ping?
I'd posted some qu
Hi,
Some comments.
On 08/09/2016 10:11 PM, Peter Senna Tschudin wrote:
Add a driver that create a drm_bridge and a drm_connector for the LVDS
to DP++ display bridge of the GE B850v3.
There are two physical bridges on the video signal pipeline: a
STDP4028(LVDS to DP) and a STDP2690(DP to DP++).
On 09/26/2016 05:24 PM, Peter Senna Tschudin wrote:
On Monday, September 26, 2016 12:29 CEST, Archit Taneja
wrote:
Hi,
Some comments.
Thank you for the review!
On 08/09/2016 10:11 PM, Peter Senna Tschudin wrote:
Add a driver that create a drm_bridge and a drm_connector for the LVDS
On 9/7/2016 4:25 PM, Srinivas Kandagatla wrote:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller, there is
also a common block which is shared across all the 3 ports.
Signed-off-by:
Signed-off-by: Jose Abreu
Acked-by: Russell King
Cc: Carlos Palminha
Cc: Archit Taneja
Cc: David Airlie
Cc: Russell King
Cc: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
---
drivers/gpu/drm/bridge/dw-hdmi.c | 7 ---
1 file changed, 4 insertions(+), 3
Hi,
On 8/30/2016 5:11 AM, John Stultz wrote:
From: Andy Green
Set the initial audio packet settings to allow the audio
driver to work.
Cc: David Airlie
Cc: Archit Taneja
Cc: Laurent Pinchart
Cc: Wolfram Sang
Cc: Srinivas Kandagatla
Cc: "Ville Syrjälä"
Cc: Boris Brezillon
time. Before starting of any operation, this buffer will
be synced for device operation and after operation
completion, it will be synced again for CPU.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c
.
- The size of the buffer used for BAM transactions
is calculated based on the NAND device with the maximum page size,
among all the devices connected to the
controller.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 94
using
BAM.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
*/
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
void *
nandc_set_readl(nandc, 0, 0, size, 1);
The READ_LOC reg should already be set up in update_rw_regs, right? If so, we
could
drop this line.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
config_nand_single_cw_page_read(nandc);
@@ -1502,6 +1551,7 @@ static int qcom_nandc_r
codeword/page detection controller. This register should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 21 +
1 file
e required later if we want the controller to support multiple NAND chips?
If not,
then we could consider dropping this. Anyway, that can be posted as a separate
patch
later.
Reviewed-by: Archit Taneja
Thanks,
Archit
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
write_reg_dma(nandc, NAND_
descriptor formation function.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
in the registers
defined above, it might get confusing for someone who doesn't have access
to the HW docs. Could you explicitly mention in this comment all the register
names that are required to go through this translation, it should make things
more readable. With that:
Reviewed-by: Archit T
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 19
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 108 +++---
1 file changed, 92 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index d17c466
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ8074 QPIC NAND controller
version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers
starting offset is 0x7000.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ4019 QPIC NAND controller
version 1.4.0 which uses BAM DMA.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 10 ++
1 file changed, 10
dge lookup/attach into the component bind process.
Reviewed-by: Archit Taneja
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_dsi.c | 97 +--
1 file changed, 57 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/g
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference the NULL in the hotplug
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device includes both
Video/Sound, like HDMI.
As far as I
On 05/26/2017 09:46 AM, Archit Taneja wrote:
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device
On 05/25/2017 07:49 PM, Jose Abreu wrote:
Introduce a new helper function which calls mode_valid() callback
for all bridges in an encoder chain.
Reviewed-by: Archit Taneja
Signed-off-by: Jose Abreu
Reviewed-by: Daniel Vetter
Cc: Carlos Palminha
Cc: Ville Syrjälä
Cc: Dave Airlie
Cc
mode_valid()
will handle the mode validation.
Reviewed-by: Archit Taneja
NOTE: Only compile tested.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 13
been tested on Meson by Neil.
Since this also touches rockchip/imx drm driver files, can I get an
OK from the maintainers to pull the changes via drm-misc?
Thanks,
Archit
Signed-off-by: Jose Abreu
Acked-by: Neil Armstrong
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej
need to use mode_fixup() callback as mode_valid()
will handle the mode validation.
NOTE: Only compile tested.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
---
drivers/gpu/drm/bridge/analogix
Hi,
On 10/26/2017 06:39 AM, Brian Norris wrote:
On Wed, Oct 25, 2017 at 03:57:19AM -0400, Sean Paul wrote:
Archit asked a question about moving to
dw-mipi-dsi
That question made me think though: this approach seems backwards. It
seems like someone did copy/paste/fork, and then we're asking th
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/d
On 10/25/2017 01:34 PM, Sean Paul wrote:
On Wed, Oct 25, 2017 at 11:51:01AM +0800, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
Signed-off-by:
Acked-by: Archit Taneja
Acked-by: Jingoo Han
Best regards,
Jingoo Han
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 50 +
-
drivers/gpu/drm/exynos/exynos_dp.c | 26 ++-
dr
peripheral driver might have an unregistered device pointer without
being aware of it.
Some comments on these would help.
[1]: https://lkml.org/lkml/2015/6/30/42
Archit Taneja (5):
drm/dsi: Refactor device creation
drm/dsi: Try to match non-DT dsi devices
drm/dsi: Check for used channels
dr
be removed. This does leave
the possibility of the host removing the dsi device without the
peripheral driver being aware of it. I don't know a good way to solve
this. Some suggestions here would be of help too.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 7 +
list of all the hosts DSI that are currently registered.
This list will be used to find the mipi_dsi_host corresponding to the
device_node passed in of_find_mipi_dsi_host_by_node.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 30 ++
includ
pi) perform a non-DT match by comparing the
device name and entries in the driver's id_table. The id_table structs
for different buses are defined in "include/linux/mod_devicetable.h", I
didn't want to touch that for now.
Signed-off-by: Archit Taneja
device_new as a standalone way to create
a dsi device not available via DT.
The new device creation process tries to closely follow what's been done
in i2c_new_device in i2c-core.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 61 +--
e populated via
DT. Now that we also support creating devices manually, we could end up
in a situation where a driver tries to create a device with a virtual
channel already taken by a device populated in DT.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/drm_mipi_dsi.c | 26 +++
Hi,
On 10/06/2015 02:47 PM, Brian Norris wrote:
Hi Archit,
On Mon, Oct 05, 2015 at 12:21:54PM +0530, Archit Taneja wrote:
On 10/02/2015 08:35 AM, Brian Norris wrote:
On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
The Qualcomm NAND controller is found in SoCs like IPQ806x
: Archit Taneja
Cc: Archit Taneja
Cc: Hai Li
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 91 +
drivers/clk/qcom/gcc-msm8916.c | 14 +--
drivers/clk/qcom/mmcc-apq8084.c | 18
if (ret < 0) {
Looks good to me.
Reviewed-by: Archit Taneja
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majo
uch prints when the underlying regulator doesn't support DRMS.
Signed-off-by: Archit Taneja
---
drivers/regulator/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 3c3137a..f2262fa 100644
--- a/drivers/re
Hi,
On 9/4/2015 12:00 AM, Hai Li wrote:
Lane swap configuration is based on the board design.
This change allows the DSI host to get this information
from device tree, instead of hardcoding in driver.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++
d
Thierry,
On 08/21/2015 11:39 AM, Archit Taneja wrote:
On 08/20/2015 05:18 PM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote:
Hi Thierry, Lucas,
On 08/19/2015 08:32 PM, Thierry Reding wrote:
On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote
the errors go away.
Fixes: 5532cfb567fe ("clk: qcom: mmcc-8960: Add DSI related clocks")
Cc: Archit Taneja
Signed-off-by: Stephen Boyd
---
Acked-by: Archit Taneja
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, hosted by The Linux Foundation
--
To u
Hi Brian,
Thanks for the review.
On 10/02/2015 08:35 AM, Brian Norris wrote:
Hi Archit,
On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote:
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External
idge_mode_set(struct drm_bridge *bridge,
void drm_bridge_pre_enable(struct drm_bridge *bridge);
void drm_bridge_enable(struct drm_bridge *bridge);
+#ifdef CONFIG_DRM_PANEL
+struct drm_bridge *drm_panel_bridge_add(struct drm_panel *panel,
+ u32 connector_type);
+void drm_panel_bridge_remove(struct drm_bridge *bridge);
+#endif
Shouldn't this be CONFIG_DRM_PANEL_BRIDGE?
As I mentioned on irc, I was facing some build issues with this patch
applied. Once we sort that out:
Acked-by: Archit Taneja
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
mode_valid() callback
for all bridges in an encoder chain.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Alexey Brodkin
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Andrzej Hajda
Cc: Archit Taneja
---
drivers/gpu/drm/drm_bridge.c | 33 +
include/drm
On 05/12/2017 04:31 PM, Laurent Pinchart wrote:
Hi Archit,
On Friday 12 May 2017 16:20:07 Archit Taneja wrote:
On 05/12/2017 03:08 PM, Laurent Pinchart wrote:
On Wednesday 10 May 2017 17:14:33 Daniel Vetter wrote:
On Wed, May 10, 2017 at 04:41:09PM +0300, Ville Syrjälä wrote:
On Tue, May
On 01/26/2018 06:16 AM, Brian Norris wrote:
On Thu, Jan 25, 2018 at 11:38:00AM +0100, Philippe Cornu wrote:
The dw_mipi_dsi_host_transfer() must return the number of
bytes transmitted/received on success instead of 0.
Note: As the read feature is not implemented, only the
transmitted number of
On 01/26/2018 06:14 AM, Brian Norris wrote:
On Thu, Jan 25, 2018 at 11:37:59AM +0100, Philippe Cornu wrote:
The dcs/generic dsi read feature is not yet implemented so it
is important to warn the host_transfer() caller in case of
read operation requests.
Signed-off-by: Philippe Cornu
Awesom
Hi,
On 01/22/2018 06:20 PM, Kieran Bingham wrote:
The ADV7511 has four 256-byte maps that can be accessed via the main I²C
ports. Each map has it own I²C address and acts as a standard slave
device on the I²C bus.
Allow a device tree node to override the default addresses so that
address confli
On 01/26/2018 03:24 PM, Philippe CORNU wrote:
Hi Brian,
And a big thanks for your Tested-by
On 01/25/2018 11:47 PM, Brian Norris wrote:
On Thu, Jan 25, 2018 at 7:55 AM, Philippe Cornu wrote:
The "adjusted_mode" clock value (ie the real pixel clock) is more
accurate than "mode" clock value (
On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
Parts of PHY code could be useful also for custom PHYs. For example,
Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
with few additional memory mapped registers, so most of the Synopsys PHY
related code could be reused.
It turns o
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
We inited connector in attach(), so need a detach() to cleanup.
Also fix wrong use of dw_hdmi_remove() in bind().
Signed-off-by: Jeffy Chen
Signed-off-by: Thierry Escande
Reviewed-by: Archit Taneja
---
drivers/gpu/drm
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
Let plat drivers own the drvdata, so that they could cleanup resources
in their unbind().
Signed-off-by: Jeffy Chen
Signed-off-by: Thierry Escande
Reviewed-by: Neil Armstrong
Reviewed-by: Archit Taneja
---
drivers/gpu
On 01/09/2018 08:18 PM, Thierry Escande wrote:
Hi,
This patchset makes edp display work on Chromebook kevin.
This patchset has been originally posted by Jeffy Chen and the 2 first
commits from the previous version (v6) are already merged in mainline.
This v7 has been rebased on top of next-20
On 12/12/2017 06:40 AM, Nickey Yang wrote:
Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.
Reviewed-by: Archit Taneja
Signed-off-by: Nickey Yang
Signed-off-by: Brian Norris
Reviewed-by: Brian Norris
Reviewed-by: Sean Paul
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
Add missing pm_runtime_disable() in bind()'s error handling path.
Also cleanup encoder & connector in unbind().
I guess you'll need to drop this commit if this patch goes in first:
https://patchwork.kernel.org/patch/10106105/
On 01/10/2018 08:03 PM, Andrzej Hajda wrote:
On 09.01.2018 21:32, Brian Norris wrote:
We're filling the "remainder" word with little-endian data, then writing
it out to IO registers with endian-correcting writel(). That probably
won't work on big-endian systems.
Let's mark the "remainder" var
On 01/10/2018 02:02 AM, Brian Norris wrote:
This takes care of 2 TODOs in this driver, by using the common DSI
packet-marshalling code instead of our custom short/long write code.
This both saves us some duplicated code and gets us free support for
command types that weren't already part of our
Hi,
On Friday 09 March 2018 07:21 PM, Jacopo Mondi wrote:
Hello,
after some discussion on the proposed bindings for generic lvds decoder and
Thine THC63LVD1024, I decided to drop the THC63 specific part and just live with
a transparent decoder that does not support any configuration from DT.
Hi,
On Tuesday 06 March 2018 03:23 PM, Neil Armstrong wrote:
Hi Architt,
On 23/02/2018 12:44, Neil Armstrong wrote:
The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
identified needing this workaround.
This patch adds the corresponding version to enable a single iteratio
Signed-off-by: Stefan Agner
Reviewed-by: Archit Taneja
Archit
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..d729b2b4b66d 1006
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Yakir Yang
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Reviewed-by: Archit Taneja
Cc: 征增 王
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Reviewed-by: Archit Taneja
this patch,
you can let it stay if it happens to cause conflicts with future
patches. Other than that:
Reviewed-by: Archit Taneja
Thanks,
Archit
#include
#include
@@ -35,6 +36,8 @@
#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
+static const
exiting.
With the subject fix:
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: Sonny Rao
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to enable video before analogix_dp_is_video_stream_on(), so
we can get the right video stream status.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
Signed-off-by:
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off
27;s reset fast_train_enable in
analogix_dp_bridge_disable();
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu/
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Reviewed-by: Archit
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by:
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
There was a 1ms delay to detect the hpd signal, which is too short to
detect a short pulse. This patch extends this delay to 100ms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征
, we just
enable it at the beginning of link training and then keep it on all the
time.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to check the dpcd write/read return value to see whether the
write/read was successful
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Kristian H. Kristensen
Signed-off-by: Lin Huang
Signed-off
ht? AUX_PD
sounds like just one of the fields of the register.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
Tested
EMOTEIO;
A couple of ETIMEDOUTs have been replaced with EREMOTEIOs after this
change. Maybe we set it the error no in ret and return ret?
With those changes,
Reviewed-by: Archit Taneja
Thanks,
Archit
}
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
If we failed disable psr, it would hang the display until next psr
cycle coming. So we should restore psr->state when it failed.
For the bridge part,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tom
streamclk is ok if we wait enough time,
it does no effect on display.
Let's change this error to warn.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signe
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Reviewed-by: Archit Taneja
edp phy,
BIT 7 reserved
BIT 6 RK_VID_CAP_FUNC_EN_N
BIT 5 RK_VID_FIFO_FUNC_EN_N
So, we should do some private operations to Rockchip.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by
was finding AUX channel errors and eventually
reported "Failed to apply PSR", where I had a kgdb breakpoint. Presumably
the device would have eventually given up and shut down anyway, but it
seems better to fix the order to be more correct.
Reviewed-by: Archit Taneja
Thanks,
Archit
C
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
It's too early to detect fast link training, if other step after it
failed, we will set fast_link flag to 1, and retry set_bridge again. In
this case we will power down and power up panel power supply, and we
wi
bug.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: 征增 王
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu/drm/bridge/analogix/analogi
could adjust
the comment, but it seems more likely that we want the same retry
behavior across all platforms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征增 王
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by:
Hi,
On 01/08/2015 08:56 AM, Andy Gross wrote:
Signed-off-by: Andy Gross
+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
+ struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned long flags,
+ void *co
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