>From 6f439bdcc027fe9c0cb4ce2ca4f7d1879d84097d Mon Sep 17 00:00:00 2001
From: Bin Gao
Date: Thu, 18 Oct 2012 16:13:46 -0700
Subject: [PATCH] arch/x86/Kconfig: not select X86_MPPARSE when SFI is present
MPS tables are not needed for systems that have proper ACPI support.
This is also true
MPS tables are not needed for systems that have proper ACPI support.
This is also true for systems that have SFI in place.
So this patch is to exclude X86_MPPARSE when either ACPI or SFI is present.
Signed-off-by: Bin Gao
---
arch/x86/Kconfig |2 +-
1 files changed, 1 insertions(+), 1
MPS tables are not needed for systems that have proper ACPI support.
This is also true for systems that have SFI in place.
So this patch allows the configuration (turning off) of CONFIG_X86_MPPARSE
when either ACPI or SFI is present.
Signed-off-by: Bin Gao
---
arch/x86/Kconfig |2 +-
1
Yes, your suggested descriptions more match the change.
I'm sending a new patch for your review. Thanks.
-Bin
On Thu, Oct 25, 2012 at 09:57:52AM +0200, Ingo Molnar wrote:
>
> * Bin Gao wrote:
>
> > MPS tables are not needed for systems that have proper ACPI support.
>
On Fri, Jun 14, 2013 at 10:29:09AM +0300, Andy Shevchenko wrote:
> On Tue, Jun 11, 2013 at 8:11 PM, Bin Gao wrote:
> > On Sun, Jun 09, 2013 at 10:53:35PM +0300, Andy Shevchenko wrote:
> >> Please, try to avoid top posting in the future emails.
> >>
> >> On F
.
Signed-off-by: Bin Gao
---
drivers/i2c/i2c-core.c | 17 +
include/linux/i2c.h|1 +
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 48e31ed..17683de6 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers
t 9:33 PM, Bin Gao wrote:
> > There is a requirement to get the i2c_client pointer dynamically without
> > knowing the bus and slave address. But we do know the client name,
> > i.e. the name in the i2c_board_info. This patch is to fit this requirement.
> >
> > A go
On 6/19/2013 3:13 AM, Wolfram Sang wrote:
Even you prefer to extend v4l2, you still need this helper.
The idea is just to move the unregister/register from a specific ISP driver
to v4l2.
I think you misunderstood my pionts somehow. Let me clarfiy a little bit:
Current solution:
1. Platform co
On Sun, Jun 09, 2013 at 10:53:35PM +0300, Andy Shevchenko wrote:
> Please, try to avoid top posting in the future emails.
>
> On Fri, Jun 7, 2013 at 12:26 AM, Bin Gao wrote:
> > With v4l2, the camera sensor i2c devices are taken over by v4l2 master
> > driver, i.e. IS
On Wed, May 01, 2013 at 11:17:10AM -0600, Bjorn Helgaas wrote:
> Is there any possibility of multi-function devices at bus 0, device 0, 2, or
> 3?
>
> What about bridges -- can any of these be a bridge?
>
> If either of those could happen, these checks could be too specific.
0:2:0 and 0:3:0 are
On Mon, May 06, 2013 at 10:38:55AM -0700, Bjorn Helgaas wrote:
> Please use the conventional Linux PCI address formatting
> (:BB:dd.f, where = domain (optional, often omitted if ==
> 0), BB = bus, dd = device, f = function), because this is quite
> confusing.
Yes, will do.
> You say
On Mon, May 06, 2013 at 11:56:38AM -0700, Bjorn Helgaas wrote:
> I hate it when I go to the trouble of reviewing something and asking
> relevant questions, and then people ignore the questions :(
Sorry for that.
> I'd still like to know whether multi-function devices are possible at
> bus 0, devi
devices. Instead,
always use type 1 for those devices.
Signed-off-by: Bin Gao
---
arch/x86/pci/mrst.c | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 6eb18c4..0e0fabf 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86
This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC.
This driver is based on gpio-crystalcove.c.
Signed-off-by: Ajay Thomas
Signed-off-by: Bin Gao
Reviewed-by: Andy Shevchenko
Reviewed-by: Mika Westerberg
---
Changes in v6:
- Removed unnecessary wcove_gpio_remove
: Yegnesh S Iyer
Signed-off-by: Bin Gao
Changes in v3:
- Moved driver data from mfd domain to the driver
- Minor coding style related cleanup
Changes in v2:
- Removed unnecessary request_threaded_irq() - we should be only
using devm_request_threaded_irq() with virq
---
drivers/thermal
On Tue, Jun 28, 2016 at 03:58:49PM +0100, Lee Jones wrote:
> On Mon, 27 Jun 2016, Bin Gao wrote:
>
> > This patch adds the mapping of PMIC ADC channel to thermal zone and
> > USB type-C resources. This mapping is used in the pmic thermal driver
> > to notify the therma
The Intel Whiskey Cove PMIC includes several function units, e.g.
ADC, thermal, USB Type-C, GPIO, etc. The corresponding device has
to be created in the mfd driver(intel_soc_pmic_bxtwc.c). This change
adds the USB Type-c device.
Signed-off-by: Bin Gao
---
drivers/mfd/intel_soc_pmic_bxtwc.c | 23
>
> Looks good. I have couple of minor comments, see below.
Thanks for review again.
>
> > + * Copyright (C) 2015 Intel Corporation. All rights reserved.
>
> It is 2016 now isn't it? :-)
Will fix this in v3.
> > +#define DRV_NAME "bxt_wcove_gpio"
>
> Drop this.
We have _TWO_ places using DRV_
On Fri, Jun 17, 2016 at 09:01:59AM +0100, Lee Jones wrote:
> > +static struct trip_config_map str0_trip_config[] = {
> > + {
> > + .irq_reg = BXTWC_THRM0IRQ,
> > + .irq_mask = 0x01,
> > + .irq_en = BXTWC_MTHRM0IRQ,
> > + .irq_en_mask = 0x01,
> > +
This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC.
This driver is based on gpio-crystalcove.c.
Signed-off-by: Ajay Thomas
Signed-off-by: Bin Gao
---
Changes in v3:
- Fixed the year in copyright line(2015-->2016).
- Removed DRV_NAME macro.
- Added kernel-doc
On Mon, Jun 20, 2016 at 09:52:00AM +0100, Lee Jones wrote:
> > > > > +static struct trip_config_map str3_trip_config[] = {
> > > > > + {
> > > > > + .irq_reg = BXTWC_THRM2IRQ,
> > > > > + .irq_mask = 0x10,
> > > > > + .irq_en = BXTWC_MTHRM2IRQ,
> > > > > +
On Mon, Jun 20, 2016 at 04:20:26PM -0700, John Stultz wrote:
> On Fri, Jun 17, 2016 at 12:48 AM, Thomas Gleixner wrote:
> > On Thu, 16 Jun 2016, Bin Gao wrote:
> >
> >> Unlike PIT based calibration which counts TSC cycles against another timer,
> >> MSR or CPU
On Tue, Jun 21, 2016 at 02:19:57AM +0300, Andy Shevchenko wrote:
> My comments below.
Thanks for your review.
> > +config GPIO_WHISKEY_COVE
> > + tristate "GPIO support for Whiskey Cove PMIC"
> > + depends on INTEL_SOC_PMIC
> > + select GPIOLIB_IRQCHIP
> > + help
> > +
On Wed, Jul 27, 2016 at 11:21:13AM +0200, Oliver Neukum wrote:
> On Tue, 2016-07-26 at 11:37 -0700, Bin Gao wrote:
> > +#define MAKE_HEADER(port, header, msg, objs) \
> > +do { \
> > + header->type = msg; \
> > + header->data_role = PD_DATA_ROLE_UF
On Wed, Jul 27, 2016 at 11:13:43AM +0300, Felipe Balbi wrote:
>
> Hi,
>
> Bin Gao writes:
> > This patch implements a simple USB Power Delivery sink port state machine.
> > It assumes the hardware only handles PD packet transmitting and receiving
> > over the CC li
On Wed, Aug 24, 2016 at 10:51:20AM +0200, Thomas Gleixner wrote:
> On Tue, 16 Aug 2016, Bin Gao wrote:
> > On some newer Intel x86 processors/SoCs the TSC frequency can be directly
> > calculated by factors read from specific MSR registers or from a cpuid
> > leaf (0x15). TSC
Peter Hurley,
First of all, thank you for your reviewing.
Please see my answers below.
On Tue, May 26, 2015 at 01:12:34PM -0400, Peter Hurley wrote:
> Hi Bin,
>
> Please don't drop lists (or other addressees) from patch revisions.
>
> [ +cc linux-serial]
Will fix this.
> Please update Document
On Sun, May 24, 2015 at 12:52:25PM -0700, Greg Kroah-Hartman wrote:
> > Signed-off-by: Bin Gao
> > ---
> > Changes in v4:
> > - moved PCI_EARLY definition from arch/x86/Kconfig to drivers/pci/Kconfig
> > - added 'earlyprintk' for x86 as alias to the ea
On Wed, May 27, 2015 at 08:21:21PM -0400, Peter Hurley wrote:
> I meant that the patch hunk below should be moved to patch
> 2/2, and the purpose of patch 2/2 should be to replace x86-specific
> earlyprintk=pciserial with arch-independent earlyprintk=pciserial.
>
> There are 2 reasons for my sugge
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
Changes in v6: None
Changes in v5:
- updated Documentation/kernel-parameters.txt.
- moved earlyprintk= to patch 2/2 (requires x86 people's r
x27;commit 5140fda16051 ("Specify PCI based UART for earlyprintk")'
is removed. And its equivalent function will be available from
uart8250 early console driver.
Signed-off-by: Bin Gao
---
Changes in v6:
- limited the early parameter 'earlyprintk' in drivers/tty/seri
On Tue, Jun 02, 2015 at 01:54:33PM +0200, Ingo Molnar wrote:
>
> * Bin Gao wrote:
>
> > The arch independent uart8250 early console driver has good support for
> > memory
> > mapped and io port based 8250 uarts. Since pci is arch independent so it's
> >
On Tue, Jun 02, 2015 at 11:46:02PM +0200, Ingo Molnar wrote:
> So the format on x86 used to be:
>
> earlyprintk=serial,ttyS0,115200
>
> does that work too?
>
> Thanks,
>
> Ingo
Just tested it, and yes it works.
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On Tue, Jun 02, 2015 at 11:07:39PM +0200, Thomas Gleixner wrote:
> What about the memory mapped uarts which have been source of trouble
> in the past?
>
> Thanks,
>
> tglx
Not sure which specific early console you are referring to.
Currently we have serial, ttyS, vga, dbgp, xen, efi and pc
On Tue, Jun 02, 2015 at 01:37:52PM -0700, Yinghai Lu wrote:
> how about
> earlyprintk=serial,ttyS0
> earlyprintk=ttyS0
>
> Thanks
>
> Yinghai
Yes, both work.
-Bin
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Mor
On Wed, Jun 03, 2015 at 12:16:36AM +, Anderson, Stuart R wrote:
> Bin, et al,
>
> What we are losing here is the ability to specify a UART by its bus address
> instead of just supplying the memory or io address. There are some cases
> where this is useful, though I admit it is probably not goi
On Wed, Jun 03, 2015 at 08:35:29AM -0400, Peter Hurley wrote:
> > +/* x86 uses "earlyprintk=xxx", so we keep the compatibility here */
> > +#ifdef CONFIG_X86
> > +static int __init param_setup_earlycon_x86(char *buf)
> > +{
> > + return param_setup_earlycon(buf);
> > +}
> > +early_param("earlypri
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
Changes in v5:
- updated Documentation/kernel-parameters.txt.
- moved earlyprintk= to patch 2/2 (requires x86 people's review).
- rolled ba
x27;commit 5140fda16051 ("Specify PCI based UART for earlyprintk")'
is removed. And its equivalent function will be available from
uart8250 early console driver.
Signed-off-by: Bin Gao
---
Changes in v5:
- moved earlyprintk= (an alias to earlycon=) from patch 1/2 to patch 2/
> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a3acbac2ee72$
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
> local_irq_save(flags);
> i = try_msr_calibrate_tsc(&fast_calibrate);
> lo
On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
> Actually it does not work. I had the fallback path still in the patch when
> I tried.
Let's merge the ptach v2 then(continue on msr calibration retuning 0).
All supported SoCs now have the correct frequency ID coding
so continuing
debugging on
embedded systems.
Signed-off-by: Bin Gao
---
drivers/misc/Kconfig| 1 +
drivers/misc/Makefile | 1 +
drivers/misc/rawio/Kconfig | 21 ++
drivers/misc/rawio/Makefile | 1 +
drivers/misc/rawio/rawio.c | 514
include/linux
With pci rawio driver, you can read/write any pci config space register
by debug fs interface. This driver is based on the rawio framework.
Signed-off-by: Bin Gao
---
drivers/misc/rawio/Kconfig | 15 +++
drivers/misc/rawio/Makefile| 1 +
drivers/misc/rawio/rawio_pci.c | 235
To read/write registers from a device is very important on embedded system,
especially SoC systems. Physically there could be different types of devices
based on bus tyes, e.g. PCI devices, I2C (slave)devices, I/O devices(memory
mapped), inter-processor devices, etc. Typically there are userland
to
With i2c rawio driver, you can read/write registers from any i2c
client(slave) device via debug fs interface.
This driver is based on the rawio framework.
Signed-off-by: Bin Gao
---
drivers/misc/rawio/Kconfig | 11 ++
drivers/misc/rawio/Makefile| 1 +
drivers/misc/rawio/rawio_i2c.c
With iomem rawio driver, you can read/write memory mapped registers
from any I/O device via debug fs interface.
This driver is based on the rawio framework.
Signed-off-by: Bin Gao
---
drivers/misc/rawio/Kconfig | 12 ++
drivers/misc/rawio/Makefile | 1 +
drivers/misc/rawio
On Tue, Oct 22, 2013 at 06:44:06AM +0100, Greg Kroah-Hartman wrote:
> So, just because userspace is "hard" you want to add stuff to the kernel
> instead.
>
Well, there are other reasons - "hard" is just one of them.
For instance, on some platforms with runtime pm enabled, access to registers
of a
On Tue, Oct 22, 2013 at 06:45:38AM +0100, Greg Kroah-Hartman wrote:
>
> Oh, one more technical thing, you totally fail to document the
> user/kernel api you have just created.
Yes, this is required to be done. Will fix it.
> You are parsing userspace data in ways that I really don't understand a
On Tue, Oct 22, 2013 at 10:14:00AM -0700, Guenter Roeck wrote:
> >
> > You can already do this today for PCI with the UIO framework, right?
> > Why duplicate that functionality here with another userapce API that we
> > will then have to maintain for the next 40+ years?
> >
> Same for i2c, where
On Thu, Jul 23, 2015 at 03:21:27PM -0700, Greg Kroah-Hartman wrote:
> > +config PCI_EARLY
> > + bool "Early PCI access"
> > + depends on PCI
> > + default n
>
> Default is always 'n' so this isn't needed here.
Will fix this.
> > diff --git a/drivers/tty/serial/serial_core.c
> > b/drivers/
On Wed, May 20, 2015 at 11:16:25AM +0200, Paul Bolle wrote:
> What I should have asked is: do you expect architectures other than X86
> to set HAVE_EARLY_PCI? Because then you should put that Kconfig entry in
> a file reachable by all architectures. Say, in init/Kconfig or in
> drivers/tty/serial/K
On Wed, May 20, 2015 at 07:50:12PM +0200, Paul Bolle wrote:
> That makes more sense. So v4 will put HAVE_EARLY_PCI in a Kconfig under
> drivers/pci/?
>
Yes.
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More majordo
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
arch/x86/Kconfig | 1 +
drivers/pci/Kconfig | 11 +++
drivers/tty/serial/earlycon.c| 9 +++
drivers/tty/serial
x27;commit 5140fda16051 ("Specify PCI based UART for earlyprintk")'
is removed. And its equivalent function will be available from
uart8250 early console driver.
Signed-off-by: Bin Gao
---
arch/x86/kernel/early_printk.c | 180 -
1 file chang
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
Changes in v4:
- moved PCI_EARLY definition from arch/x86/Kconfig to drivers/pci/Kconfig
- added 'earlyprintk' for x86 as alias to the e
On Wed, May 20, 2015 at 09:31:45PM -0700, Greg Kroah-Hartman wrote:
> What changed in this version?
>
> You can't just put "v4" without giving us some hint as to the
> differences here, sorry.
I just resent [PATCH v4 1/2] with "Changes in v4" added.
There is no change for patch 2/2 since the firs
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
Changes in v4:
- moved PCI_EARLY definition from arch/x86/Kconfig to drivers/pci/Kconfig
- added 'earlyprintk' for x86 as alias to the e
x27;commit 5140fda16051 ("Specify PCI based UART for earlyprintk")'
is removed. And its equivalent function will be available from
uart8250 early console driver.
Signed-off-by: Bin Gao
---
arch/x86/kernel/early_printk.c | 180 -
1 file chang
> On Wed, May 13, 2015 at 11:08:44PM +0100, One Thousand Gnomes wrote:
>
> We've already got support for this
>
> commit ea9e9d8029020d438b0717ffddf65140fda16051
>
>
> I actually think the fact you've put it into drivers/tty is better as PCI
> is generic and PCI serial boot likewise. However it
>From 0d02240f022c8aca593c42a7220699dbbe37f292 Mon Sep 17 00:00:00 2001
From: Bin Gao
Date: Tue, 12 May 2015 16:40:27 -0700
Subject: [PATCH] serial_core: add pci uart early console support
On some Intel Atom SoCs, the legacy IO port UART(0x3F8) is not available.
Instead, a 8250 compatible
>From 78ab0810176c544e2b6f14ca8b19c90d339fa6f1 Mon Sep 17 00:00:00 2001
From: Bin Gao
Date: Thu, 14 May 2015 15:49:58 -0700
Subject: [PATCH] arch/x86: remove pci uart early console from early_prink.c
The arch independent uart8250 early console driver has good
support for memory mapped and
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
drivers/tty/serial/earlycon.c| 6 ++
drivers/tty/serial/serial_core.c | 140 ++-
2 files changed, 144
x27;commit 5140fda16051 ("Specify PCI based UART for earlyprintk")'
is removed. And its equivalent function will be available from
uart8250 early console driver.
Signed-off-by: Bin Gao
---
arch/x86/kernel/early_printk.c | 180 -
1 file chang
the following line to the kernel command line
(assume baud rate is 115200):
earlyprintk=uart8250,pci32,0:24.2,115200n8
Signed-off-by: Bin Gao
---
arch/x86/Kconfig | 11 +++
drivers/tty/serial/earlycon.c| 9 +++
drivers/tty/serial/serial_core.c | 145
x27;commit 5140fda16051 ("Specify PCI based UART for earlyprintk")'
is removed. And its equivalent function will be available from
uart8250 early console driver.
Signed-off-by: Bin Gao
---
arch/x86/kernel/early_printk.c | 180 -
1 file chang
On Tue, May 19, 2015 at 02:01:07PM +0200, Paul Bolle wrote:
> On Mon, 2015-05-18 at 14:21 -0700, Bin Gao wrote:
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -2228,6 +2228,8 @@ config PCI
> > your box. Other bus systems are ISA, EISA, MicroChannel
>From 8977941ac3d70425fa7ca5ef3ab6de6c28743f1f Mon Sep 17 00:00:00 2001
From: Bin Gao
Date: Tue, 12 May 2015 16:40:27 -0700
Subject: [PATCH] serial_core: add pci uart early console support
On some Intel Atom SoCs, the legacy IO port UART(0x3F8) is not available.
Instead, a 8250 compatible
On Fri, Jul 15, 2016 at 08:31:08AM +0200, Oliver Neukum wrote:
> > +static void ack_message(struct pd_sink_port *port, int msg_id)
> > +{
> > + struct pd_msg_header *header = kzalloc(PD_MSG_HEADER_LEN, GFP_KERNEL);
>
> This must be GFP_NOIO. We are in a cycle that can lead to deadlock.
>
> Assu
On Fri, Jul 15, 2016 at 02:21:48PM +0300, Felipe Balbi wrote:
> Greg Kroah-Hartman writes:
> > On Fri, Jul 15, 2016 at 01:38:12PM +0300, Felipe Balbi wrote:
> >>
> >> Hi,
> >>
> >> Bin Gao writes:
> >> > +static voi
On Fri, Jul 15, 2016 at 10:25:36AM +0300, Felipe Balbi wrote:
> Bin Gao writes:
>
> > This patch implements a simple USB Power Delivery sink port state machine.
> > It assumes the hardware only handles PD packet transmitting and receiving
> > over the CC line of the U
On Sat, Jul 16, 2016 at 08:49:53AM +0900, Greg Kroah-Hartman wrote:
> On Fri, Jul 15, 2016 at 03:41:10PM -0700, Bin Gao wrote:
> > On Fri, Jul 15, 2016 at 02:21:48PM +0300, Felipe Balbi wrote:
> > > Greg Kroah-Hartman writes:
> > > > On Fri, Jul 15, 2016 at 01:38:
On Mon, Jul 18, 2016 at 10:07:24AM +0300, Felipe Balbi wrote:
>
> Hi,
>
> Bin Gao writes:
> >> > +int pd_sink_queue_msg(struct pd_sink_msg *msg)
> >> > +{
> >> > +unsigned long flags;
> >> > +struct pd_sink_port *p
: struct trip_config_map{},
struct thermal_irq_map {} and struct pmic_thermal_data {} which are
required by changes we did on intel_soc_pmic_bxtwc.c.
Signed-off-by: Yegnesh S Iyer
Signed-off-by: Rohit S Kenchanpura
Signed-off-by: Bin Gao
---
Changes in v3:
- Added USB type-C resources.
Changes in v2
This series modifies the pen function signature to take bit field
and adds a new opregion driver for Intel BXT WhiskeyCove PMIC. It
also adds support for PMIC regs operation region.
Yegnesh Iyer (1):
acpi: pmic: Modifying the pen function signature to take bit field
Ajay Thomas (1):
acpi: pmi
first approach.
Solution: Modified the policy enable function to take bit field as well.
The use of bit field is left to the pmic specific opregion driver.
Signed-off-by: Yegnesh Iyer
Signed-off-by: Bin Gao
---
Changes in v3: no change
Changes in v2:
- Fixed subject line.
drivers/acpi/pmic
This patch adds operation region driver for Intel BXT WhiskeyCove
PMIC. The register mapping is done as per the BXT WC data sheet.
Signed-off-by: Ajay Thomas
Signed-off-by: Felipe Balbi
Signed-off-by: Chandra Sekhar Anagani
Signed-off-by: Bin Gao
---
Changes in v3:
- Added regs_read() and
.
Signed-off-by: Chandra Sekhar Anagani
Signed-off-by: Felipe Balbi
Signed-off-by: Bin Gao
---
Changes in v3: none
Changes in v2: none
drivers/acpi/pmic/intel_pmic.c | 74 +-
drivers/acpi/pmic/intel_pmic.h | 5 +++
2 files changed, 71 insertions(+), 8
> Well, I'm dropping the old series due to comments from Aaron on the
> second patch.
>
> I will be waiting for an update addressing the Aaron's comments in
> [2/3] and [3/3].
Right, there was no change on [1/3].
I'll address Aaron's comments and re-send all as v4. Thanks.
-Bin
This series modifies the pen function signature to take bit field
and adds a new opregion driver for Intel BXT WhiskeyCove PMIC. It
also adds support for PMIC regs operation region.
Yegnesh Iyer (1):
acpi: pmic: Modifying the pen function signature to take bit field
Ajay Thomas (1):
acpi: pmi
first approach.
Solution: Modified the policy enable function to take bit field as well.
The use of bit field is left to the pmic specific opregion driver.
Signed-off-by: Yegnesh Iyer
Signed-off-by: Bin Gao
---
Changes in v4: none
Changes in v3: none
Changes in v2:
- Fixed subject line.
drivers
This patch adds operation region driver for Intel BXT WhiskeyCove
PMIC. The register mapping is done as per the BXT WC data sheet.
Signed-off-by: Ajay Thomas
Signed-off-by: Bin Gao
---
Changes in v4:
- Reverted(removed) regs_read() and regs_write() methods
Changes in v3:
- Added regs_read
and write.
Signed-off-by: Felipe Balbi
Signed-off-by: Chandra Sekhar Anagani
Signed-off-by: Bin Gao
---
Changes in v4:
- various fixes to address Aaron's comments.
Changes in v3: none
Changes in v2: none
drivers/acpi/pmic/intel_pmic.c | 74 --
dr
On Wed, Jul 06, 2016 at 10:57:19AM +0200, Linus Walleij wrote:
> > +static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
> > +{
> > + int pending;
> > + unsigned int p0, p1, virq, gpio;
> > + struct wcove_gpio *wg = data;
> > +
> > + if (regmap_read(wg->regmap, IRQ
On Wed, Jul 06, 2016 at 01:07:15PM +0300, Mika Westerberg wrote:
> On Wed, Jul 06, 2016 at 10:57:19AM +0200, Linus Walleij wrote:
> > On Tue, Jun 28, 2016 at 1:56 AM, Bin Gao wrote:
> >
> > > This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC.
>
On Tue, Jun 14, 2016 at 01:09:31PM +0300, Mika Westerberg wrote:
> On Fri, Jun 10, 2016 at 11:01:51PM -0700, Bin Gao wrote:
> > +static const struct platform_device_id pmic_gpio_id_table[] = {
> > + { "bxt_wcove_gpio", },
> > +};
>
> Do you really n
This series introduce a USB PD(Power Delivery) sink port simple state
machine driver and adds USB PD sink port support for Intel BXT Whiskey
Cove PMIC Type-C phy driver.
This series depends on these two patches:
https://lkml.org/lkml/2016/6/29/349
https://lkml.org/lkml/2016/6/29/350
Bin Gao (1
function and it doesn't support source port and port swap yet.
This patch depends on these two patches:
https://lkml.org/lkml/2016/6/29/349
https://lkml.org/lkml/2016/6/29/350
Signed-off-by: Bin Gao
---
drivers/usb/typec/Kconfig | 13 +
drivers/usb/typec/Makefile | 1 +
drivers/usb/
From: Chandra Sekhar Anagani
This adds PD sink port support for the USB Type-C PHY on Intel WhiskeyCove
PMIC which is available on some of the Intel Broxton SoC based platforms.
This patch depends on these two patches:
https://lkml.org/lkml/2016/6/29/349
https://lkml.org/lkml/2016/6/29/350
Sign
This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC.
This driver is based on gpio-crystalcove.c.
Signed-off-by: Ajay Thomas
Signed-off-by: Bin Gao
Reviewed-by: Andy Shevchenko
Reviewed-by: Mika Westerberg
---
Changes in v7:
- Fixed various coding style comments from Andy
This series introduce a USB PD(Power Delivery) sink port simple state
machine driver and adds USB PD sink port support for Intel BXT Whiskey
Cove PMIC Type-C phy driver.
This series depends on these two patches:
https://lkml.org/lkml/2016/6/29/349
https://lkml.org/lkml/2016/6/29/350
Bin Gao (1
function and it doesn't support source port and port swap yet.
This patch depends on these two patches:
https://lkml.org/lkml/2016/6/29/349
https://lkml.org/lkml/2016/6/29/350
Signed-off-by: Bin Gao
Changes in v2:
- Removed work queue so messages are directly handled in phy driver's
Signed-off-by: Chandra Sekhar Anagani
Signed-off-by: Pranav Tipnis
Signed-off-by: Bin Gao
Changes in v2:
- Added PD support for cold boot case
---
drivers/usb/typec/typec_wcove.c | 309
1 file changed, 285 insertions(+), 24 deletions(-)
diff --git a
On Fri, Aug 26, 2016 at 12:14:58PM +0200, Thomas Gleixner wrote:
> On Fri, 26 Aug 2016, Thomas Gleixner wrote:
> > On Thu, 25 Aug 2016, Bin Gao wrote:
> > > On Wed, Aug 24, 2016 at 10:51:20AM +0200, Thomas Gleixner wrote:
> > > > On Tue, 16 Aug 2016, Bin Gao wrote:
This patch series adds X86_FEATURE_TSC_KNOWN_FREQ flag and modifies
Intel Atom SoC related TSC codes to use the new TSC_KNOWN_FREQ flag
and the existed TSC_RELIABLE flag.
Bin Gao (4):
x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
x86/tsc: mark TSC frequency determined by CPUID as known
x86
This
makes us believe that we should prefer CPUID determined frequency over
software calibrated frequency.
Signed-off-by: Bin Gao
---
arch/x86/kernel/tsc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 3ba146e..f1a7fb5 100644
---
e set both X86_FEATURE_TSC_KNOWN_FREQ and
X86_FEATURE_TSC_RELIABLE flags to make sure the calibration is
skipped and no watchdog on TSC.
Signed-off-by: Bin Gao
---
arch/x86/kernel/tsc_msr.c | 18 ++
arch/x86/platform/intel-mid/mfld.c | 9 +++--
arch/x86/platform/intel-mid/mr
On Intel GOLDMONT Atom SoC TSC is the only reliable clocksource.
We mark TSC reliable to avoid watchdog on it.
Signed-off-by: Bin Gao
---
arch/x86/kernel/tsc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index f1a7fb5..354b302 100644
alibration is skipped.
Signed-off-by: Bin Gao
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/tsc.c | 11 ---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index a39629
> > --- a/arch/x86/kernel/tsc.c
> > +++ b/arch/x86/kernel/tsc.c
> > @@ -1283,10 +1283,10 @@ static int __init init_tsc_clocksource(void)
> > clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
> >
> > /*
> > -* Trust the results of the earlier calibration on systems
> > -
> > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > }
> > }
> >
> > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
>
> I can understand the one below, but this one changes existing behaviour w/o
> explaining why this is correct and desired. If at all then
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