On 2018-01-17 02:28, Suzuki K Poulose wrote:
On 17/01/18 03:34, ckad...@codeaurora.org wrote:
On 2018-01-16 02:23, Suzuki K Poulose wrote:
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table
On 2018-02-01 02:44, Mark Rutland wrote:
On Thu, Jan 25, 2018 at 03:55:12PM -0800, Channagoud Kadabi wrote:
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi
---
On 2018-02-01 02:48, Mark Rutland wrote:
On Thu, Jan 25, 2018 at 03:55:12PM -0800, Channagoud Kadabi wrote:
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi
---
On 2018-02-08 08:52, Matt Sealey wrote:
Hiya,
On 25 January 2018 at 17:55, Channagoud Kadabi
wrote:
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
[snippety snip]
+- llcc-bank-off:
+ Usage: required
+
On 2018-02-02 03:05, Mark Rutland wrote:
On Thu, Feb 01, 2018 at 12:39:09PM -0800, Channa wrote:
On 2018-02-01 02:44, Mark Rutland wrote:
> On Thu, Jan 25, 2018 at 03:55:12PM -0800, Channagoud Kadabi wrote:
> > Documentation for last level cache controller device tree bindings,
&
On 2018-02-13 06:37, Mark Rutland wrote:
On Tue, Feb 06, 2018 at 11:56:50AM -0800, Channa wrote:
On 2018-02-02 03:05, Mark Rutland wrote:
> On Thu, Feb 01, 2018 at 12:39:09PM -0800, Channa wrote:
> > On 2018-02-01 02:44, Mark Rutland wrote:
> > > On Thu, Jan 25, 2018 a
On 2018-04-18 07:52, Rob Herring wrote:
On Tue, Apr 17, 2018 at 5:12 PM, wrote:
On 2018-04-17 10:43, risha...@codeaurora.org wrote:
On 2018-04-16 07:59, Rob Herring wrote:
On Tue, Apr 10, 2018 at 01:08:12PM -0700, Rishabh Bhatnagar wrote:
Documentation for last
On 2018-04-18 11:11, Channa wrote:
On 2018-04-18 07:52, Rob Herring wrote:
On Tue, Apr 17, 2018 at 5:12 PM, <risha...@codeaurora.org> wrote:
On 2018-04-17 10:43, risha...@codeaurora.org wrote:
On 2018-04-16 07:59, Rob Herring wrote:
On Tue, Apr 10, 2018 at 01:08:12PM -0700, R
On 2018-03-29 01:08, Stanimir Varbanov wrote:
Hi,
On 03/27/2018 09:52 PM, Rishabh Bhatnagar wrote:
LLCC (Last Level Cache Controller) provides additional cache memory
in the system. LLCC is partitioned into muliple slices and each
slice getting its own priority, size, ID and other config
On 2018-04-02 02:11, Stanimir Varbanov wrote:
Hi,
Please adjust your mail client to drop on new line on 80 column!
On 03/29/2018 08:55 PM, Channa wrote:
On 2018-03-29 01:08, Stanimir Varbanov wrote:
Hi,
On 03/27/2018 09:52 PM, Rishabh Bhatnagar wrote:
LLCC (Last Level Cache Controller
On 2018-03-19 07:55, Jordan Crouse wrote:
On Thu, Jan 25, 2018 at 03:55:13PM -0800, Channagoud Kadabi wrote:
LLCC (Last Level Cache Controller) provides additional cache memory
in the system. LLCC is partitioned into muliple slices and each
slice gets its own priority, size, ID and other config
On 2018-03-19 07:55, Jordan Crouse wrote:
On Thu, Jan 25, 2018 at 03:55:13PM -0800, Channagoud Kadabi wrote:
LLCC (Last Level Cache Controller) provides additional cache memory
in the system. LLCC is partitioned into muliple slices and each
slice gets its own priority, size, ID and other config
On 2018-03-29 01:08, Stanimir Varbanov wrote:
Hi,
On 03/27/2018 09:52 PM, Rishabh Bhatnagar wrote:
LLCC (Last Level Cache Controller) provides additional cache memory
in the system. LLCC is partitioned into muliple slices and each
slice getting its own priority, size, ID and other config
On 2018-04-18 11:11, Channa wrote:
On 2018-04-18 07:52, Rob Herring wrote:
On Tue, Apr 17, 2018 at 5:12 PM, wrote:
On 2018-04-17 10:43, risha...@codeaurora.org wrote:
On 2018-04-16 07:59, Rob Herring wrote:
On Tue, Apr 10, 2018 at 01:08:12PM -0700, Rishabh Bhatnagar wrote
On 2018-04-02 02:11, Stanimir Varbanov wrote:
Hi,
Please adjust your mail client to drop on new line on 80 column!
On 03/29/2018 08:55 PM, Channa wrote:
On 2018-03-29 01:08, Stanimir Varbanov wrote:
Hi,
On 03/27/2018 09:52 PM, Rishabh Bhatnagar wrote:
LLCC (Last Level Cache Controller
On 2018-04-18 07:52, Rob Herring wrote:
On Tue, Apr 17, 2018 at 5:12 PM, wrote:
On 2018-04-17 10:43, risha...@codeaurora.org wrote:
On 2018-04-16 07:59, Rob Herring wrote:
On Tue, Apr 10, 2018 at 01:08:12PM -0700, Rishabh Bhatnagar wrote:
Documentation for last level cache controller
On 2018-02-01 02:44, Mark Rutland wrote:
On Thu, Jan 25, 2018 at 03:55:12PM -0800, Channagoud Kadabi wrote:
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt
On 2018-02-01 02:48, Mark Rutland wrote:
On Thu, Jan 25, 2018 at 03:55:12PM -0800, Channagoud Kadabi wrote:
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt
On 2018-02-13 06:37, Mark Rutland wrote:
On Tue, Feb 06, 2018 at 11:56:50AM -0800, Channa wrote:
On 2018-02-02 03:05, Mark Rutland wrote:
> On Thu, Feb 01, 2018 at 12:39:09PM -0800, Channa wrote:
> > On 2018-02-01 02:44, Mark Rutland wrote:
> > > On Thu, Jan 25, 2018 a
On 2018-02-02 03:05, Mark Rutland wrote:
On Thu, Feb 01, 2018 at 12:39:09PM -0800, Channa wrote:
On 2018-02-01 02:44, Mark Rutland wrote:
> On Thu, Jan 25, 2018 at 03:55:12PM -0800, Channagoud Kadabi wrote:
> > Documentation for last level cache controller device tree bindings,
&
On 2018-02-08 08:52, Matt Sealey wrote:
Hiya,
On 25 January 2018 at 17:55, Channagoud Kadabi
wrote:
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
[snippety snip]
+- llcc-bank-off:
+ Usage: required
+ Value Type:
+
On 2018-01-17 02:28, Suzuki K Poulose wrote:
On 17/01/18 03:34, ckad...@codeaurora.org wrote:
On 2018-01-16 02:23, Suzuki K Poulose wrote:
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table
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