[PATCH] dtc: Use quotes to include header files

2014-12-15 Thread Chris Packham
the source directory without needing to add CFLAGS for the sources that happen to include linux/libfdt.h. Signed-off-by: Chris Packham chris.pack...@alliedtelesis.co.nz --- Hi, This probably should come via git://git.jdl.com/software/dtc.git however this appears to be inaccessible at the moment

Re: [PATCH] dtc: Use quotes to include header files

2015-01-30 Thread Chris Packham
On Thu, 29 Jan 2015, Grant Likely wrote: On Tue, 16 Dec 2014 15:13:24 +1300 , Chris Packham chris.pack...@alliedtelesis.co.nz wrote: Currently in arch and driver code that needs early access to the flattened device tree it is necessary to add specific CFLAGS so that when scripts/dtc/libfdt

Re: [PATCH net-next 0/3] net: Switch tag HW extraction/insertion

2015-07-30 Thread Chris Packham
Hi Florian, On 07/31/2015 01:51 PM, Florian Fainelli wrote: On 30/07/15 15:51, David Miller wrote: From: David Miller da...@davemloft.net Date: Thu, 30 Jul 2015 14:19:35 -0700 (PDT) This looks fine, series applied, thanks. I think your control block is too large, you'll need to rework this

[RFC PATCH v1] mips: Use unsigned int when reading CP0 registers

2015-07-14 Thread Chris Packham
as per the CPU datasheet. Signed-off-by: Chris Packham judge.pack...@gmail.com --- This has come up via u-boot[1] which sync's asm/mipsregs.h with the kernel. In u-boots case the value read from read_c0_count() is assigned to an unsigned long [2] which triggers a sign extension and causes a bug. U

[PATCH] net: vrf: replace hard tab with space in assignment

2016-06-20 Thread Chris Packham
The assignment of rth->dst.output in vrf_rt6_create() and vrf_rtable_create() used a hard tab before the '='. The neighboring assignments did not. Make the assignment of rth->dst.output consistent with the surrounding code. Signed-off-by: Chris Packham <chris.pack...@alliedtele

[RFC PATCH v1] pinctrl: mvebu: add 98dx1135-pinctrl

2016-01-27 Thread Chris Packham
The Marvell 98DX1135 is a switch chip with an integrated CPU, similar to the MV98DX4122. From a pinctrl point of view the only difference is that NF_REN, NF_WEN, NF_ALE and NF_CEN lines are MPP pins instead of dedicated ones. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co

[PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support

2017-02-01 Thread Chris Packham
The l2-cache controller on the T2080 SoC has similar capabilities to the others already supported by the mpc85xx_edac driver. Add it to the list of compatible devices. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Johannes Thumshirn <j...@k

Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support

2017-02-01 Thread Chris Packham
On 02/02/17 12:28, Borislav Petkov wrote: > On Thu, Feb 02, 2017 at 12:16:24PM +1300, Chris Packham wrote: >> The l2-cache controller on the T2080 SoC has similar capabilities to the >> others already supported by the mpc85xx_edac driver. Add it to the list >> of compatible

Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support

2017-02-02 Thread Chris Packham
On 03/02/17 12:55, Michael Ellerman wrote: > Chris if you want to send a patch to add the compatible string to the > l2cache.txt I would merge that, but honestly it doesn't achieve much > other than possibly catching a typo in the compatible name. I think catching a typo might be worthwhile. It's

[PATCH 1/4] ARM: dts: armada-xp-98dx3236: combine dfx server nodes

2017-02-02 Thread Chris Packham
Rather than having a separate node for the dfx server add a reg property to the parent node. This give somes compatibility with the Marvell supplied SDK. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Documentation/devicetree/bindings/net/marvell,prestera.tx

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-02 Thread Chris Packham
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. Port code from the Marvell supplied Linux kernel to support different PLL frequencies and provide clock gating support. Signed-off-by: Chr

[PATCH 0/4] Updates for Marvell Switch SoCs

2017-02-02 Thread Chris Packham
don't have to disable nodes for blocks that only exist on the Armada-XP. Patch 3/4 and 4/4 are ported from the Marvell Linux kernel. I've tested them on the hardware I have access to and things look pretty good. Chris Packham (4): ARM: dts: armada-xp-98dx3236: combine dfx server nodes ARM: dts

[PATCH 3/4] ARM: mvebu: Add mv98dx3236-soc-id

2017-02-02 Thread Chris Packham
The DFX server on the 98dx3236 and compatible SoCs has an ID register that provides revision information that the PCI based ID register doesn't have. Use this if it's available. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- .../bindings/arm/marvell/mv98dx3236-soc-

[PATCH 2/4] ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236

2017-02-02 Thread Chris Packham
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In reality there are a number of differences to the actual Armada-XP so rather than including armada-xp.dtsi and disabling many of the IP blocks. Include armada-370-xp.dtsi and add the required nodes. Signed-off-by: Chr

[PATCH] ARM: dts: armada-38x add node labels

2017-02-01 Thread Chris Packham
As was done with Armada XP, add node labels to Armada 38x common and SoC specific nodes to make them easier to reference in board device trees. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- arch/arm/boot/dts/armada-385.dtsi | 20 +--- arch/arm/bo

Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-06 Thread Chris Packham
On 07/02/17 14:13, Chris Packham wrote: > On 07/02/17 14:03, Stephen Boyd wrote: >> On 02/06, Chris Packham wrote: >>> On 07/02/17 12:14, Stephen Boyd wrote: >>>> On 02/03, Chris Packham wrote: >>>>> The initial implementation in commit e120c17a70e5

Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-06 Thread Chris Packham
On 07/02/17 14:03, Stephen Boyd wrote: > On 02/06, Chris Packham wrote: >> On 07/02/17 12:14, Stephen Boyd wrote: >>> On 02/03, Chris Packham wrote: >>>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support >>>> for 98DX3236

Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-06 Thread Chris Packham
On 07/02/17 14:25, Chris Packham wrote: > On 07/02/17 14:13, Chris Packham wrote: >> On 07/02/17 14:03, Stephen Boyd wrote: >>> On 02/06, Chris Packham wrote: >>>> On 07/02/17 12:14, Stephen Boyd wrote: >>>>> On 02/03, Chris Packham wrote: >>>

Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-06 Thread Chris Packham
On 07/02/17 12:14, Stephen Boyd wrote: > On 02/03, Chris Packham wrote: >> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support >> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. >> Port code from the Marvell supplied Li

[PATCH v2 0/6] Updates for Marvell Switch SoCs

2017-02-07 Thread Chris Packham
need to use the coreclk label on a different node. It also means I don't have to disable nodes for blocks that only exist on the Armada-XP. Patch 4/6, 5/6 and 6/6 are ported from the Marvell Linux kernel. I've tested them on the hardware I have access to and things look pretty good. Chris Packham (6

[PATCH v2 3/6] ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236

2017-02-07 Thread Chris Packham
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In reality there are a number of differences to the actual Armada-XP so rather than including armada-xp.dtsi and disabling many of the IP blocks. Include armada-370-xp.dtsi and add the required nodes. Signed-off-by: Chr

[PATCH v2 5/6] ARM: dts: mvebu: Move mv98dx3236 clock bindings

2017-02-07 Thread Chris Packham
This moves the coreclk binding for the 98dx3236 SoC to the DFX block where the sampled at reset register is located and switches to using the correct gating clock compatible string. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2: - New.

[PATCH v2 6/6] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-07 Thread Chris Packham
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. Port code from the Marvell supplied Linux kernel to support different PLL frequencies and provide clock gating support. Signed-off-by: Chr

[PATCH v2 2/6] ARM: dts: armada-xp-98dx3236: combine dfx server nodes

2017-02-07 Thread Chris Packham
Rather than having a separate node for the dfx server add a reg property to the parent node. This give somes compatibility with the Marvell supplied SDK. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2: - none Documentation/devicetree/bi

[PATCH v2 1/6] ARM: dts: Fix typo in armada-xp-98dx4251

2017-02-07 Thread Chris Packham
The compatible should be 98dx4251 not 98dx4521. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2 - new arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/arm

[PATCH v2 4/6] ARM: mvebu: Add mv98dx3236-soc-id

2017-02-07 Thread Chris Packham
The DFX server on the 98dx3236 and compatible SoCs has an ID register that provides revision information that the PCI based ID register doesn't have. Use this if it's available. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2:

Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

2017-02-08 Thread Chris Packham
On 08/02/17 23:53, Arnd Bergmann wrote: > On Tuesday, February 7, 2017 3:07:37 AM CET Chris Packham wrote: >>> >>> Actually I wonder if I can try a bit harder to keep a system booting. >>> The following might work >>> 1) add the compatible strings to t

[PATCH] Documentation: powerpc/fsl: Update compatible for l2cache binding

2017-02-02 Thread Chris Packham
List all the current valid compatible strings for the l2cache binding. This should stop checkpatch.pl from complaining and will hopefully save someone from having to debug a typo in their dts. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- .../devicetree/bindings/p

Re: [PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-22 Thread Chris Packham
On 21/01/17 13:48, Stephen Boyd wrote: > On 01/13, Chris Packham wrote: >> @@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = { >> .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), >> }; >> >> +static const struct cor

Re: [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-23 Thread Chris Packham
On 20/01/17 10:10, Chris Packham wrote: > On 19/01/17 23:03, Russell King - ARM Linux wrote: >> On Fri, Jan 13, 2017 at 10:12:18PM +1300, Chris Packham wrote: >>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = { >>> + MPP_FUNC_CTRL(0, 3

Re: [PATCHv3 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-26 Thread Chris Packham
On 27/01/17 04:10, Gregory CLEMENT wrote: > Hi Chris, > > On ven., janv. 06 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz> > wrote: > >> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs >> with integrated CPUs. They are simil

Re: [PATCHv3 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-26 Thread Chris Packham
On 27/01/17 04:10, Gregory CLEMENT wrote: >> +internal-regs { [snip] >> + >> +dfx-registers { > node label > [snip] >> +switch { > node label > These are peers to the internal-regs, i.e. parts of the SoC with mappable windows in the address space. Do they

[PATCHv5 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-26 Thread Chris Packham
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs with integrated CPUs. They are similar to the Armada XP SoCs but have different I/O interfaces. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Rob Herring <r...@kernel.org> --- Notes:

[PATCHv5 0/5] Support for Marvell switches with integrated CPUs

2017-01-26 Thread Chris Packham
package as the switch. I've rebased this series against linux-pinctrl/devel to get access to mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to v4.10.0-rc5. Chris Packham (4): clk: mvebu: support for 98DX3236 SoC Changes in v2: - Update devicetree binding documentation for new

[PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-26 Thread Chris Packham
tree if it is set in the machine definition. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Rob Herring <r...@kernel.org> --- Notes: Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 C

[PATCHv5 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards

2017-01-26 Thread Chris Packham
These boards are Marvell's evaluation boards for the 98DX4251 and 98DX3336 SoCs. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v5: - update license text - use node labels arch/arm/boot/dts/db-dxbc2.dts

[PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-26 Thread Chris Packham
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris

[PATCHv5 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-26 Thread Chris Packham
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz

Re: [PATCH v6 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards

2017-01-30 Thread Chris Packham
Hi Gregory, On 31/01/17 03:29, Gregory CLEMENT wrote: > Hi Chris, > > On lun., janv. 30 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz> > wrote: > >> These boards are Marvell's evaluation boards for the 98DX4251 and >> 98DX3336 SoCs. >> >

Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs

2017-01-30 Thread Chris Packham
On 31/01/17 03:40, Gregory CLEMENT wrote: > Hi Chris, > > The 5 patches should be available soon (if it is not already the case), > in the linux-next branch. > > The clk patch is already there, the 3 arm patch have been merged in my > mvebu/for-next branch, and the pinctrl patch is about to be

[PATCH] arm: mvebu: Fix whitespace in armada-xp-98dx3236.dtsi

2017-01-30 Thread Chris Packham
Change sequences of 8 spaces to hard-tabs. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- I think this crept in during review and I didn't notice. The file is new enough that we shouldn't lose any useful history. arch/arm/boot/dts/armada-xp-98dx3236.dts

Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs

2017-01-29 Thread Chris Packham
On 28/01/17 07:47, Stephen Boyd wrote: > On 01/27, Gregory CLEMENT wrote: >> Hi all, >> >> On ven., janv. 27 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz> >> wrote: >> >>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs wi

[PATCHv5 0/5] Support for Marvell switches with integrated CPUs

2017-01-29 Thread Chris Packham
package as the switch. I've rebased this series against linux-pinctrl/devel to get access to mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to v4.10.0-rc5. Chris Packham (4): clk: mvebu: support for 98DX3236 SoC Changes in v2: - Update devicetree binding documentation for new

[PATCH v6 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-29 Thread Chris Packham
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs with integrated CPUs. They are similar to the Armada XP SoCs but have different I/O interfaces. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Rob Herring <r...@kernel.org> --- Notes:

[PATCH v6 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-29 Thread Chris Packham
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris

[PATCH v6 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-29 Thread Chris Packham
tree if it is set in the machine definition. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Rob Herring <r...@kernel.org> --- Notes: Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 C

[PATCH v6 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-29 Thread Chris Packham
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz

[PATCH v6 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards

2017-01-29 Thread Chris Packham
These boards are Marvell's evaluation boards for the 98DX4251 and 98DX3336 SoCs. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v5: - update license text - use node labels Changes in v6: - Rename dts files to include 'armada-xp-'

Re: [PATCHv3 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-26 Thread Chris Packham
On 27/01/17 09:24, Chris Packham wrote: > On 27/01/17 04:10, Gregory CLEMENT wrote: >>> + internal-regs { > > [snip] > >>> + >>> + dfx-registers { >> node label >> > > [snip] > >>> + switch {

[PATCH] docs: hwmon: Fix typo "Microship" should be "Microchip"

2017-02-21 Thread Chris Packham
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Documentation/hwmon/tc654 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/hwmon/tc654 b/Documentation/hwmon/tc654 index 91a2843f5f98..47636a8077b4 100644 --- a/Documentation/hwmon/tc654

Re: [PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

2017-02-20 Thread Chris Packham
On 18/02/17 05:17, Arnd Bergmann wrote: > On Fri, Feb 17, 2017 at 5:22 AM, Chris Packham > <chris.pack...@alliedtelesis.co.nz> wrote: >> Hi Arnd, >> On 17/02/17 02:28, Arnd Bergmann wrote: >>> On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote: &g

[PATCH v3 2/6] ARM: dts: armada-xp-98dx3236: combine dfx server nodes

2017-02-16 Thread Chris Packham
to retain a backwards compatible binding. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2: - none Changes in v3: - update commit message to indicate backwards incompatible change and why it's OK - retain dfx-server compatible

[PATCH v3 1/6] ARM: dts: Fix typo in armada-xp-98dx4251

2017-02-16 Thread Chris Packham
The compatible should be 98dx4251 not 98dx4521. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2: - new Changes in v3: - none arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

2017-02-16 Thread Chris Packham
The DFX server on the 98dx3236 and compatible SoCs has an ID register that provides revision information that the PCI based ID register doesn't have. Use this if it's available. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2: - none C

[PATCH v3 6/6] ARM: dts: mvebu: Move mv98dx3236 clock bindings

2017-02-16 Thread Chris Packham
to the DFX block enables support for different clock strapping options in hardware. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v2: - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support" Changes in v3:

[PATCH v2 0/6] Updates for Marvell Switch SoCs

2017-02-16 Thread Chris Packham
need to use the coreclk label on a different node. It also means I don't have to disable nodes for blocks that only exist on the Armada-XP. Patch 4/6, 5/6 are split from the previous versions. Patch 6/6 is the device tree portion of a change already in clk-next. Chris Packham (6): ARM: dts: Fix

[PATCH v3 3/6] ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236

2017-02-16 Thread Chris Packham
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In reality there are a number of differences to the actual Armada-XP so rather than including armada-xp.dtsi and disabling many of the IP blocks. Include armada-370-xp.dtsi and add the required nodes. Signed-off-by: Chr

[PATCH v3 4/6] ARM: dts: mvebu: Add binding for mv98dx3236-soc-id

2017-02-16 Thread Chris Packham
The DFX server on the 98dx3236 and compatible SoCs has an ID register. Add documentation and a binding for this. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Notes: Changes in v3: - new, split from driver .../devicetree/bindings/arm/marvell/mv98dx3236-soc-

Re: [PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

2017-02-16 Thread Chris Packham
Hi Arnd, On 17/02/17 02:28, Arnd Bergmann wrote: > On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote: >> The DFX server on the 98dx3236 and compatible SoCs has an ID register >> that provides revision information that the PCI based ID register >> doesn't h

Re: [PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-18 Thread Chris Packham
On 19/01/17 11:25, Rob Herring wrote: > On Fri, Jan 13, 2017 at 10:12:16PM +1300, Chris Packham wrote: >> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from >> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. >> >> The clock

Re: [PATCHv4 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-18 Thread Chris Packham
On 19/01/17 13:48, Stephen Boyd wrote: > On 01/13, Chris Packham wrote: >> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c >> index 46c742d3bd41..59be3ca0464f 100644 >> --- a/arch/arm/mach-mvebu/platsmp.c >> +++ b/arch/arm/mach-mvebu/pla

Re: [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-19 Thread Chris Packham
On 19/01/17 23:03, Russell King - ARM Linux wrote: > On Fri, Jan 13, 2017 at 10:12:18PM +1300, Chris Packham wrote: >> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = { >> +MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl), >> +}; > > As Linus has ta

Re: [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-19 Thread Chris Packham
On 14/01/17 20:50, Chris Packham wrote: > On 13/01/17 22:54, Sebastian Hesselbarth wrote: >> On 13.01.2017 10:12, Chris Packham wrote: >>> From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> >>> >>> This pinctrl driver supports the 98DX3236, 9

Re: [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-19 Thread Chris Packham
On 20/01/17 12:19, Sebastian Hesselbarth wrote: > On 19.01.2017 22:12, Chris Packham wrote: >> On 14/01/17 20:50, Chris Packham wrote: >>> On 13/01/17 22:54, Sebastian Hesselbarth wrote: >>>> On 13.01.2017 10:12, Chris Packham wrote: >>>>> From: Kalyan

adm9240 error handling (was Re: [PATCHv1] hwmon: adm9240: handle temperature readings below 0)

2016-10-04 Thread Chris Packham
Hi Guenter, On 10/05/2016 11:10 AM, Guenter Roeck wrote: > On Tue, Oct 04, 2016 at 09:09:10PM +0000, Chris Packham wrote: >> >>> >>> Of course, all that doesn't solve the real problem in this driver, which is >>> that it ignores error codes from the smbus fun

[PATCHv2] hwmon: adm9240: handle temperature readings below 0

2016-10-04 Thread Chris Packham
of a signed 16-bit value. When presenting this in sysfs the value is shifted and scaled appropriately. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Changes in v2: - Simplify as per feedback from Guenter. - Re-word commit message. drivers/hwmon/adm9240.c | 4 ++-- 1 file c

Re: [PATCHv1] hwmon: adm9240: handle temperature readings below 0

2016-10-04 Thread Chris Packham
On 10/05/2016 09:54 AM, Guenter Roeck wrote: > On Tue, Oct 04, 2016 at 05:08:00PM +1300, Chris Packham wrote: >> Unlike the temperature thresholds the temperature data is a 9-bit signed >> value. This allows and additional 0.5 degrees of precision on the >> reading but means

[PATCHv1] hwmon: adm9240: handle temperature readings below 0

2016-10-03 Thread Chris Packham
Unlike the temperature thresholds the temperature data is a 9-bit signed value. This allows and additional 0.5 degrees of precision on the reading but means we can't rely on sign-extension to handle negative values. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- d

[PATCHv1] hwmon: Add tc654 driver

2016-10-06 Thread Chris Packham
Add support for the tc654 and tc655 fan controllers from Microchip. http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Hi Gunter, I realise this isn't using the new hwmon registration API. This is essen

[PATCHv2] hwmon: Add tc654 driver

2016-10-06 Thread Chris Packham
Add support for the tc654 and tc655 fan controllers from Microchip. http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Changes in v2: - Add Documentation/hwmon/tc654 - Incorporate most of the review comment

Re: [PATCHv1] hwmon: Add tc654 driver

2016-10-06 Thread Chris Packham
On 10/07/2016 11:57 AM, Guenter Roeck wrote: > On Fri, Oct 07, 2016 at 10:36:47AM +1300, Chris Packham wrote: >> Add support for the tc654 and tc655 fan controllers from Microchip. >> >> http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf >> >> Signed-

[PATCH] ARM: dts: armada-38x: Add NAND pinctrl information

2016-08-23 Thread Chris Packham
Add pin control information for the NAND flash interface. This interface is multiplexed with the device bus interface to the function is "dev" not "nand" as one might expect. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- arch/arm/boot/dts/armada

[PATCHv4] hwmon: Add tc654 driver

2016-10-10 Thread Chris Packham
Add support for the tc654 and tc655 fan controllers from Microchip. http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Changes in v4: - tab-align values in #defines - ensure locking in set_pwm covers updating

Re: [PATCHv3] hwmon: Add tc654 driver

2016-10-10 Thread Chris Packham
On 10/11/2016 02:22 AM, Guenter Roeck wrote: >> +if (val) >> > + data->config |= TC654_REG_CONFIG_DUTYC; >> > + else >> > + data->config &= ~TC654_REG_CONFIG_DUTYC; > I just realized that this won't work as intended. Problem is that you > only fill data->config when reading

[PATCH] ARM: mvebu: Update comment for main PLL frequency

2016-10-25 Thread Chris Packham
The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the comment was not updated. Update it now. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- arch/arm/boot/dts/armada-375.d

[PATCH] EDAC: mpc85xx: Add T2080 l2-cache support

2016-11-28 Thread Chris Packham
The l2-cache controller on the T2080 SoC has similar capabilities to the others already supported by the mpc85xx_edac driver. Add it to the list of compatible devices. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 1 + d

Re: [PATCHv4] hwmon: Add tc654 driver

2016-10-12 Thread Chris Packham
On 10/13/2016 02:03 AM, Guenter Roeck wrote: > On Tue, Oct 11, 2016 at 10:26:31AM +1300, Chris Packham wrote: >> > Add support for the tc654 and tc655 fan controllers from Microchip. >> > >> > http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf >>

Re: [PATCHv2] hwmon: Add tc654 driver

2016-10-09 Thread Chris Packham
Hi Gunter, Thanks for the review. v3 on it's way some responses below. On 10/08/2016 07:29 AM, Guenter Roeck wrote: > On Fri, Oct 07, 2016 at 02:38:44PM +1300, Chris Packham wrote: >> Add support for the tc654 and tc655 fan controllers from Microchip. >> >> http://ww1.micro

[PATCHv3] hwmon: Add tc654 driver

2016-10-09 Thread Chris Packham
Add support for the tc654 and tc655 fan controllers from Microchip. http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Changes in v3: - typofix in documentation - add missing value to tc654_pwm_map, re-generate

Re: [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-13 Thread Chris Packham
On 13/01/17 22:54, Sebastian Hesselbarth wrote: > On 13.01.2017 10:12, Chris Packham wrote: >> From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> >> >> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs >> from Marvell. >> >>

Re: [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-12 Thread Chris Packham
On 12/01/17 09:56, Sebastian Hesselbarth wrote: > On 01/11/2017 03:44 PM, Linus Walleij wrote: >> On Fri, Jan 6, 2017 at 5:15 AM, Chris Packham >> <chris.pack...@alliedtelesis.co.nz> wrote: >> >>> From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.n

[PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-13 Thread Chris Packham
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris

[PATCHv4 0/5] Support for Marvell switches with integrated CPUs

2017-01-13 Thread Chris Packham
package as the switch. This series is starting to settle down now. The only major change is in "arm: mvebu: support for SMP on 98DX3336 SoC" the other changes are generally cosmetic or collecting acks. Chris Packham (4): clk: mvebu: support for 98DX3236 SoC Changes in v2: - Update

[PATCHv4 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-13 Thread Chris Packham
tree if it is set in the machine definition. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Rob Herring <r...@kernel.org> --- Notes: Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 C

[PATCHv4 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards

2017-01-13 Thread Chris Packham
These boards are Marvell's evaluation boards for the 98DX4251 and 98DX3336 SoCs. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- arch/arm/boot/dts/db-dxbc2.dts | 159 arch/arm/boot/dts/db-xc3-24g4xg.dts

[PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-13 Thread Chris Packham
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz

[PATCHv4 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-13 Thread Chris Packham
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs with integrated CPUs. They are similar to the Armada XP SoCs but have different I/O interfaces. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> Acked-by: Rob Herring <r...@kernel.org> --- Notes:

Re: [PATCHv3 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-06 Thread Chris Packham
On 06/01/17 19:44, Stephen Boyd wrote: > On 01/06, Chris Packham wrote: >> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c >> index 46c742d3bd41..3c9ab9a008ad 100644 >> --- a/arch/arm/mach-mvebu/platsmp.c >> +++ b/arch/arm/mach-mvebu/pla

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

2017-01-05 Thread Chris Packham
On 06/01/17 02:10, Andrew Lunn wrote: >> I'd love to see a switchdev driver but it's a huge task (and no I'm not >> committing to writing it). As it stands Marvell ship a switch SDK >> largely executes in userspace with a small kernel module providing some >> linkage to the underlying hardware. >

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

2017-01-05 Thread Chris Packham
quot;, V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)), MPP_MODE(10, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), +MPP_VAR_FUNCTION(0x2, "sd0", "d3&quo

Re: [PATCHv2 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-05 Thread Chris Packham
On 05/01/17 17:46, Chris Packham wrote: > On 05/01/17 17:04, Florian Fainelli wrote: >> Le 01/04/17 à 19:36, Chris Packham a écrit : >>> +} >>> + >>> +static int __init mv98dx3236_resume_init(void) >>> +{ >>> + struct device_node

Re: [PATCHv2 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-05 Thread Chris Packham
On 06/01/17 02:59, Mark Rutland wrote: > On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote: >> +internal-regs { >> +coreclk: mvebu-sar@18230 { >> +compatible = "mar

Re: [PATCHv2 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-05 Thread Chris Packham
On 06/01/17 03:01, Mark Rutland wrote: > On Thu, Jan 05, 2017 at 04:36:37PM +1300, Chris Packham wrote: >> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from >> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. >> >&g

[PATCHv2 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-04 Thread Chris Packham
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>

[PATCHv2 1/5] clk: mvebu: support for 98DX3236 SoC

2017-01-04 Thread Chris Packham
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris

[PATCHv2 0/5] Support for Marvell switches with integrated CPUs

2017-01-04 Thread Chris Packham
package as the switch. Chris Packham (4): clk: mvebu: support for 98DX3236 SoC arm: mvebu: support for SMP on 98DX3336 SoC arm: mvebu: Add device tree for 98DX3236 SoCs arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards Kalyan Kinthada (1): pinctrl: mvebu: pinctrl driver

[PATCHv2 2/5] arm: mvebu: support for SMP on 98DX3336 SoC

2017-01-04 Thread Chris Packham
tree if it is set in the machine definition. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 Documentation/devicetree/bindings/arm/cpus.txt | 1 + .../bindings/arm/m

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

2017-01-04 Thread Chris Packham
On 05/01/17 17:07, Florian Fainelli wrote: > Le 01/04/17 à 19:36, Chris Packham a écrit : >> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with >> integrated CPUs. They CPU block is common within these product lines and >> (as far as I can tell/hav

[PATCHv2 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs

2017-01-04 Thread Chris Packham
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs with integrated CPUs. They are similar to the Armada XP SoCs but have different I/O interfaces. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Changes in v2: - Update devicetree binding documen

[PATCHv2 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards

2017-01-04 Thread Chris Packham
These boards are Marvell's evaluation boards for the 98DX4251 and 98DX3336 SoCs. Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> --- Chaqnges in v2: - None arch/arm/boot/dts/db-dxbc2.dts | 159 arch/arm/boot/dts/db-xc3-24g4xg.dts

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