's bump up to 4
(approx 90 degree phase?). If we need to configure this any further
(e.g., based on board or speed factors), we may need to consider a
device tree representation.
Suggested-by: Shawn Lin
Signed-off-by: Brian Norris
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abrah
nd will cause problems if picked without that change.
Signed-off-by: Douglas Anderson
Reviewed-by: Shawn Lin
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add collected tags
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 1
ck was set to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Rev
wn)
Brian Norris (2):
phy: rockchip-emmc: configure default output tap delay
phy: rockchip-emmc: reindent the register definitions
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes
Documentation: m
s the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson
Reviewed-by: Heiko Stuebner
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add dependency on COMMON_CLK (actually in v2.1) (Guenter Roeck)
- Add collected tags
Changes in v2: None
drivers/mmc/host/Kconfig
the idea
is the same.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v3:
- Add collected tags
Changes in v2:
- List out clocks and cloc
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add collected
r
SoCs. Note that a specific compatible string for rk3399 is already in
use and so we add that to the table to match rk3399.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
Reviewed-by: Heiko Stuebner
Reviewed-by: Shawn Lin
Tested-
s series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
---
Changes in v3:
- Use phy_init / phy_exit (Heiko)
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add collected tags
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399
There's no reason to store the return value of rockchip_emmc_phy_power()
in a variable nor to check it. Just return it.
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Reviewed-by: Shawn Lin
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add collected tags
Changes
From: Shawn Lin
Signal integrity analysis has suggested we set these values. Do this in
power_on(), so that they get reconfigured after suspend/resume.
Signed-off-by: Shawn Lin
Signed-off-by: Brian Norris
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Tested-by: Heiko
Norris
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add Brian's PHY patches into my series
Changes in v2: None
drivers/phy/phy-rockchip-emmc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/driver
xport the SDHCI card clock using a standard device tree mechanism
so that the PHY can get access to it and query the card clock frequency.
Signed-off-by: Douglas Anderson
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v3:
- Add collected tags
Changes in v2:
- Adjust commit me
From: Brian Norris
Some of the spacing was wrong (spaces instead of tabs), and due to
longer entries added later, the columns weren't aligned. Let's get
everything consistent.
Signed-off-by: Brian Norris
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Reviewed
et the corecfg also include a reference to the syscon.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
Reviewed-by: Shawn Lin
---
Changes in v3:
- Add collected tags
Changes in v2:
-
the device tree property
"settle-time-up-us" which allows us to specify a fixed delay after a
voltage increase.
We don't add an option of a fixed delay on the way down for now because
the way down is probably modelled best with a ramp rate, not a fixed
delay.
Signed-off-by: Matthias Ka
e() call
until we've finished delaying. A future patch atop this one might
choose to return more immediately and let the voltages fall in the
background. That would possibly to allow us to cancel a slow downward
decay if there was a request to go back up.
Signed-off-by: Douglas Anderson
---
On some rk3399 boards GPIO0_A0 is hooked up to a 32 kHz clock. This can
be used as the source for various clocks in the system.
Add a pinmux so boards can get this pin properly configured.
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++
1 file changed
t;clk: rockchip: fix incorrect
aclk_emmc source gate bits on rk3399"). Before that change we were
presumably not actually gating any of these clocks because we were
setting the wrong gate.
Signed-off-by: Xing Zheng
Signed-off-by: Douglas Anderson
---
drivers/clk/rockchip/clk-rk3399.c
These are a few stragglers that I left out of the original patch to
cache calls to the C compiler ("kbuild: Add a cache for generated
variables") because they bleed out into the main Makefile and thus
uglify things a little bit. The idea is the same here, though.
Signed-off-by: Dougla
ore doc changes
- Moved cache stuff below cc-cross-prefix
- Removed duplicate documentation of try-run (oops)
- Add Tested-by for Ingo and Guenter since v2 and v3 are very similar
Changes in v2:
- Abstract at a different level (like shell-cached) per Masahiro Yamada
- Include ld-version, which I missed
already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
NOTE: This change requires commit fa9acf703d64 ("kbuild: add forward
declaration of
rs we were storing data in.
Note that the saving code (and the comments talking about how
important it is to do the save) has been around since
commit 336cfbb05edf ("ASoC: Intel: mrfld- add ACPI module").
Signed-off-by: Douglas Anderson
---
This problem was found only by code inspection and
nefit of
avoiding an error path in the init code.
Note that the saving code that we're removing (and the comments
talking about how important it is to do the save) has been around
since commit 336cfbb05edf ("ASoC: Intel: mrfld- add ACPI module").
Signed-off-by: Douglas Anderson
---
igned-off-by: Douglas Anderson
---
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/hcd.c | 7
drivers/usb/dwc2/hcd.h | 9 +
drivers/usb/dwc2/hcd_intr.c | 12 +++
drivers/usb/dwc2/hcd_queue.c | 81 +---
5 files changed
igned-off-by: Douglas Anderson
Reviewed-by: Julius Werner
---
Changes in v2:
- Address http://crosreview.com/737520 feedback
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/hcd.c | 7
drivers/usb/dwc2/hcd.h | 9 +
drivers/usb/dwc2/hcd_intr.c | 20 +++
driver
Convert the timers in hcd_queue to use the new timer_setup() call
introduced in commit 686fef928bba ("timer: Prepare to change timer
callback argument type").
Suggested-by: Stefan Wahren
Signed-off-by: Douglas Anderson
Cc: Kees Cook
---
Changes in v3:
- Convert hcd_queue to timer
igned-off-by: Douglas Anderson
Cc: sta...@vger.kernel.org
Reviewed-by: Julius Werner
Tested-by: Stefan Wahren
---
Changes in v3:
- Add tested-by for Stefan Wahren
- Sent to Felipe Balbi as candiate to land this.
- Add Cc for stable (it's always been broken so go as far is as easy)
Cha
mes we
could avoid the reset, we remove "irq" and rename "select_phy" to
"initial_setup" and adjust the callers accordingly.
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/core.c | 29 ++---
drivers/usb/dwc2/core.h | 2 +-
drivers/usb/dwc2
v4.3-rc1) with a few linuxnext dwc2
patches pulled in to avoid conflicts.
These patches have either landed or are planned to land on the
chromeos-3.14 branch for use in several Chromebooks that use rk3288.
Douglas Anderson (3):
usb: dwc2: Restore GUSBCFG in dwc2_get_hwparams()
CHROMIUM: usb:
patch in my RK3288-evb board. It works well.
Signed-off-by: Yunzhi Li
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 27ade0c..59fe48f 100644
--- a
t way.
Since we're now looking at GUSBCFG, it's obvious that we shouldn't need
all the extra delays if FORCEHOSTMODE was already set. This will avoid
some delays for any ports that have forced host mode.
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/core.c | 16 +--
dwc2_core_reset() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().
Signed-off-by: Douglas A
registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/core.c | 2 +-
drivers/usb/dwc2/core.h
Though we could add specific code to handle this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/hcd_intr.c | 80 +++--
1 file changed, 70 insertio
Though we could add specific code to handle this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Add static as correctly pointed by kbuild test robot
drivers/usb/dwc2/hcd_intr.c | 80
>From code inspection, it appears to be unsafe to do a read-modify-write
of PCGCTL in dwc2_port_resume(). Let's make sure the spinlock is held
around this operation.
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/hcd.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
di
neral purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson
---
Changes in v3:
- Don't pass NULL if qtd freed, just return (John Youn)
- Don't keep track of interrupts left: list_first_entry() is fast.
Changes in v2:
- Add static
ct
5. dwc2_handle_common_intr() - calls dwc2_hcd_disconnect()
...but with different timing then sometimes we'd still miss cable
insertions.
In any case, though this patch doesn't fix any (known) problems, it
still seems wise as a general policy to clear interrupt before handling
them.
Signed-
connect interrupt and
re-connecting after the disconnect is posted. We don't skip the
disconnect because if there is a transitory disconnect we really want to
de-enumerate and re-enumerate.
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/core.h | 2 ++
dr
neral purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson
---
Changes in v4:
- Fix NULL qh case
Changes in v3:
- Don't pass NULL if qtd freed, just return (John Youn)
- Don't keep track of interrupts left: list_first_entry() is
peed
for i in $(seq 10); do
dd if=/dev/zero of=/dev/sdb bs=1M count=750
done
With the above tests I found that speeds went from ~15MB/s to ~18MB/s.
Note that most other tests I did (including reading from the same USB
reader) didn't show any difference in performance.
Signe
nly present (and
only transitioned in to and out of) when (optional) power management
is enabled.
Signed-off-by: Doug Anderson
Signed-off-by: Douglas Anderson
Acked-by: Greg Kroah-Hartman
Tested-by: Caesar Wang
---
Changes in v2:
- Added comment to pinctrl_init_done() as per Linus W.
Rep
ansitioned in to and out of) when (optional) power management
is enabled.
Signed-off-by: Douglas Anderson
Acked-by: Greg Kroah-Hartman
Tested-by: Caesar Wang
---
Changes in v3:
- Moved declarations to pinctrl/devinfo.h
- Fixed author/SoB
Changes in v2:
- Added comment to pinctrl_init_done() a
ly never sets this), so we'll update the
former "else" case based on this test.
Fixes: 734643dfbdde ("usb: dwc2: host: add flag to reflect bus state")
Signed-off-by: Douglas Anderson
---
drivers/usb/dwc2/hcd.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
d
The ddc-i2c-bus property was missing from the veyron dtsi file since
downstream the ddc-i2c-bus was still being specified in rk3288.dtsi and
nobody noticed when the veyron dtsi was sent upstream. Add it.
Signed-off-by: Douglas Anderson
---
Note: I noticed that this was wrong but I don&#
if it's known
to work.
Once driver support in dw_hdmi lands, boards would use this by selecting
this pinctrl for the HDMI block and then _not_ specifying a ddc-i2c-bus
and _not_ setting the status to "okay" for i2c5 (which uses the same
pins).
Signed-off-by: Douglas Anderson
---
unrelated to the current hardware errata. Only the host port
gets the quirk property, though.
Signed-off-by: Douglas Anderson
---
arch/arm/boot/dts/rk3288.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 4f76805..03de4
As per the change to the rk3288 USB phy driver, we can now enable the
PHYs as reset providers. Do so.
Signed-off-by: Douglas Anderson
---
arch/arm/boot/dts/rk3288.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index
#x27;s
usb-next merged in.
These patches currently conflict with patches that I posted previously
to enable USB wakeup from S3, specifically:
* https://patchwork.kernel.org/patch/6727081/
* https://patchwork.kernel.org/patch/6727121/
...those patches no longer apply anyway, so presumably they need t
s reset. This reset seems to have the ability to unwedge
the dwc2 "host" port when a remote wakeup happens. It may have other
redeeming qualities as well.
Signed-off-by: Douglas Anderson
---
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 6 ++
drivers/phy/phy-rockchip-usb.c
ot;") for
some details on the reset that we plan to use.
Signed-off-by: Douglas Anderson
Signed-off-by: Yunzhi Li
---
Documentation/devicetree/bindings/usb/dwc2.txt | 7 +++
drivers/usb/dwc2/core.h| 5 +
drivers/usb/dwc2/core_intr.c | 7
n this
case reg-names wasn't needed but the driver already landed relying
on reg-names so we'll just document it and move on.
Fixes: 8b1087fa3a27 ("phy: qcom-qmp: Fix dts bindings to reflect reality")
Suggested-by: Rob Herring
Signed-off-by: Douglas Anderson
---
.../device
phen found. Hopefully someone can test them out and
make sure they work as advertised.
Douglas Anderson (2):
pinctrl: ssbi-gpio: Fix pm8xxx_pin_config_get() to be compliant
pinctrl: spmi-mpp: Fix pmic_mpp_config_get() to be compliant
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 19 ++-
t
values so I kept doing that. It seems like another driver (ssbi-gpio)
uses a custom attribute (PM8XXX_QCOM_PULL_UP_STRENGTH) for something
similar so maybe a future change should do that here too.
Fixes: cfb24f6ebd38 ("pinctrl: Qualcomm SPMI PMIC MPP pin controller driver")
Signed-o
Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-gpio has the same
problem. Let's fix it there too.
Fixes: b4c45fe974bc ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers")
Signed-off-by: Douglas Anderson
---
drivers/pinctrl/qcom/pin
No functional change here but it can make the code more readable to
have breaks in the "default" case even though it's the last case.
Let's add them.
Signed-off-by: Douglas Anderson
---
drivers/regulator/qcom-rpmh-regulator.c | 3 +++
1 file changed, 3 insertions(+)
in v2:
- Use "0x784000" for qfprom rather than "0x78" as per docs.
- Add calibration for 2nd USB port too
- LDO14 initial mode is LPM and shouldn't be always on (Vivek G)
- LDO25 should have min voltage of 3.3V
Douglas Anderson (2):
arm64: dts: qcom: sdm845-mtp: Add
rites on pmi8998:
- pm_comm_write_byte(2, 0x1153, 0x2C, 0);
- pm_comm_write_byte(2, 0x1152, 0x07, 0);
- pm_comm_write_byte(2, 0x1140, 0x00, 0);
- pm_comm_write_byte(2, 0x1140, 0x01, 0);
Signed-off-by: Douglas Anderson
---
Changes in v2: None
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 61 +
From: Manu Gautam
This adds nodes for USB and related PHYs.
Signed-off-by: Manu Gautam
[dianders: reworked quite a bit]
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Use "0x784000" for qfprom rather than "0x78" as per docs.
- Add calibration for 2nd USB port t
ct.
NOTE: This patch is loosely based on one originally shared to me by
David Collins.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- LDO14 initial mode is LPM and shouldn't be always on (Vivek G)
- LDO25 should have min voltage of 3.3V
arch/arm64/boot/dts/qcom/
more likely to work. The rest of the patches
just work on regulator_summary to try to make it so we can confirm
that the first patch works.
Douglas Anderson (4):
regulator: core: If consumers don't call regulator_set_load() assume
max
regulator: core: Add the opmode to regulat
It's handy to know what opmode a regulator has been configured to in
the summary. Add it.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/regulator/core.c b/dr
a consumer
hasn't called regulator_set_load() and the case where a consumer
called it but the load is currently 0 mA.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regul
Most functions that access the rdev lock the rdev mutex before looking
at data. ...but not the code that implements the debugfs
regulator_summary. It probably should though, so let's do it.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c
tness first.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 10 +-
drivers/regulator/internal.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 6ed568b96c0e..a4da68775b49 100644
--- a/dr
ort too
- LDO14 initial mode is LPM and shouldn't be always on (Vivek G)
- LDO25 should have min voltage of 3.3V
Douglas Anderson (2):
arm64: dts: qcom: sdm845-mtp: Add RPMh VRM/XOB regulators
arm64: dts: qcom: sdm845-mtp: Add nodes for USB
Manu Gautam (1):
arm64: dts: qcom: sdm845: A
t need to
churn with lots of patches adding regulator_set_load() calls
to drivers.
NOTE: This patch is loosely based on one originally shared to me by
David Collins.
Signed-off-by: Douglas Anderson
---
Changes in v3:
- Set vin-supply for s4a_1p8 properly (Stephen).
- All regulators now H
rites on pmi8998:
- pm_comm_write_byte(2, 0x1153, 0x2C, 0);
- pm_comm_write_byte(2, 0x1152, 0x07, 0);
- pm_comm_write_byte(2, 0x1140, 0x00, 0);
- pm_comm_write_byte(2, 0x1140, 0x01, 0);
Signed-off-by: Douglas Anderson
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/qcom/sdm845-mtp.dt
From: Manu Gautam
This adds nodes for USB and related PHYs.
Signed-off-by: Manu Gautam
[dianders: reworked quite a bit]
Signed-off-by: Douglas Anderson
---
Changes in v3:
- Don't just fix qfprom unit address, fix the reg too (Stephen).
- Rebased to next-20180822
Changes in v2:
Add both the interface and core clock.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Only 19.2, 100, 150, and 300 MHz now.
- All clocks come from MAIN rather than EVEN.
- Use parent map 0 instead of new parent map 9.
drivers/clk/qcom/gcc-sdm845.c | 63
0, 150, and 300 MHz now.
- All clocks come from MAIN rather than EVEN.
- Use parent map 0 instead of new parent map 9.
Douglas Anderson (2):
clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
clk: qcom: Add qspi (Quad SPI) clocks for sdm845
drivers/clk/qcom/gcc-sdm8
These clocks will need to be defined in the clock driver and
referenced in device tree files.
Signed-off-by: Douglas Anderson
---
Changes in v2: None
include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h
These clocks will need to be defined in the clock driver and
referenced in device tree files.
Signed-off-by: Douglas Anderson
---
Changes in v3: None
Changes in v2: None
include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings
Add both the interface and core clock.
Signed-off-by: Douglas Anderson
(am from https://lore.kernel.org/patchwork/patch/966680/mbox)
---
Changes in v3:
- Removed gcc_parent_names_9 which I had left in (doh!).
Changes in v2:
- Only 19.2, 100, 150, and 300 MHz now.
- All clocks come from MAIN
ent_names_9 which I had left in (doh!).
Changes in v2:
- Only 19.2, 100, 150, and 300 MHz now.
- All clocks come from MAIN rather than EVEN.
- Use parent map 0 instead of new parent map 9.
Douglas Anderson (2):
clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
clk: qcom: Add qsp
98b690b21c ("kbuild: Add a cache for generated variables")
Reported-by: Yang Shi
Reported-by: Dave Hansen
Reported-by: Mathieu Malaterre
Signed-off-by: Douglas Anderson
---
Changes in v3:
- Fix as per Masahiro Yamada (move change to main Makefile)
Changes in v2:
- Don't erro
ain Makefile instead of Kbuild.include
Changes in v2:
- Don't error if MAKECMDGOALS is blank.
Douglas Anderson (2):
kbuild: Require a 'make clean' if we detect gcc changed underneath us
kbuild: Don't mess with the .cache.mk when root
Makefile | 15 ++
e'll consider this heuristic good
enough because the problem really shouldn't be that serious.
Fixes: 3298b690b21c ("kbuild: Add a cache for generated variables")
Suggested-by: Masahiro Yamada
Signed-off-by: Douglas Anderson
---
Changes in v3:
- Use "uid 0" as th
be reporting kernel registers.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Init cpu_context in one line
- Explain that task_pt_regs are userspace
arch/arm64/kernel/kgdb.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/kgdb.c
We could also just make the name field
much bigger so that we're not likely to run into this. ...but both
seem like we'll just hit the bug again.
Signed-off-by: Douglas Anderson
---
include/linux/serial_core.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/i
ioning again after another
suspend/resume cycle (especially if the resume failure was
intermittent for some reason).
Obviously this patch is pretty simplistic and certainly doesn't fix
the world, but perhaps it moves us in the right direction?
Signed-off-by: Douglas Anderson
---
drivers
mers")
Reported-by: Brian Masney
Signed-off-by: Douglas Anderson
Tested-by: Brian Masney
---
drivers/regulator/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index dbe2f2e6e625..dffee5432ca1 100644
--- a/drivers/regulator/
com
Fixes: 84b66b211603 ("dt-bindings: clock: Introduce QCOM Video clock bindings")
Suggested-by: Stephen Boyd
Signed-off-by: Douglas Anderson
---
Documentation/devicetree/bindings/clock/qcom,videocc.txt | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/dev
The "requested_microamps" sysfs attribute was only being exposed for
"current" regulators. This didn't make sense. Allow it to be exposed
always.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 4
1 file changed, 4 deletions(-)
diff --git a/d
w places in the code were not properly checking for errors.
Let's resolve this.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index ff5ca185bb8f..0052bbc8
ely
resolving regulators.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 23e852d38b88..2eda87520832 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regul
Now that consumers all keep track of their own enable count, let's add
it into the regulator_summary.
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
e counts for always-on regulators because they were, well,
always on. While we could keep the optimization still for some
cases, it's cleaner to just remove it. A later patch will attempt
to get some efficiency back by not propogating enables up
unnecessarily.
Signed-off-by: Dougla
_count, but even that might be a little strange. For now
let's just remove the code and we can add something back in if someone
can explain what's expected.
Fixes: f8702f9e4aa7 ("regulator: core: Use ww_mutex for regulators locking")
Signed-off-by: Douglas Anderson
---
drive
: core: Use ww_mutex for regulators locking")
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 0052bbc8c531..63a8af1e2256 100644
--- a/drivers/regulator/core.
e counts for always-on regulators because they were, well,
always on. While we could keep the optimization still for some
cases, it's cleaner to just remove it. A later patch will attempt
to get some efficiency back by not propogating enables up
unnecessarily.
Signed-off-by: Dougla
we'll fix it together in one patch. Also: since this comes
after commit f8702f9e4aa7 ("regulator: core: Use ww_mutex for
regulators locking") we can now move to use _regulator_disable() for
our supply and keep it in the lock.
Signed-off-by: Douglas Anderson
---
NOTE: this patch is
is goes boom
at bootup.
Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for
SDM845")
Signed-off-by: Douglas Anderson
---
drivers/clk/qcom/gpucc-sdm845.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/cl
tcxo" is actually provided by the RPMh Clock
Controller. Presumably that's the one that was wanted.
Let's update the example to make this clearer.
Fixes: e431c92188a9 ("dt-bindings: clock: Introduce QCOM Graphics clock
bindings")
Signed-off-by: Douglas Anderson
---
Add the GPU clock controller nodes as per the example.
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1419b0098cb3
enabled and we'd never try them again.
Fixes: 1fc12b05895e ("regulator: core: Avoid propagating to supplies when
possible")
Reported-by: Evan Green
Signed-off-by: Douglas Anderson
---
drivers/regulator/core.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions
"fragments" to my debug kernels.
Hopefully having this extra config option is OK and useful to others
who would also prefer to make sure that kgdb is always entered on a
panic no matter what userspace might request.
Signed-off-by: Douglas Anderson
---
kernel/debug/debug_core.c |
From: Taniya Das
This adds the video clock controller node to sdm845 based on the examples
in the bindings.
Signed-off-by: Taniya Das
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Add #reset-cells = <1>.
- Sort properly.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
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