Hi Simon,
sorry but as for Luca I've lost mail with mail filter.
See below my ideas on how to improve it.
Thanks
Cheers
Il 15/11/2017 17:30, Giulio Benetti ha scritto:
Hi Luca,
I had problems with e-mail filter, so I rebuilt yours by hand.
Forgive me.
See below.
Thanks
Kind regards
>
:
GAIN 0x30 or 0x92 should be 0x82(thcal maybe?)
Can someone clarify this?
Maybe M06 or M09 are a custom firmware for focaltech ft5x,
then it has different registers?
Thanks in advance and
kind regards to everybody
--
Giulio Benetti
R Manager &
Advanced Research
MICRONOVA SRL
Sede: Via A. Nied
Hi Thomas,
Il 28/11/2017 12:20, Thomas van Kleef ha scritto:
On 28-11-17 10:50, Giulio Benetti wrote:
Hi Maxime,
Il 28/11/2017 09:35, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 01:03:59AM +0100, Giulio Benetti wrote:
Hi Maxime,
Il 16/11/2017 14:42, Giulio Benetti ha scritto:
Hi
Hi,
> Il giorno 28 nov 2017, alle ore 13:52, Maxime Ripard
> <maxime.rip...@free-electrons.com> ha scritto:
>
> On Tue, Nov 28, 2017 at 12:54:08PM +0100, Giulio Benetti wrote:
>>>>> Should I be working in sunxi-next I wonder?
>>>>
>>&g
Hi Maxime,
Il 28/11/2017 09:35, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 01:03:59AM +0100, Giulio Benetti wrote:
Hi Maxime,
Il 16/11/2017 14:42, Giulio Benetti ha scritto:
Hi,
Il 16/11/2017 14:39, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 02:17:08PM +0100, Giulio Benetti
Il 28/11/2017 14:07, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 02:03:43PM +0100, Giulio Benetti wrote:
Hi,
Il giorno 28 nov 2017, alle ore 13:52, Maxime Ripard
<maxime.rip...@free-electrons.com> ha scritto:
On Tue, Nov 28, 2017 at 12:54:08PM +0100, Giulio Benetti wrote:
Sh
Hi Thomas,
Il 28/11/2017 12:29, Thomas van Kleef ha scritto:
Hi,
On 28-11-17 12:26, Giulio Benetti wrote:
Hi Thomas,
Il 28/11/2017 12:20, Thomas van Kleef ha scritto:
On 28-11-17 10:50, Giulio Benetti wrote:
Hi Maxime,
Il 28/11/2017 09:35, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017
Il 28/11/2017 16:17, Maxime Ripard ha scritto:
On Tue, Nov 28, 2017 at 02:12:31PM +0100, Giulio Benetti wrote:
And really, just develop against 4.14. sunxi-next is rebased, and it's
just not something you can base some work on.
Where do we can work on then?
Should Thomas setup his own github
Hi Maxime,
Il 16/11/2017 14:42, Giulio Benetti ha scritto:
Hi,
Il 16/11/2017 14:39, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 02:17:08PM +0100, Giulio Benetti wrote:
Hi Hans,
Il 16/11/2017 14:12, Hans Verkuil ha scritto:
On 16/11/17 13:57, Giulio Benetti wrote:
Il 16/11/2017 13:53
Il 16/11/2017 13:53, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 01:30:52PM +0100, Giulio Benetti wrote:
On Thu, Nov 16, 2017 at 11:37:30AM +0100, Giulio Benetti wrote:
Il 16/11/2017 11:31, Andreas Baierl ha scritto:
Am 16.11.2017 um 11:13 schrieb Giulio Benetti:
Hello,
Hello,
I'm
Hi Hans,
Il 16/11/2017 14:12, Hans Verkuil ha scritto:
On 16/11/17 13:57, Giulio Benetti wrote:
Il 16/11/2017 13:53, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 01:30:52PM +0100, Giulio Benetti wrote:
On Thu, Nov 16, 2017 at 11:37:30AM +0100, Giulio Benetti wrote:
Il 16/11/2017 11:31
Hi,
Il 16/11/2017 14:39, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 02:17:08PM +0100, Giulio Benetti wrote:
Hi Hans,
Il 16/11/2017 14:12, Hans Verkuil ha scritto:
On 16/11/17 13:57, Giulio Benetti wrote:
Il 16/11/2017 13:53, Maxime Ripard ha scritto:
On Thu, Nov 16, 2017 at 01:30
to be the right one
for v4l2 and removed Russell, Rob and Mark
On Thu, Nov 16, 2017 at 11:37:30AM +0100, Giulio Benetti wrote:
Il 16/11/2017 11:31, Andreas Baierl ha scritto:
Am 16.11.2017 um 11:13 schrieb Giulio Benetti:
Hello,
Hello,
I'm wondering why cedrus
https://github.com/FlorentRevest/linux
Hi Luca,
Il 17/11/2017 18:16, Luca Ceresoli ha scritto:
Hi Giulio,
On 15/11/2017 17:30, Giulio Benetti wrote:
Hi Luca,
I had problems with e-mail filter, so I rebuilt yours by hand.
Forgive me.
See below.
Thanks
Kind regards
Hi Giulio,
On 14/11/2017 22:42, Giulio Benetti wrote:
Hello
Hi Simon,
sorry for the mess with mailing list.
My mail filter gave me problems and removed e-mails from linux-input
mailing list.
> Hi Giulio
>
> On Tue, 2017-11-14 at 22:42 +0100, Giulio Benetti wrote:
> > I'm using ft5206 with edt-ft5x06.c driver,
> > but what I
.
Best regards
--
Giulio Benetti
R Manager &
Advanced Research
MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 049/8931563 - Fax 049/8931346
Cod.Fiscale - P.IVA 02663420285
Capitale Sociale € 26.000 i.v.
Iscritta al Reg. Imprese di Padova N. 02663420285
Numero R.E.A. 258642
Hi,
Il 16/11/2017 11:31, Andreas Baierl ha scritto:
Am 16.11.2017 um 11:13 schrieb Giulio Benetti:
Hello,
Hello,
I'm wondering why cedrus
https://github.com/FlorentRevest/linux-sunxi-cedrus has never been
merged with linux-sunxi sunxi-next.
Because it is not ready to be merged
Hi Luca,
I had problems with e-mail filter, so I rebuilt yours by hand.
Forgive me.
See below.
Thanks
Kind regards
> Hi Giulio,
>
> On 14/11/2017 22:42, Giulio Benetti wrote:
> > Hello everybody,
> >
> > I'm using ft5206 with edt-ft5x06.c driver,
> > but what
This patch gives possibility to set parallel lcd pins for RGB888.
To be used with tcon0 in your .dts
Best regards
Giulio Benetti
Micronova srl
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 8
1 file changed, 8 insertions(+)
This patch adds device tree mali node compatible with r6p2 utgard kernel driver
provided by ARM and patched by maxime ripard on his github.
It can be easily used in target.dts with:
{
status = "okay";
}
then loading mali.ko in user space.
Best regards
Giulio Benetti
Mic
This patch gives possibility to set parallel lcd pins for RGB888.
To be used with tcon0 in your .dts
Best regards
Giulio Benetti
Micronova srl
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 8
1 file changed, 8 insertions(+)
This patch adds device tree mali node compatible with r6p2 utgard kernel driver
provided by ARM and patched by maxime ripard on his github.
It can be easily used in target.dts with:
{
status = "okay";
}
then loading mali.ko in user space.
Best regards
Giulio Benetti
Mic
On sun7i-a20-* there's no way to enable PA00--PA27 as RGB888 LCD0 pins.
Add lcd_rgb888_pins in sun7i-a20.dtsi.
It can be used on sun7i-a20-olinuxino-lime.dts.
This patch gives possibility to set parallel lcd pins for RGB888.
To be used with tcon0 in your .dts
Best regards
Giulio Benetti
;okay";
}
then loading mali.ko in user space.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7
Hi,
Il 07/11/2017 12:05, Maxime Ripard ha scritto:
Hi,
On Tue, Nov 07, 2017 at 11:03:30AM +0100, Giulio Benetti wrote:
This patch adds device tree mali node compatible with r6p2 utgard kernel driver
provided by ARM and patched by maxime ripard on his github.
It can be easily used
Board could be any with A20,
for example Olinuxino A20.
Or our Q027, S027 boards, but final dts still are not complete.
--
Giulio Benetti
R Manager &
Advanced Research
MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 049/8931563 - Fax 049/8931346
Cod.Fiscale - P.IVA 0266342
Hi Sergey,
Il 04/05/2018 23:59, Sergey Suloev ha scritto:
Hi, Giulio,
On 05/05/2018 12:52 AM, Giulio Benetti wrote:
Hi Maxime!
Il 04/05/2018 10:06, Maxime Ripard ha scritto:
Hi,
On Wed, May 02, 2018 at 06:41:34PM +0200, Giulio Benetti wrote:
You don't have to handcode the fragments
Hi Maxime!
Il 04/05/2018 10:06, Maxime Ripard ha scritto:
Hi,
On Wed, May 02, 2018 at 06:41:34PM +0200, Giulio Benetti wrote:
You don't have to handcode the fragments anymore with the new syntax,
and U-Boot makes it really trivial to use if you use the FIT image
format to have multiple
Hi,
Il 07/05/2018 09:30, Maxime Ripard ha scritto:
Otherwise as in-tree dts with make dtbs "-@" argument is not passed.
Right?
You should use DTC_FLAGS='-@'
Thank you, I'm going to use that.
--
Giulio Benetti
CTO
MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 0
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with freq_test attribute, OUT pin will tick 512 times
faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.b
sysfs.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
V1 => V2: changed "calibration" from dt property to rtc sysfs offset
drivers/rtc/rtc-ds1307.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/rtc/rtc
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
://elixir.bootlin.com/linux/v4.16.7/source/Documentation/ABI/testing/sysfs-class-rtc#L68
and https://elixir.bootlin.com/linux/v4.16.7/source/drivers/rtc/interface.c#L999
Used sysfs now and just submitted V2 patchset.
Thanks for pointing me those links.
--
Giulio Benetti
CTO
MICRONOVA SRL
Sede: Via A. Niedda
Sorry everybody,
Il 09/05/2018 20:28, Giulio Benetti ha scritto:
static int ds1307_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -1783,6 +1851,24 @@ static int ds1307_probe(struct i2c_client *client,
if (err)
return err
Hi Rob,
Il 08/05/2018 19:40, Rob Herring ha scritto:
On Tue, May 8, 2018 at 9:56 AM, Giulio Benetti
<giulio.bene...@micronovasrl.com> wrote:
m41txx chips can hold a calibration value to get really near to real
tick value.
Typo in the subject.
Add calibration property(ranging betwee
Hi Rob,
Il 08/05/2018 19:44, Rob Herring ha scritto:
On Tue, May 8, 2018 at 9:56 AM, Giulio Benetti
<giulio.bene...@micronovasrl.com> wrote:
On m41txx you can enable open-drain OUT pin to check if calibration is ok.
Enabling OUT pin with frequency-test bool property, OUT pin will ti
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with freq_test attribute, OUT pin will tick 512 times
faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.b
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
sysfs.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 0ab0c166da83..33895668b363
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
On m41txx you can enable open-drain OUT pin to check if calibration is ok.
Enabling OUT pin with frequency-test bool property, OUT pin will tick
512 times faster than 1s tick base.
Enable FT bit on CONTROL register if calibration is active.
Signed-off-by: Giulio Benetti <giulio.b
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
m41txx chips can hold a calibration value to get really near to real
tick value.
Add calibration property(ranging between (-31) and 31), so on every probe
calibration value will be written to rtc.
This is because ic could loose supply due to low battery.
Signed-off-by: Giulio Benetti
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
V3 => V4:
* use ppm as offset input according to documentation instead of
raw
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with freq_test attribute, OUT pin will tick 512 times
faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.b
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
include/uapi/linux/tty_flags.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/linux/tty_flags.h b/include/uapi/linux/tty_flags.h
index 6ac609a00dea..900a32e63424 100644
--- a/include/uapi
Hi,
Il 16/05/2018 17:36, Greg KH ha scritto:
On Wed, May 16, 2018 at 04:39:31PM +0200, Giulio Benetti wrote:
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
include/uapi/linux/tty_flags.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Sorry, but I can'
On #define ASYNCB_FOURPORT there's an ortography error on comment:
"Set OU1, OUT2 per AST Fourport settings"
Change it into:
"Set OUT1, OUT2 per AST Fourport settings"
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
V1 => V2:
* add commit log
i
Oh, sorry, I've forgotten to reword commit log.
I follow with v5 patchset.
Sorry again.
Giulio
Il 16/05/2018 12:05, Giulio Benetti ha scritto:
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with freq_test attribute, OUT pin will tick 512 times
faster
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.b
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
V3 => V4:
* use ppm as offset input according to documentation instead of
raw
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.b
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 81
1 file chang
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
The m41t11 variant is very similar to the already supported m41t00 and
m41t0, but it has also 56 bytes of NVRAM.
Add it to driver taking into account NVRAM section.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
.../devicetree/bindings/rtc/rtc-ds1307.txt
Hi,
Il 16/05/2018 23:10, Alexandre Belloni ha scritto:
On 16/05/2018 23:02:16+0200, Giulio Benetti wrote:
+static ssize_t frequency_test_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf
Hi,
Il 16/05/2018 22:22, Andy Shevchenko ha scritto:
On Wed, May 16, 2018 at 1:32 PM, Giulio Benetti
<giulio.bene...@micronovasrl.com> wrote:
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512
m41txx chips can hold a calibration value to get correct clock bias.
Add offset handling (ranging between -63ppm and 126ppm) via sysfs.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 81
1 file chang
data field points to m41t00, instead it should point to m41t0.
Driver works correctly because on both cases(m41t0 and m41t00) chip_desc
are equal.
Point to right enum m41t0 instead of m41t00.
Signed-off-by: Giulio Benetti <giulio.bene...@micronovasrl.com>
---
drivers/rtc/rtc-ds1307.c | 2
Sorry, no V5 => V6 changelog, I resubmit.
Il 16/05/2018 23:07, Giulio Benetti ha scritto:
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT
On m41txx you can enable open-drain OUT pin to check if offset is ok.
Enabling OUT pin with frequency_test_enable attribute, OUT pin will tick
512 times faster than 1s tick base.
Enable or Disable FT bit on CONTROL register if freq_test is 1 or 0.
Signed-off-by: Giulio Benetti <giulio.b
If "linux,rs485-enabled-at-boot-time" is specified need to setup 485
in probe function.
Call uart_get_rs485_mode() to get rs485 configuration, then call
rs485_config() callback directly to setup port as rs485.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c |
Need to use rs485 transceiver so let's use existing em485 485 emulation
layer on top of 8250.
Add rs485_config callback to port.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/tty
is on with RTS_AFTER_SEND set, if so return -EBUSY in
rpm_suspend,
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index 888280ff5451..6b0ee6dc8ad0 100644
Some 8250 ports only have TEMT interrupt, so current implementation
can't work for ports without it. The only chance to make it work is to
loop-read on LSR register.
With NO TEMT interrupt check if both TEMT and THRE are set looping on
LSR register.
Signed-off-by: Giulio Benetti
---
drivers
When rs485 enabled and RTS_AFTER_SEND set on startup, need to preserve
mctrl status, because later functions will call set_mctrl passing
port->mctrl=0 overriding rts status, resulting in rts pin in
transmission when idle.
Make mctrl reflect rts pin state.
Signed-off-by: Giulio Bene
Il 06/06/2018 13:56, Andy Shevchenko ha scritto:
On Wed, 2018-06-06 at 11:49 +0200, Giulio Benetti wrote:
em485 gets lost during serial8250_register_8250_port().
Copy em485 to final uart port.
Is it needed at all?
The individual driver decides either to use software emulation (and
calls
If rs485 is enabled and RTS_AFTER_SEND is set on startup need to keep
TIOCM_RTS asserted to keep rs485 transceiver in RX when idle.
Check if rs485 is on and RTS_AFTER_SEND is set and mask port->mctrl with
TIOCM_RTS too and not only TIOCM_DTR.
Signed-off-by: Giulio Benetti
---
drivers/
RS485 can modify mctrl on startup, especially when RTS_AFTER_SEND is on
TIOCM_RTS is set, then need to keep it set when registering port.
Copy mctrl to new port too.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git
em485 gets lost during serial8250_register_8250_port().
Copy em485 to final uart port.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/8250/8250_core.c
b/drivers/tty/serial/8250/8250_core.c
index
--
Giulio Benetti
CTO
MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 049/8931563 - Fax 049/8931346
Cod.Fiscale - P.IVA 02663420285
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Iscritta al Reg. Imprese di Padova N. 02663420285
Numero R.E.A. 258642
Il 06/06/2018 14:03, Andy Shevchenko ha scritto:
On Wed, 2018-06-06 at 11:49 +0200, Giulio Benetti wrote:
If rs485 is enabled and RTS_AFTER_SEND is set on startup need to keep
TIOCM_RTS asserted to keep rs485 transceiver in RX when idle.
Check if rs485 is on and RTS_AFTER_SEND is set and mask
Il 07/06/2018 09:03, Matwey V. Kornilov ha scritto:
2018-06-06 22:15 GMT+03:00 Giulio Benetti :
Il 06/06/2018 20:55, Matwey V. Kornilov ha scritto:
2018-06-06 16:11 GMT+03:00 Andy Shevchenko
:
On Wed, 2018-06-06 at 14:15 +0200, Giulio Benetti wrote:
Il 06/06/2018 13:56, Andy Shevchenko ha
Hi,
Il 04/06/2018 13:38, Andy Shevchenko ha scritto:
On Mon, 2018-06-04 at 12:50 +0200, Giulio Benetti wrote:
Hi,
Il 04/06/2018 12:17, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
Some 8250 ports only have TEMT interrupt, so current
implementation
Hi everybody,
Il 04/06/2018 12:34, Matwey V. Kornilov ha scritto:
2018-06-04 13:12 GMT+03:00 Andy Shevchenko :
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
Need to handle rs485 with 8250_dw port.
Use existing em485 emulation layer for 8250 taking care to fix some
bug
and taking
Hi,
Il 04/06/2018 12:13, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
em485 gets lost during serial8250_register_8250_port().
Copy em485 to final uart port.
Fixes better to go first.
I think you need to reorder the series.
Ok, thanks.
So after re
Hi,
Il 04/06/2018 12:17, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote:
Some 8250 ports only have TEMT interrupt, so current implementation
can't work for ports without it. The only chance to make it work is to
loop-read on LSR register.
With NO TEMT
Il 04/06/2018 13:49, Andy Shevchenko ha scritto:
On Fri, 2018-06-01 at 16:11 +0200, Giulio Benetti wrote:
It can be useful to override 8250 mctrl lines with gpios, for rts on
rs485 for example, when rts is not mapped correctly to HW RTS pin.
Enable SERIAL_MCTRL_GPIO by default
Il 04/06/2018 19:40, Matwey V. Kornilov ha scritto:
01.06.2018 15:40, Giulio Benetti пишет:
Some 8250 ports only have TEMT interrupt, so current implementation
can't work for ports without it. The only chance to make it work is to
loop-read on LSR register.
With NO TEMT interrupt check if both
Il 04/06/2018 13:44, Andy Shevchenko ha scritto:
On Mon, 2018-06-04 at 12:42 +0200, Giulio Benetti wrote:
I don't see in Cc list author of rs485 code, who might be
interested in
this.
So, added him here.
Thanks Andy for adding in Cc an reviewing.
Dumb question: how did you find him?
I'm
When rs485 enabled and RTS_AFTER_SEND set on startup, need to preserve
mctrl status, because later functions will call set_mctrl passing
port->mctrl=0 overriding rts status, resulting in rts pin in
transmission when idle.
Make mctrl reflect rts pin state.
Signed-off-by: Giulio Bene
Need to handle rs485 with 8250_dw port.
Use existing em485 emulation layer for 8250 taking care to fix some bug
and taking care especially of RTS_AFTER_SEND case.
Giulio Benetti (8):
serial: 8250_dw: add em485 support
serial: 8250_dw: allow enable rs485 at boot time
serial: 8250: Copy
If rs485 is enabled and RTS_AFTER_SEND is set on startup need to keep
TIOCM_RTS asserted to keep rs485 transceiver in RX when idle.
Check if rs485 is on and RTS_AFTER_SEND is set and mask port->mctrl with
TIOCM_RTS too and not only TIOCM_DTR.
Signed-off-by: Giulio Benetti
---
drivers/
Need to use rs485 transceiver so let's use existing em485 485 emulation
layer on top of 8250.
Add rs485_config callback to port.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/tty
is on with RTS_AFTER_SEND set, if so return -EBUSY in
rpm_suspend,
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index 888280ff5451..6b0ee6dc8ad0 100644
Some 8250 ports only have TEMT interrupt, so current implementation
can't work for ports without it. The only chance to make it work is to
loop-read on LSR register.
With NO TEMT interrupt check if both TEMT and THRE are set looping on
LSR register.
Signed-off-by: Giulio Benetti
---
drivers
RS485 can modify mctrl on startup, especially when RTS_AFTER_SEND is on
TIOCM_RTS is set, then need to keep it set when registering port.
Copy mctrl to new port too.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git
If "linux,rs485-enabled-at-boot-time" is specified need to setup 485
in probe function.
Call uart_get_rs485_mode() to get rs485 configuration, then call
rs485_config() callback directly to setup port as rs485.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_dw.c |
em485 gets lost during serial8250_register_8250_port().
Copy em485 to final uart port.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/8250/8250_core.c
b/drivers/tty/serial/8250/8250_core.c
index
Sometimes mctrl signals can be connected to pins different from HW ones.
User serial_mctrl_gpio helpers to align HW signals(RTS, CTS, etc.) with
gpios-rts, gpios-cts etc.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/8250_core.c | 6 ++
drivers/tty/serial/8250/8250_port.c | 18
It can be useful to override 8250 mctrl lines with gpios, for rts on
rs485 for example, when rts is not mapped correctly to HW RTS pin.
Enable SERIAL_MCTRL_GPIO by default.
Signed-off-by: Giulio Benetti
---
drivers/tty/serial/8250/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Andy,
Il 06/06/2018 15:11, Andy Shevchenko ha scritto:
On Wed, 2018-06-06 at 14:15 +0200, Giulio Benetti wrote:
Il 06/06/2018 13:56, Andy Shevchenko ha scritto:
On Wed, 2018-06-06 at 11:49 +0200, Giulio Benetti wrote:
em485 gets lost during
Copy em485 to final uart port.
Is it needed
Il 06/06/2018 18:51, Andy Shevchenko ha scritto:
On Wed, Jun 6, 2018 at 12:51 PM, Giulio Benetti
wrote:
Need to use rs485 transceiver so let's use existing em485 485 emulation
layer on top of 8250.
Add rs485_config callback to port.
Besides the fact the series lacks of cover letter, I think
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