:
- Improved the spelling and the wording of the documentation and the
1st commit log
- Removed the end_of_list name which are unused here.
- Fix the cpu clock by using of_clk_src_onecell_get in the same way it
was used for the core clocks
Regards,
Gregory CLEMENT (3):
clk: mvebu: add armada-370
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
cc: John Stultz johns...@us.ibm.com
---
arch/arm/boot/dts/armada-370-db.dts |4
arch/arm/boot/dts/armada-370-xp.dtsi |1 +
drivers/clocksource/time-armada-370-xp.c | 11 ++-
3 files changed, 7
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi | 12 +
arch/arm/boot/dts/armada-xp.dtsi| 48 +++
arch/arm/mach-mvebu/Kconfig |5
arch/arm/mach-mvebu/armada-370-xp.c |8
forward. For a new
SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children
clocks
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../devicetree/bindings
On 10/17/2012 05:39 PM, Jason Cooper wrote:
Mike,
On Mon, Oct 15, 2012 at 02:18:16PM +0200, Gregory CLEMENT wrote:
Hello Mike,
The v3.7-rc1 was released yesterday. So here it is the updated version
of my patch set. The rebase was flawless. An I have just fixed a typo
in the device tree
, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
---
arch/arm/plat-orion/addr-map.c |4
arch/arm/plat-orion/include/plat/addr-map.h |1 +
2 files changed
initialization of the platform.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |3 +-
arch/arm/mach-mvebu/addr-map.c |3 ++
arch/arm/mach-mvebu/armada-370-xp.c |1 +
arch/arm/mach
to be able to set the memory windows as
shared memory.
This series depend on the SMP patch set posted on Monday
(http://thread.gmane.org/gmane.linux.ports.arm.kernel/194901).
Regards,
Gregory
Gregory CLEMENT (2):
arm: plat-orion: Add coherency attribute when setup mbus target
arm: mvebu: Add
On 10/24/2012 01:36 PM, Arnd Bergmann wrote:
On Wednesday 24 October 2012, Gregory CLEMENT wrote:
+void __init armada_370_xp_coherency_iocache_init(void)
+{
+ /* When the coherency fabric is available, the Armada XP and
+* Aramada 370 are close to a coherent architecture, so we
On 10/24/2012 10:25 AM, Andrew Lunn wrote:
On Wed, Oct 24, 2012 at 10:04:01AM +0200, Gregory CLEMENT wrote:
Armada 370 and XP come with an unit called coherency fabric. This unit
allows to use the Armada XP as a nearly coherent architecture. The
coherency mechanism uses snoop filters to ensure
On 10/24/2012 01:48 PM, Gregory CLEMENT wrote:
On 10/24/2012 01:36 PM, Arnd Bergmann wrote:
On Wednesday 24 October 2012, Gregory CLEMENT wrote:
+void __init armada_370_xp_coherency_iocache_init(void)
+{
+ /* When the coherency fabric is available, the Armada XP and
+* Aramada
-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Cc: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mach-mvebu/armada-370-xp.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c
b/arch/arm/mach-mvebu/armada-370-xp.c
index
From: Lior Amsalem al...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/armada-370-db.dts |3 +++
arch/arm/boot/dts/armada-370-xp.dtsi | 10 ++
arch/arm/boot/dts/armada-xp-db.dts
/gmane.linux.kernel/1375701). The git branch
called mvebu-SATA-for-3.8 is also available at
https://github.com/MISL-EBU-System-SW/mainline-public.git.
Regards,
Gregory
Gregory CLEMENT (1):
arm: mvebu: increase atomic coherent pool size for armada 370/XP
Lior Amsalem (1):
arm: mvebu: adding
On 10/24/2012 02:24 PM, Arnd Bergmann wrote:
On Wednesday 24 October 2012, Gregory CLEMENT wrote:
On 10/24/2012 01:48 PM, Gregory CLEMENT wrote:
On 10/24/2012 01:36 PM, Arnd Bergmann wrote:
I think it would be cleaner to statically define the operations in a
constant
structure and point
/Andrew on this.
Another comment below, though.
On Wed, 24 Oct 2012 15:49:21 +0200, Gregory CLEMENT wrote:
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi
b/arch/arm/boot/dts/armada-370-xp.dtsi
index 94b4b9e..3f08233 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm
On 10/24/2012 02:27 PM, Thomas Petazzoni wrote:
[...]
I will fixed the spelling and complete the comments as suggested
[...]
+struct dma_map_ops armada_xp_dma_ops;
static
OK
+static inline void armada_xp_sync_io_barrier(void)
+{
+writel(0x1, coherency_cpu_base +
On 10/24/2012 04:08 PM, Andrew Lunn wrote:
On Wed, Oct 24, 2012 at 03:49:21PM +0200, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/armada-370
doesn't work like this. You can
only pass the number of ports supported not the list of the port you
want to support. I've checked in the device tree binding documentation
_and_ also in the code.
Best regards,
Thomas
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded
On 10/25/2012 03:53 PM, Rob Herring wrote:
On 10/25/2012 08:18 AM, Jason Cooper wrote:
On Wed, Oct 24, 2012 at 04:05:45PM +0200, Gregory CLEMENT wrote:
On 10/24/2012 04:01 PM, Thomas Petazzoni wrote:
Hello,
Shouldn't you split into one commit adding the SATA definition in
the .dtsi + doing
On 10/25/2012 03:57 PM, Rob Herring wrote:
On 10/25/2012 08:34 AM, Gregory CLEMENT wrote:
On 10/25/2012 03:21 PM, Thomas Petazzoni wrote:
Jason,
On Thu, 25 Oct 2012 09:18:18 -0400, Jason Cooper wrote:
Jason, Andrew, do you want I split this patch as suggested by
Thomas or are you fine
the mvebu_defconfig file with only the necessary symbols.
- Updated also the multi_v7_defconfig file.
Regards,
Gregory
Gregory CLEMENT (4):
arm: mvebu: increase atomic coherent pool size for armada 370/XP
arm: mvebu: adding SATA support: dt binding for Armada 370/XP
arm: mvebu: adding SATA support
-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Acked-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mach-mvebu/armada-370-xp.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c
b/arch/arm/mach-mvebu/armada-370-xp.c
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/configs/multi_v7_defconfig |2 ++
arch/arm/configs/mvebu_defconfig|3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b
Add the SATA device tree bindings for
- Armada XP evaluation board (DB-78460-BP)
- Armada 370 evaluation board (DB-88F6710-BP-DDR3)
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/armada-370-db.dts |4
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi
b/arch/arm/boot/dts/armada-370-xp.dtsi
On 10/26/2012 02:39 PM, Andrew Lunn wrote:
On Fri, Oct 26, 2012 at 02:30:45PM +0200, Gregory CLEMENT wrote:
Hello,
this patch set adds the SATA support for Armada 370 and Armada XP. Few
changes have been done since the first version by taking in account
the comments received for the first
On 10/26/2012 03:34 PM, Andrew Lunn wrote:
On Fri, Oct 26, 2012 at 09:31:54AM -0400, Jason Cooper wrote:
On Fri, Oct 26, 2012 at 02:30:47PM +0200, Gregory CLEMENT wrote:
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch
On 10/26/2012 05:02 PM, Jason Cooper wrote:
On Fri, Oct 26, 2012 at 04:57:59PM +0200, Thomas Petazzoni wrote:
On Fri, 26 Oct 2012 15:52:25 +0200, Andrew Lunn wrote:
Now, about white spaces vs tab, I don't know what is the rule
for .dts file.
I personally use tabs, but i don't see anything
This platform, available from Globalscale has an Armada 370. For now,
only the serial port is supported. Support for network, USB and other
peripherals will be added as drivers for them become available for
Armada 370 in mainline.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
it
was used for the core clocks
Regards,
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework
.../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++
.../devicetree
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts |4
arch/arm/boot/dts/armada-370-xp.dtsi |1 +
drivers/clocksource/time-armada-370-xp.c | 11 ++-
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi | 12 +
arch/arm/boot/dts/armada-xp.dtsi| 48 +++
arch/arm/mach-mvebu/Kconfig |5
arch/arm/mach-mvebu/armada-370-xp.c |8
forward. For a new
SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children
clocks
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../devicetree/bindings
On 04/15/2013 05:47 PM, Jason Cooper wrote:
On Fri, Apr 12, 2013 at 04:29:05PM +0200, Gregory CLEMENT wrote:
Hi Jason,
I have just rebased the commits that you haven't applied yet. They are
rebased on mvebu/dt. I check that all the dtb can be built.
Thanks,
Gregory CLEMENT (3):
ARM
the patch in the following
email.
Any feedback on this issue would be welcome
Thanks,
Gregory CLEMENT (1):
ARM: don't allow to register the early_console twice
arch/arm/kernel/early_printk.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
--
1.7.9.5
--
To unsubscribe from
selected.
This patch simply doesn't allow to call twice register_console() with
the early_console.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/kernel/early_printk.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 108 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 78
arch/arm/boot/dts/armada-370-rd.dts |2 +
arch/arm/boot/dts/armada-370
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 28
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 28
opportunity to fix
all the bad indentation.
* New patch from Thomas fix cpus section indentation to finalize the
fixing of the bad indentation
* For DMA transfer, DMA_ZONE was selected instead of DMABOUNCE: all
the DMA transfer are restricted to the low 32 bits address space.
Gregory
don't support LPAE)
This was heavily based on the work of Lior Amsalem.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts |2 +-
arch/arm/boot/dts/armada-370-mirabox.dts |2 +-
arch/arm/boot/dts/armada-370-rd.dts
-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..db1bbc8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -13,6
From: Lior Amsalem al...@marvell.com
pj4b cpus are LPAE capable so enable them on LPAE compilations
Signed-off-by: Lior Amsalem al...@marvell.com
Tested-by: Franklin f...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mm/proc-v7.S |3 ++-
1 file
From: Lior Amsalem al...@marvell.com
In order to be able to support he LPAE, the internal registers virtual
base must be aligned to 2MB.
Signed-off-by: Lior Amsalem al...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/include/debug/mvebu.S |2
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi | 26 +-
arch/arm/boot/dts/armada-370.dtsi| 23 ---
From: Lior Amsalem al...@marvell.com
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/skeleton64.dtsi | 13
On 04/05/2013 10:43 PM, Arnd Bergmann wrote:
On Friday 05 April 2013, Gregory CLEMENT wrote:
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
The patch looks good but the description is a bit short.
It cannot be more brief! :)
I explained the purpose of this patch
On 04/05/2013 10:41 PM, Arnd Bergmann wrote:
On Friday 05 April 2013, Gregory CLEMENT wrote:
When LPAE is activated on Armada XP, all registers and IOs are still
32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
That means that all the DMA transfer are restricted to the low
On 04/05/2013 10:46 PM, Arnd Bergmann wrote:
On Friday 05 April 2013, Gregory CLEMENT wrote:
The Armada XP SoCs have LPAE support. This is the second version patch
set whixh allow to run kernel on this SoCs with LPAE support.
The biggest changes are the conversion of the device tree file
On 04/05/2013 10:50 PM, Arnd Bergmann wrote:
On Friday 05 April 2013, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
In order to be able to support he LPAE, the internal registers virtual
base must be aligned to 2MB.
Signed-off-by: Lior Amsalem al...@marvell.com
Signed-off
From: Lior Amsalem al...@marvell.com
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/skeleton64.dtsi | 13
.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 108 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 78
arch/arm/boot/dts/armada-370-rd.dts |2 +
arch/arm/boot/dts/armada-370
of the device tree format,
armada-370 include the 32 bit skeleton and all the armada 370 based
dts can remain the same.
This was heavily based on the work of Lior Amsalem.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |4
-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..db1bbc8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -13,6
From: Lior Amsalem al...@marvell.com
pj4b cpus are LPAE capable so enable them on LPAE compilations
Signed-off-by: Lior Amsalem al...@marvell.com
Tested-by: Franklin f...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mm/proc-v7.S |3 ++-
1 file
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).
Signed-off-by: Thomas Petazzoni
cpus section indentation to finalize the
fixing of the bad indentation
* For DMA transfer, DMA_ZONE was selected instead of DMABOUNCE: all
the DMA transfer are restricted to the low 32 bits address space.
Gregory CLEMENT (4):
ARM: mvebu: Limit the DMA zone when LPAE is selected
ARM: dts
-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/include/debug/mvebu.S |2 +-
arch/arm/mach-mvebu/armada-370-xp.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index 865c6d0
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Align the cpu node indentation with the rest of the file
[gc]: added a commit description
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 28
);
+void of_fixed_factor_clkdiv_setup(struct device_node *node);
/**
* struct clk_gate - gating clock
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
--
To unsubscribe from this list
statically deriving one clock from another in
our SOCs.
Greetings,
Christian
On Wed, Apr 10, 2013 at 05:56:25PM +0200, Gregory CLEMENT wrote:
Hi Christian,
On 04/10/2013 05:40 PM, Christian Ruppert wrote:
This patch adds a device tree binding for the simple fixed factor clock
divider
Hi Jason,
On 04/11/2013 08:08 PM, Jason Cooper wrote:
On Tue, Apr 09, 2013 at 12:52:12AM +0200, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
pj4b cpus are LPAE capable so enable them on LPAE compilations
Signed-off-by: Lior Amsalem al...@marvell.com
Tested-by: Franklin f
Hi Jason,
On 04/11/2013 08:12 PM, Jason Cooper wrote:
On Tue, Apr 09, 2013 at 12:52:13AM +0200, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT gregory.clem
On 04/12/2013 08:54 AM, Christian Ruppert wrote:
On Thu, Apr 11, 2013 at 06:26:07PM +0200, Gregory CLEMENT wrote:
On 04/11/2013 11:19 AM, Christian Ruppert wrote:
Hi Gregory,
Since there doesn't seem to be anyone opposing this feature I just
checked your patch and after adding
On 04/12/2013 08:54 AM, Christian Ruppert wrote:
On Thu, Apr 11, 2013 at 06:26:07PM +0200, Gregory CLEMENT wrote:
On 04/11/2013 11:19 AM, Christian Ruppert wrote:
Hi Gregory,
Since there doesn't seem to be anyone opposing this feature I just
checked your patch and after adding
On 04/12/2013 11:12 AM, Christian Ruppert wrote:
On Fri, Apr 12, 2013 at 11:04:51AM +0200, Gregory CLEMENT wrote:
On 04/12/2013 08:54 AM, Christian Ruppert wrote:
On Thu, Apr 11, 2013 at 06:26:07PM +0200, Gregory CLEMENT wrote:
On 04/11/2013 11:19 AM, Christian Ruppert wrote:
Hi Gregory
Add support for DT fixed-factor-clock binding to the common fixed
factor clock support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c | 36
.
- Adding CLK_OF_DECLARE
- Using IS_ERR to test the clk value
Thanks,
Gregory CLEMENT (1):
clk: add device tree fixed-factor-clock binding support
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c | 36
tested-by flag?
Thanks,
Greetings,
Christian
On Fri, Apr 12, 2013 at 11:58:28AM +0200, Gregory CLEMENT wrote:
Add support for DT fixed-factor-clock binding to the common fixed
factor clock support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../bindings/clock
Add support for DT fixed-factor-clock binding to the common fixed
factor clock support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Tested-by: Christian Ruppert christian.rupp...@abilis.com
---
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers
to test the clk value
Thanks,
Gregory CLEMENT (1):
clk: add device tree fixed-factor-clock binding support
.../bindings/clock/fixed-factor-clock.txt | 24 +
drivers/clk/clk-fixed-factor.c | 36
include/linux/clk-provider.h
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).
Signed-off-by: Thomas Petazzoni
Hi Jason,
I have just rebased the commits that you haven't applied yet. They are
rebased on mvebu/dt. I check that all the dtb can be built.
Thanks,
Gregory CLEMENT (3):
ARM: dts: mvebu: Convert all the mvebu files to use the range
property
ARM: dts: mvebu: introduce internal-regs node
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Align the cpu node indentation with the rest of the file
[gc]: added a commit description
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 32 +-
of the device tree format,
armada-370 include the 32 bit skeleton and all the armada 370 based
dts can remain the same.
This was heavily based on the work of Lior Amsalem.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |4
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm
trouble?
This is a known bug. Gregory Clement already has a fix and he
will submit it soon. In case you need this fixed ASAP, I'm attaching
you a patch with a fix.
Thanks! I'll try that.
Please note the attached patch is not ready for mainline inclusion,
as I said Gregory will submit
On 03/19/2013 08:48 PM, Florian Fainelli wrote:
On Tuesday 19 March 2013 17:43:49 Gregory CLEMENT wrote:
Hi Masami,
You can try this patch if you want.
I don't have the hardware today so I didn't test it.
If you (and also Florian and Ezequiel) can test it and if it fixed
the bug, then I
On 03/13/2013 07:17 PM, Stephen Boyd wrote:
drivers/clocksource/time-armada-370-xp.c:217:13: warning: symbol
'armada_370_xp_timer_init' was not declared. Should it be static?
Also remove the __init marking in the prototype as it's
unnecessary and drop the init.h file.
Cc: Gregory CLEMENT
cd5772dd fff5692e ed55f79e (7ed5a5f7)
---[ end trace 1b75b31a2719ed1d ]---
I am trying to figure out what happened.
Cc: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/clocksource/time-armada-370-xp.c | 85
On 03/20/2013 06:09 PM, Gregory CLEMENT wrote:
On 03/13/2013 07:17 PM, Stephen Boyd wrote:
Separate the armada 370xp local timers from the local timer API.
This will allow us to remove ARM local timer support in the near
future and makes this driver multi-architecture friendly.
At first
On 03/20/2013 06:20 PM, Stephen Boyd wrote:
On 03/20/13 10:09, Gregory CLEMENT wrote:
On 03/13/2013 07:17 PM, Stephen Boyd wrote:
Separate the armada 370xp local timers from the local timer API.
This will allow us to remove ARM local timer support in the near
future and makes this driver
On 03/20/2013 06:26 PM, Gregory CLEMENT wrote:
On 03/20/2013 06:20 PM, Stephen Boyd wrote:
On 03/20/13 10:09, Gregory CLEMENT wrote:
On 03/13/2013 07:17 PM, Stephen Boyd wrote:
Separate the armada 370xp local timers from the local timer API.
This will allow us to remove ARM local timer
From: Lior Amsalem al...@marvell.com
For mvebu IOs are 32 bits and we have 40 bits memory due to LPAE so
make sure we give 32 bits addresses to the IOs.
Signed-off-by: Lior Amsalem al...@marvell.com
Tested-by: Franklin f...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free
don't support
LPAE)
This was heavily based on the work of Lior Amsalem.
Signed-off-by: Lior Amsalem al...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts |2 +-
arch/arm/boot/dts/armada-370-mirabox.dts
. The
git branch called lpae is available at:
https://github.com/MISL-EBU-System-SW/mainline-public.git.
Thanks,
Gregory CLEMENT (1):
arm: dts: Convert mvebu device tree files to 64 bits
Lior Amsalem (4):
arm: mvebu: Aligne the internal registers virtual base to support
LPAE
arm: mvebu
From: Lior Amsalem al...@marvell.com
In order to be able to support he LPAE, the internal registers virtual
base must be aligned to 2MB.
Signed-off-by: Lior Amsalem al...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/include/debug/mvebu.S |2
From: Lior Amsalem al...@marvell.com
In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/skeleton64.dtsi | 13
From: Lior Amsalem al...@marvell.com
pj4b cpus are LPAE capable so enable them on LPAE compilations
Signed-off-by: Lior Amsalem al...@marvell.com
Tested-by: Franklin f...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mm/proc-v7.S |3 ++-
1 file
was to let the driver
find by itself the port type, but I didn't find yet how it managed to
do it and then why it failed in our case.
I will continue to investigate but any pointers are welcome.
Thanks,
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development
On 02/27/2013 03:40 PM, Gregory CLEMENT wrote:
Hello,
[ I have added linux-serial mailing list as I should added them
initially ]
when I tried to use the linux-next git tree (next-20130226), I
encountered a problem during boot: the serial port was no more
initialized on my Armada XP (ARM
Hi Heikki,
On 02/28/2013 10:26 AM, Heikki Krogerus wrote:
Hi Gregory.
On Wed, Feb 27, 2013 at 05:08:04PM +0100, Gregory CLEMENT wrote:
I found the root of the problem in drivers/tty/serial/8250/8250.c
in the autoconfig() function, when the IIR register is acceded, it is
done using
, I'll prepare the patch. I thought that Gregory was going to create
a patch for this.
If you want I still can take care of it.
Br,
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
On 01/25/2013 09:16 AM, Linus Walleij wrote:
On Tue, Jan 22, 2013 at 10:10 PM, Gregory CLEMENT
gregory.clem...@free-electrons.com wrote:
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off
can't say it didn't break anything. Maybe
this time again Maxime will be willing to test it.
For the remaining improvement related to the PWA and MMP #ifdef, I
hope to be able to work on it this week-end.
Regards
Gregory CLEMENT (1):
gpio: pca953x: use simple irqdomain
Linus Walleij (1):
gpio
-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio-pca953x.c | 32
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 1dc9906..2405946 100644
--- a/drivers
the initialization of the driver.
Based on a initial patch from Linus Walleij linus.wall...@linaro.org
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio-pca953x.c | 65 +++
1 file changed, 28 insertions(+), 37 deletions(-)
diff
On the SOCs Armada 370 and Armada XP, each CPU comes with two private
timers. This patch use the timer 0 of each CPU as local timer for the
clockevent if CONFIG_LOCAL_TIMER is selected. In the other case, use
only the private Timer 0 of CPU 0.
Signed-off-by: Gregory CLEMENT gregory.clem...@free
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