Need help on Linux PCIe

Hi, I have few question on Linux PCIe subsystem, I am trying to understand the PCIe on ARM platform. 1. Compared to PCI, PCIe have an extra port functionalists/services which is implemented drivers/pci/pcie/* is it true? 2. PCIe root complex is same as Host controller drivers in linux

Re: Need help on Linux PCIe

Thanks for your quick response. Please find my comments below. On Tue, Dec 3, 2013 at 11:09 PM, Bjorn Helgaas bhelg...@google.com wrote: On Tue, Dec 3, 2013 at 4:24 AM, Jagan Teki jagannadh.t...@gmail.com wrote: Hi, I have few question on Linux PCIe subsystem, I am trying to understand

Re: Need help on Linux PCIe

On Wed, Dec 4, 2013 at 8:41 PM, Bjorn Helgaas bhelg...@google.com wrote: On Tue, Dec 3, 2013 at 11:20 PM, Jagan Teki jagannadh.t...@gmail.com wrote: Thanks for your quick response. Please find my comments below. On Tue, Dec 3, 2013 at 11:09 PM, Bjorn Helgaas bhelg...@google.com wrote: On Tue

Re: Need help on Linux PCIe

On Wed, Dec 4, 2013 at 11:35 PM, Bjorn Helgaas bhelg...@google.com wrote: On Wed, Dec 4, 2013 at 10:00 AM, Jagan Teki jagannadh.t...@gmail.com wrote: On Wed, Dec 4, 2013 at 8:41 PM, Bjorn Helgaas bhelg...@google.com wrote: On Tue, Dec 3, 2013 at 11:20 PM, Jagan Teki jagannadh.t...@gmail.com

Re: Need help on Linux PCIe

On Thu, Dec 5, 2013 at 11:45 PM, Bjorn Helgaas bhelg...@google.com wrote: On Wed, Dec 4, 2013 at 11:30 PM, Jagan Teki jagannadh.t...@gmail.com wrote: On Wed, Dec 4, 2013 at 11:35 PM, Bjorn Helgaas bhelg...@google.com wrote: On Wed, Dec 4, 2013 at 10:00 AM, Jagan Teki jagannadh.t...@gmail.com

I2C Slave monitor mode support

Hi, Few of the I2C interfaces are [operated] with slave monitor mode, when there is a requirement for a particular slave may need to wait some time to get the ADDR before sending an ACK. In slave monitor mode, the I2C interface is set up as a master and continues to attempt a transfer to a

Re: [PATCH 2/2] Documentation: pci: Add pcie-howto.txt

Hi Randy On Wed, Dec 11, 2013 at 11:02 PM, Randy Dunlap rdun...@infradead.org wrote: On 12/11/13 01:15, Jagannadha Sutradharudu Teki wrote: Added pcie-howto.txt for describing the information on PCI Express basics and Root Complex driver. Signed-off-by: Jagannadha Sutradharudu Teki

Link up issue on ethernet/realtek/r8169.c

Hi, I'm using TP-LINK PCIe NIC card on my PCIe Root Complex. Probing looks fine by setting: r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded PCI: enabling device :00:00.0 (0140 - 0143) PCI: enabling device :01:00.0 (0140 - 0143) r8169 :01:00.0 eth0: RTL8168e/8111e at 0xf006a000,

Re: Link up issue on ethernet/realtek/r8169.c

On Fri, Apr 4, 2014 at 12:17 PM, Jagan Teki jagannadh.t...@gmail.com wrote: Hi, I'm using TP-LINK PCIe NIC card on my PCIe Root Complex. Probing looks fine by setting: r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded PCI: enabling device :00:00.0 (0140 - 0143) PCI: enabling device

Re: [V5 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

On 12 November 2014 01:11, Graham Moore grmo...@opensource.altera.com wrote: On 11/05/2014 09:09 PM, bpqw wrote: This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced

Re: [PATCH 1/1 v3] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

On 27 October 2014 05:39, bpqw b...@micron.com wrote: This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When

read performance is too low compared to write - /dev/sda1

Hi, I'm doing a performance testing on my bench ARM box. 1. dd test: I have validate the read and write by mounting /dev/sda1 with ext4 filesystem, able to get the good performance numbers where read is high compared to write 2. robocopy test: - mkfs.ext4 /dev/sda1 - mount

Re: read performance is too low compared to write - /dev/sda1

, Jagan Teki jagannadh.t...@gmail.com wrote: Hi, I'm doing a performance testing on my bench ARM box. 1. dd test: I have validate the read and write by mounting /dev/sda1 with ext4 filesystem, able to get the good performance numbers where read is high compared to write 2. robocopy

ARM64 Crypto validation

Hi, I need some information to validate arm64/crypto, do we have any exact/defined way to validate this. Here are my findings: 1. I see a dirty test module tcrypto.c where we need to give the sec and mode module params as inputs. 2. Validate through open crypto [1] Do we have any arm64 specific

Re: read performance is too low compared to write - /dev/sda1

On 14 November 2014 19:22, Roger Heflin rogerhef...@gmail.com wrote: What kind of underlying disk is it? GEN3 Sata link, SSD from Samsung. On Fri, Nov 14, 2014 at 7:36 AM, Jagan Teki jagannadh.t...@gmail.com wrote: On 14 November 2014 18:50, Roger Heflin rogerhef...@gmail.com wrote: If you

[PATCH] staging: android: Add more help description on Kconfig

This patch adds more help description on android Kconfig for - lowmemory killer - Timed gpio (same for timed output) Signed-off-by: Jagan Teki jt...@openedev.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org Cc: Brian Swetland swetl...@google.com --- drivers/staging/android/Kconfig | 11

[PATCH v2] staging: rtl8712: Use ether_addr_copy() instead of memcpy()

with this change as well. staging: rtl8712: fix Prefer ether_addr_copy() over memcpy() (sha1: 36e4d8826b317080e283e4edd08bf8d5ac706f38) Signed-off-by: Jagan Teki jt...@openedev.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org Cc: Larry Finger larry.fin...@lwfinger.net Cc: Florian Schilhabel

[PATCH v3] staging: rtl8712: Use ether_addr_copy() instead of memcpy()

some patches with this change as well. staging: rtl8712: fix Prefer ether_addr_copy() over memcpy() (sha1: 36e4d8826b317080e283e4edd08bf8d5ac706f38) Signed-off-by: Jagan Teki jt...@openedev.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org Cc: Larry Finger larry.fin...@lwfinger.net Cc: Florian

[PATCH] staging: rtl8188eu: core: Fix line over 80 characters

This patch fixes line over 80 characters warninings while running checkpatch.pl - WARNING: line over 80 characters Signed-off-by: Jagan Teki jt...@openedev.com Cc: Greg Kroah-Hartman gre...@linux.com Cc: Larry Finger larry.fin...@lwfinger.net --- drivers/staging/rtl8188eu/core/rtw_ap.c | 52

Re: [PATCH v2] staging: rtl8712: Use ether_addr_copy() instead of memcpy()

On 18 May 2015 at 20:08, Dan Carpenter dan.carpen...@oracle.com wrote: On Mon, May 18, 2015 at 07:47:06PM +0530, Jagan Teki wrote: struct eeprom_priv { u8 bautoload_fail_flag; /* 0 1 */ u8 bempty; /* 1 1

[PATCH] block: Use BIT macro from include/linux/bitops.h

Replace (1 nr) to BIT(nr) where nr = 0, 1, 2 31 Signed-off-by: Jagan Teki jt...@openedev.com Cc: Wolfram Sang w...@the-dreams.de Cc: Jens Axboe ax...@kernel.dk --- drivers/block/mg_disk.c | 10 +- drivers/block/mtip32xx/mtip32xx.c | 14 +++--- drivers/block

[PATCH] staging: rtl8712: Use ether_addr_copy() instead of memcpy()

This patch fixes to use ether_addr_copy() instead of memcpy() Encounter this by applying checkpatch.pl against this file: WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2) Signed-off-by: Jagan Teki jt...@openedev.com Cc: Greg Kroah-Hartman gre

Re: [PATCH v3] staging: rtl8712: Use ether_addr_copy() instead of memcpy()

On 18 May 2015 at 22:02, Jagan Teki jt...@openedev.com wrote: Fixes Warning encounter this by applying checkpatch.pl against this file: Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2) pahole output for respective structures: - addr-sa_data struct sockaddr

[PATCH] dma-buf: Minor coding style fixes

- WARNING: Missing a blank line after declarations - WARNING: line over 80 characters - WARNING: please, no space before tabs Signed-off-by: Jagan Teki jt...@openedev.com Cc: Sumit Semwal sumit.sem...@linaro.org --- drivers/dma-buf/dma-buf.c | 9 +++-- drivers/dma-buf/reservation.c | 9

Re: [PATCH v3] staging: rtl8712: Use ether_addr_copy() instead of memcpy()

On 21 May 2015 at 01:10, Larry Finger larry.fin...@lwfinger.net wrote: On 05/20/2015 01:41 PM, Jagan Teki wrote: On 18 May 2015 at 22:02, Jagan Teki jt...@openedev.com wrote: Fixes Warning encounter this by applying checkpatch.pl against this file: Prefer ether_addr_copy() over memcpy

Re: [PATCH] block: Use BIT macro from include/linux/bitops.h

Ping! On 19 May 2015 at 00:44, Jagan Teki jt...@openedev.com wrote: Replace (1 nr) to BIT(nr) where nr = 0, 1, 2 31 Signed-off-by: Jagan Teki jt...@openedev.com Cc: Wolfram Sang w...@the-dreams.de Cc: Jens Axboe ax...@kernel.dk --- drivers/block/mg_disk.c | 10

Re: [PATCH] staging: rtl8188eu: core: Fix line over 80 characters

On 18 May 2015 at 22:34, Jagan Teki jt...@openedev.com wrote: This patch fixes line over 80 characters warninings while running checkpatch.pl - WARNING: line over 80 characters Signed-off-by: Jagan Teki jt...@openedev.com Cc: Greg Kroah-Hartman gre...@linux.com Cc: Larry Finger larry.fin

[PATCH 1/2] dma: omap-dma: Fix line over 80 characters

This patch fixes line over 80 characters warninings while running checkpatch.pl Signed-off-by: Jagan Teki jt...@openedev.com Cc: Dan Williams dan.j.willi...@intel.com Cc: Vinod Koul vinod.k...@intel.com --- drivers/dma/omap-dma.c | 18 -- 1 file changed, 12 insertions(+), 6

[PATCH 2/2] dma: amba-pl08x: Fix line over 80 characters

This patch fixes line over 80 characters warninings while running checkpatch.pl Signed-off-by: Jagan Teki jt...@openedev.com Cc: Dan Williams dan.j.willi...@intel.com Cc: Vinod Koul vinod.k...@intel.com --- drivers/dma/amba-pl08x.c | 13 + 1 file changed, 9 insertions(+), 4 deletions

Re: [PATCH] block: Use BIT macro from include/linux/bitops.h

On 21 May 2015 at 00:52, Jens Axboe ax...@kernel.dk wrote: On 05/18/2015 01:14 PM, Jagan Teki wrote: Replace (1 nr) to BIT(nr) where nr = 0, 1, 2 31 I don't like it, I think it hurts readability. What do you mean by don't like, using kernel defined macro instead of numerical

Re: [PATCH] block: Use BIT macro from include/linux/bitops.h

On 21 May 2015 at 01:13, Jens Axboe ax...@kernel.dk wrote: On 05/20/2015 01:41 PM, Jagan Teki wrote: On 21 May 2015 at 00:52, Jens Axboe ax...@kernel.dk wrote: On 05/18/2015 01:14 PM, Jagan Teki wrote: Replace (1 nr) to BIT(nr) where nr = 0, 1, 2 31 I don't like it, I think

Re: [PATCH 00/11] ARM64 PCI hostbridge init based on ACPI

On 27 May 2015 at 09:27, Hanjun Guo hanjun@linaro.org wrote: On 2015年05月27日 08:30, Rafael J. Wysocki wrote: On Tuesday, May 26, 2015 08:49:13 PM Hanjun Guo wrote: This patch set is introducing ARM64 PCI hostbridge init based on ACPI, which based on Jiang Liu's patch set Consolidate ACPI

Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

Hi Zhiqiang, On 19 August 2015 at 17:42, Hou Zhiqiang b48...@freescale.com wrote: Hi Jagan, -Original Message- From: Jagan Teki [mailto:jt...@openedev.com] Sent: 2015年8月19日 17:57 To: linux-...@lists.infradead.org Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286; Hu

Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

Hi Zhiqiang, On 20 August 2015 at 08:36, Hou Zhiqiang b48...@freescale.com wrote: Hello Jagan, -Original Message- From: Jagan Teki [mailto:jt...@openedev.com] Sent: 2015年8月20日 1:49 To: Hou Zhiqiang-B48286 Cc: linux-...@lists.infradead.org; Hu Mingkai-B21284; Brian Norris; David

[PATCH 1/3] mtd: spi-nor: Use write_sr for write status

Use existing write_sr() call instead of decoding and calling nor-write_reg separately. Signed-off-by: Jagan Teki jt...@openedev.com Cc: David Woodhouse dw...@infradead.org Cc: Brian Norris computersforpe...@gmail.com --- drivers/mtd/spi-nor/spi-nor.c | 3 +-- 1 file changed, 1 insertion(+), 2

[PATCH 2/3] mtd: spi-nor: Zap unneeded write_enable from write_reg

Since write enabling shall do with buf and len without need of exctra write_enable argument, hence removed the same from write_reg. Signed-off-by: Jagan Teki jt...@openedev.com Cc: David Woodhouse dw...@infradead.org Cc: Brian Norris computersforpe...@gmail.com Cc: Han Xu han...@freescale.com

[PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

The clear flag status register operation was required by Micron SPI-NOR chips, which support FSR. And if an error bit of FSR have been set like protection, voltage, erase, and program, it must be cleared by the clear FSR operation. Signed-off-by: Jagan Teki jt...@openedev.com Cc: Hou Zhiqiang b48

Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

On 27 August 2015 at 17:19, punnaiah choudary kalluri punn...@xilinx.com wrote: On Thu, Aug 27, 2015 at 3:45 PM, Jagan Teki jt...@openedev.com wrote: On 27 August 2015 at 14:18, punnaiah choudary kalluri punn...@xilinx.com wrote: On Thu, Aug 27, 2015 at 11:53 AM, Jagan Teki jt...@openedev.com

Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

Hi Zhiqiang, On 25 August 2015 at 07:52, Hou Zhiqiang b48...@freescale.com wrote: Hi Jagan, -Original Message- From: Jagan Teki [mailto:jt...@openedev.com] Sent: 2015年8月21日 15:12 To: Hou Zhiqiang-B48286 Cc: linux-...@lists.infradead.org; Hu Mingkai-B21284; Brian Norris; David

Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

On 26 August 2015 at 11:56, Ranjit Waghmode ranjit.waghm...@xilinx.com wrote: This series adds dual parallel mode support for Zynq Ultrascale+ MPSoC GQSPI controller driver. What is dual parallel mode? --- ZynqMP GQSPI controller supports Dual Parallel mode with

[PATCH v2 3/3] mtd: spi-nor: Add clear flag status register support

The clear flag status register operation is required by Micron SPI-NOR chips, which support FSR. And if error bits of FSR have been set like protection, voltage, erase, and program, it must be cleared by executing clear FSR operation. Signed-off-by: Jagan Teki jt...@openedev.com Cc: Hou Zhiqiang

Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

On 27 August 2015 at 14:18, punnaiah choudary kalluri punn...@xilinx.com wrote: On Thu, Aug 27, 2015 at 11:53 AM, Jagan Teki jt...@openedev.com wrote: On 26 August 2015 at 21:02, punnaiah choudary kalluri punn...@xilinx.com wrote: On Wed, Aug 26, 2015 at 5:49 PM, Jagan Teki jt...@openedev.com

Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

On 26 August 2015 at 21:02, punnaiah choudary kalluri punn...@xilinx.com wrote: On Wed, Aug 26, 2015 at 5:49 PM, Jagan Teki jt...@openedev.com wrote: On 26 August 2015 at 11:56, Ranjit Waghmode ranjit.waghm...@xilinx.com wrote: This series adds dual parallel mode support for Zynq Ultrascale

Re: [PATCH 2/3] mtd: spi-nor: Zap unneeded write_enable from write_reg

On 19 August 2015 at 15:26, Jagan Teki <jt...@openedev.com> wrote: > Since write enabling shall do with buf and len without > need of exctra write_enable argument, hence removed the > same from write_reg. > > Signed-off-by: Jagan Teki <jt...@openedev.com> > Cc: David

Re: [PATCH 1/3] mtd: spi-nor: Use write_sr for write status

On 19 August 2015 at 15:26, Jagan Teki <jt...@openedev.com> wrote: > Use existing write_sr() call instead of decoding and > calling nor->write_reg separately. > > Signed-off-by: Jagan Teki <jt...@openedev.com> > Cc: David Woodhouse <dw...@infradead.org>

Re: [PATCH 1/5] spi: introduce mmap read support for spi flash devices

On 4 September 2015 at 13:59, Vignesh R wrote: > In addition to providing direct access to SPI bus, some spi controller > hardwares (like ti-qspi) provide special memory mapped port > to accesses SPI flash devices in order to increase read performance. > This means the controller

Re: [PATCH 1/3] doc: dt: add documentation for Mediatek spi-nor controller

On 8 September 2015 at 15:19, Bayi Cheng wrote: > Add device tree binding documentation for serial flash with > Mediatek serial flash controller > > Signed-off-by: Bayi Cheng > --- > Documentation/devicetree/bindings/mtd/mtk_nor.txt | 25 >

Re: [PATCH 3/3] arm64: dts: mt8173: Add nor flash node

On 8 September 2015 at 15:19, Bayi Cheng wrote: > Add Mediatek nor flash node > > Signed-off-by: Bayi Cheng > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git

Re: [PATCH v2 3/3] mtd: spi-nor: Add clear flag status register support

On 26 August 2015 at 16:18, Jagan Teki <jt...@openedev.com> wrote: > The clear flag status register operation is required by Micron > SPI-NOR chips, which support FSR. And if error bits of FSR > have been set like protection, voltage, erase, and program, > it must be cleared by e

Re: [PATCH 1/5] spi: introduce mmap read support for spi flash devices

On 15 September 2015 at 00:05, Mark Brown <broo...@kernel.org> wrote: > On Fri, Sep 04, 2015 at 04:55:33PM +0530, Jagan Teki wrote: >> On 4 September 2015 at 13:59, Vignesh R <vigne...@ti.com> wrote: > >> > + * @spi_mtd_mmap_read: some spi-co

Re: [linux-next RFC v7 2/6] mtd: spi-nor: read JEDEC ID with multiple I/O protocols

On 15 September 2015 at 20:58, Cyrille Pitchen wrote: > When their quad or dual I/O mode is enabled, Micron and Macronix spi-nor > memories don't reply to the regular Read ID (0x9f) command. Instead they > reply to a new dedicated command Read ID Multiple I/O (0xaf). >

Re: [PATCH v2 3/3] mtd: spi-nor: Add clear flag status register support

On 1 September 2015 at 21:40, Jagan Teki <jt...@openedev.com> wrote: > On 26 August 2015 at 16:18, Jagan Teki <jt...@openedev.com> wrote: >> The clear flag status register operation is required by Micron >> SPI-NOR chips, which support FSR. And if error bits of FSR >&

Re: [PATCH v8] mtd: spi-nor: add hisilicon spi-nor flash controller driver

On Friday 11 March 2016 01:11 PM, Jiancheng Xue wrote: Add hisilicon spi-nor flash controller driver Signed-off-by: Binquan Peng Signed-off-by: Jiancheng Xue Acked-by: Rob Herring Reviewed-by: Ezequiel Garcia

Re: [PATCH v9] mtd: spi-nor: add hisilicon spi-nor flash controller driver

ring <r...@kernel.org> > Reviewed-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar> > --- Reviewed-by: Jagan Teki <jt...@openedev.com> -- Jagan.

[PATCH] mtd: spi-nor: Add at25df321 spi-nor flash support

Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids. Cc: Brian Norris <computersforpe...@gmail.com> Cc: Wenyou Yang <wenyou.y...@atmel.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+) diff -

Re: [PATCH v2] mtd: spi-nor: Add support for N25Q016A

On 15 July 2016 at 22:33, Moritz Fischer <moritz.fisc...@ettus.com> wrote: > This commit adds support in the spi-nor driver for the > N25Q016A, a 16Mbit SPI NOR flash from Micron. > > Cc: David Woodhouse <dw...@infradead.org> > Cc: Brian Norris <computersforpe...@g

Re: [PATCH v2 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash

On 22 April 2016 at 12:09, Yunhui Cui wrote: > From: Yunhui Cui > > With the physical sectors combination, S25FS-S family flash > requires some special operations for read/write functions. > > Signed-off-by: Yunhui Cui > --- >

[PATCH] mtd: spi-nor: Add s25fs256s1 spi-nor flash support

these family parts again and do two different erase operations. Cc: Brian Norris <computersforpe...@gmail.com> Cc: Yunhui Cui <yunhui@nxp.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor/spi-nor.c

[PATCH v2] mtd: spi-nor: Add s25fs256s1 spi-nor flash support

these family parts again and do two different erase operations. Cc: Brian Norris <computersforpe...@gmail.com> Cc: Yunhui Cui <yunhui@nxp.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- Changes for v2:

[PATCH 6/6] mtd: spi-nor: Enable QPP for winbond parts

Enable QPP support for winbond flash parts. Cc: Brian Norris <computersforpe...@gmail.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor/spi-nor.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor

[PATCH 5/6] mtd: spi-nor: Enable QPP for spansion parts

Enable QPP support for spansion flash parts. Cc: Brian Norris <computersforpe...@gmail.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor/spi-nor.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-n

[PATCH 1/6] mtd: spi-nor: Add quad page program support

Add quad page program support with the use of nor->flags and then controller will use 4 lines for data transmission which is quite faster than page program(02h) Cc: Brian Norris <computersforpe...@gmail.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor

[PATCH 2/6] mtd: m25p80: Use spi-nor quad page program

Identify the 4-wire tx transfer from spi controller mode value and then assign QPP support to nor->flags to make use of that. Cc: Brian Norris <computersforpe...@gmail.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/devices/m25p80.c | 2 ++ 1 file change

[PATCH 3/6] mtd: spi-nor: Enable QPP for macronix parts

Enable QPP support for micronix flash parts. Cc: Brian Norris <computersforpe...@gmail.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor/spi-nor.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor

[PATCH 4/6] mtd: spi-nor: Enable QPP for micron parts

Enable QPP support for micron flash parts. Cc: Brian Norris <computersforpe...@gmail.com> Signed-off-by: Jagan Teki <jt...@openedev.com> --- drivers/mtd/spi-nor/spi-nor.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor

[PATCH 0/6] mtd: spi-nor: Add QPP support

This series adding support for 4-wire quad page program(32h) for supported flash chips. Jagan Teki (6): mtd: spi-nor: Add quad page program support mtd: m25p80: Use spi-nor quad page program mtd: spi-nor: Enable QPP for macronix parts mtd: spi-nor: Enable QPP for micron parts mtd: spi

Re: [PATCH v2 1/3] spi-nor: Add support for Intel SPI serial flash controller

ootable. > + > + To compile this driver as a module, choose M here: the module > + will be called intel-spi-platform. > + > endif # MTD_SPI_NOR > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile > index 0bf3a7f81675..60c0b1bb8264 100644 > --- a/dr

Re: [PATCH v2 2/3] ARM: dts: imx6ul: Add Engicam Is.IoT MX6UL eMMC initial support

On Monday 23 January 2017 10:47 AM, Shawn Guo wrote: On Fri, Jan 20, 2017 at 12:09:34AM +0100, Jagan Teki wrote: From: Jagan Teki <ja...@amarulasolutions.com> Engicam Is.IoT MX6UL has separate module for eMMC, so add emmc dts file for imx6ul-isiot.dtsi, usdhc2 node represent eMMC.

[PATCH v2 2/4] arm: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual OpenFrame Cap 10.1 initial support

From: Jagan Teki <ja...@amarulasolutions.com> i.CoreM6 Quad/Dual OpenFrame modules are "system on modules plus openframe display carriers" which are good solution for develop user friendly graphic user interface. General features: CPU NXP i.MX6Q rev1.2 at 792 MHz RAM

[PATCH v2 3/4] arm: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual OpenFrame Cap 12.3 initial support

ions.com> Cc: Shawn Guo <shawn...@kernel.org> Signed-off-by: Jagan Teki <ja...@openedev.com> --- Changes for v2: - newly added patch arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/imx6q-icore-ofcap12.dts | 76 +++ 2 files changed, 77 in

[PATCH v2 1/4] arm: dts: imx6qdl-icore: Add backlight support for lvds

From: Jagan Teki <ja...@amarulasolutions.com> This patch add support for lvds backlight on i.CoreM6 QDL variant boards. Cc: Domenico Acri <domenico.a...@engicam.com> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Cc: Shawn

[PATCH v2 4/4] arm: dts: imx6q-icore: Add LVDS support

: Shawn Guo <shawn...@kernel.org> Signed-off-by: Jagan Teki <ja...@openedev.com> --- Changes for v2: - newly added patch arch/arm/boot/dts/imx6q-icore.dts | 25 + 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts

[PATCH v3 4/4] arm: dts: imx6q-icore: Add LVDS support

From: Jagan Teki <ja...@amarulasolutions.com> Add LVDS display support for OpenFrame Capacitive touch 7 inc display which is supported by Engicam i.CoreM6 QDL Starter Kit. Cc: Domenico Acri <domenico.a...@engicam.com> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Micha

[PATCH v3 3/4] arm: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual OpenFrame Cap 12.3 initial support

From: Jagan Teki <ja...@amarulasolutions.com> i.CoreM6 Quad/Dual OpenFrame modules are "system on modules plus openframe display carriers" which are good solution for develop user friendly graphic user interface. General features: CPU NXP i.MX6Q rev1.2 at 792 MHz RAM

[PATCH v3 1/4] arm: dts: imx6qdl-icore: Add backlight support for lvds

From: Jagan Teki <ja...@amarulasolutions.com> This patch add support for lvds backlight on i.CoreM6 QDL variant boards. Cc: Domenico Acri <domenico.a...@engicam.com> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Cc: Shawn

[PATCH v3 2/4] arm: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual OpenFrame Cap 10.1 initial support

From: Jagan Teki <ja...@amarulasolutions.com> i.CoreM6 Quad/Dual OpenFrame modules are "system on modules plus openframe display carriers" which are good solution for develop user friendly graphic user interface. General features: CPU NXP i.MX6Q rev1.2 at 792 MHz RAM

[PATCH 2/2] arm: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual OpenFrame Cap 10.1 initial support

From: Jagan Teki <ja...@amarulasolutions.com> i.CoreM6 Quad/Dual OpenFrame modules are "system on modules plus openframe display carriers" which are good solution for develop user friendly graphic user interface. General features: CPU NXP i.MX6Q rev1.2 at 792 MHz RAM

[PATCH 1/2] arm: dts: imx6qdl-icore: Add backlight support for lvds

From: Jagan Teki <ja...@amarulasolutions.com> This patch add support for lvds backlight on i.CoreM6 QDL variant boards. Cc: Domenico Acri <domenico.a...@engicam.com> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Cc: Shawn

[PATCH 2/2] ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible"

From: Jagan Teki <ja...@amarulasolutions.com> Fixed code indent tabs in respetcive imx6qdl dtsi files and also add space on imx6qdl-icore-rqs.dtsi on usdhc bus-width nodes. Cc: Shawn Guo <shawn...@kernel.org> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- arch/ar

[PATCH 1/2] ARM: dts: imx6ul-isiot: Add eMMC node

From: Jagan Teki <ja...@amarulasolutions.com> Add usdhc2 node, which is eMMC for Engicam Is.IoT MX6UL modules. dmesg: - mmc1: SDHCI controller on 2194000.usdhc [2194000.usdhc] using ADMA mmc1: new DDR MMC card at address 0001 mmcblk1: mmc1:0001 M62704 3.53 GiB Cc: Matteo Lisi <

[PATCH v2 2/3] ARM: dts: imx6ul: Add Engicam Is.IoT MX6UL eMMC initial support

From: Jagan Teki <ja...@amarulasolutions.com> Engicam Is.IoT MX6UL has separate module for eMMC, so add emmc dts file for imx6ul-isiot.dtsi, usdhc2 node represent eMMC. dmesg: - mmc1: SDHCI controller on 2194000.usdhc [2194000.usdhc] using ADMA mmc1: new DDR MMC card at address 0001 m

[PATCH v2 1/3] ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible"

From: Jagan Teki <ja...@amarulasolutions.com> Fixed code indent tabs in respetcive imx6qdl dtsi files and also add space on imx6qdl-icore-rqs.dtsi on usdhc bus-width nodes. Cc: Shawn Guo <shawn...@kernel.org> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- Chan

[PATCH v2 3/3] ARM: dts: imx6ul: Add Engicam Is.IoT MX6UL NAND initial support

From: Jagan Teki <ja...@amarulasolutions.com> Engicam Is.IoT MX6UL has separate module for NAND, so add nand dts file for imx6ul-isiot.dtsi. dmesg: - nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda nand: Micron MT29F2G08ABAEAH4 nand: 256 MiB, SLC, erase size: 128 KiB, pag

[PATCH v4] ARM: dts: imx6ul-geam: Add Engicam IMX6UL GEA M6UL initial support

<matteo.l...@engicam.com> Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- Changes for v4: - Fix comments from 'Shawn Guo' - Fix new blank line at EOF arch/arm/boot/dts/imx6ul-geam-kit.dts Changes for

[PATCH v3] ARM: dts: imx6ul-geam: Add Engicam IMX6UL GEA M6UL initial support

<matteo.l...@engicam.com> Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- Changes for v3: - Rebase on master - Replace flexcan1 and flexcan2 with can1 and can2 - Fix to use RAM size as 128MB instead of

[PATCH v4 3/5] ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support

://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Sascha Hauer <ker...@pengutronix.de> Cc: Fabio Estevam <fabio.este...@nxp.com> Cc: Shawn Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com

[PATCH v4 0/5] ARM: dts: imx6q: Add Engicam i.CoreM6 dts

This is series add dts support for Engicam I.Core M6 qdl modules. Jagan Teki (5): of: Add vendor prefix for Engicam s.r.l company ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support ARM: dts: imx6qdl-icore

[PATCH v4 2/5] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Sascha Hauer <ker...@pengutronix.de> Cc: Fabio Estevam <fabio.este...@nxp.com> Cc: Shawn Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com>

[PATCH v4 1/5] of: Add vendor prefix for Engicam s.r.l company

n Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- Changes for v4: - none Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file

[PATCH v4 5/5] ARM: dts: imx6qdl-icore: Add usbotg support

Add usbotg support for Engicam i.CoreM6 dql modules. Cc: Sascha Hauer <ker...@pengutronix.de> Cc: Fabio Estevam <fabio.este...@nxp.com> Cc: Shawn Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com>

[PATCH v4 4/5] ARM: dts: imx6qdl-icore: Add usbhost support

Add usbhost support for Engicam i.CoreM6 dql modules. Cc: Sascha Hauer <ker...@pengutronix.de> Cc: Fabio Estevam <fabio.este...@nxp.com> Cc: Shawn Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com>

Re: [PATCH v4 2/5] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

On Wed, Sep 14, 2016 at 4:06 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Sun, Sep 11, 2016 at 3:30 PM, Jagan Teki <jagannadh.t...@gmail.com> wrote: > >> + reg_3p3v: regulator-3p3v { >> + compatible = "regulator-fixed"; &

Re: [PATCH v3 2/3] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

On Sat, Sep 10, 2016 at 3:49 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Fri, Sep 9, 2016 at 7:19 PM, Fabio Estevam <feste...@gmail.com> wrote: >> On Fri, Sep 9, 2016 at 7:14 PM, Jagan Teki <ja...@amarulasolutions.com> >> wrote: >> >>>>

Re: [PATCH v3 2/3] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

On Sat, Sep 10, 2016 at 3:55 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Fri, Sep 9, 2016 at 7:21 PM, Jagan Teki <ja...@amarulasolutions.com> wrote: > >> Why? can't we update iomux reg value any side effects or something. > > Sure you can change it. > > Y

Re: [PATCH v3 2/3] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

On Sat, Sep 10, 2016 at 3:29 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Fri, Sep 9, 2016 at 6:45 PM, Jagan Teki <jagannadh.t...@gmail.com> wrote: > >> + { >> + pinctrl_flexcan1: flexcan1grp { >> + fsl,pins = < >> +

Re: [PATCH v3 2/3] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

On Sat, Sep 10, 2016 at 3:33 AM, Jagan Teki <ja...@amarulasolutions.com> wrote: > On Sat, Sep 10, 2016 at 3:29 AM, Fabio Estevam <feste...@gmail.com> wrote: >> On Fri, Sep 9, 2016 at 6:45 PM, Jagan Teki <jagannadh.t...@gmail.com> wrote: >> >>> + {

[PATCH v5 6/6] ARM: dts: imx6qdl-icore: Add FEC support

/patch/3490511/ Cc: Sascha Hauer <ker...@pengutronix.de> Cc: Fabio Estevam <fabio.este...@nxp.com> Cc: Shawn Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <ja...@amarula

[PATCH v5 0/6] ARM: dts: imx6q: Add Engicam i.CoreM6 dts

This is series add dts support for Engicam I.Core M6 qdl modules. Jagan Teki (6): of: Add vendor prefix for Engicam s.r.l company ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support ARM: dts: imx6qdl-icore

[PATCH v5 3/6] ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support

://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Sascha Hauer <ker...@pengutronix.de> Cc: Fabio Estevam <fabio.este...@nxp.com> Cc: Shawn Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com

[PATCH v5 1/6] of: Add vendor prefix for Engicam s.r.l company

n Guo <shawn...@kernel.org> Cc: Matteo Lisi <matteo.l...@engicam.com> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- Changes for v5: - none Changes for v4: - new patch Documentation/devicetree/bindin

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