On Wed, Apr 10, 2013 at 09:44:52AM +0100, Lukasz Majewski wrote:
[...]
Have you also looked at the power clamp driver that have similar
target ?
I might be wrong here, but in my opinion the power clamp driver is a bit
different:
1. It is dedicated to Intel SoCs, which provide special
the check
in the idle thread before entering idle ? It does not hurt, agreed, and we'd
better leave it there, it is just for my own understanding, thanks a lot.
Having said that, on the series:
Tested-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
+ dev-next_event.tv64 bc
Hi Jason,
On Thu, Feb 21, 2013 at 06:16:51AM +, Jason Liu wrote:
2013/2/20 Thomas Gleixner t...@linutronix.de:
On Wed, 20 Feb 2013, Jason Liu wrote:
void arch_idle(void)
{
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, cpu);
enter_the_wait_mode();
one.
They are always welcome.
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
You can add mine too, we should fix the WARN_ON_ONCE mentioned in Santosh's
reply.
Tested-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux
On Fri, Feb 22, 2013 at 10:24:00AM +, Thomas Gleixner wrote:
On Fri, 22 Feb 2013, Santosh Shilimkar wrote:
BTW, Lorenzo off-list mentioned to me about warning in boot-up
which I missed while testing your patch. It will take bit more
time for me to look into it and hence thought of
On Fri, Feb 22, 2013 at 12:07:30PM +, Thomas Gleixner wrote:
On Fri, 22 Feb 2013, Santosh Shilimkar wrote:
On Friday 22 February 2013 04:01 PM, Lorenzo Pieralisi wrote:
On Fri, Feb 22, 2013 at 10:24:00AM +, Thomas Gleixner wrote:
On Fri, 22 Feb 2013, Santosh Shilimkar wrote
On Fri, Feb 22, 2013 at 03:03:02PM +, Thomas Gleixner wrote:
On Fri, 22 Feb 2013, Lorenzo Pieralisi wrote:
On Fri, Feb 22, 2013 at 12:07:30PM +, Thomas Gleixner wrote:
Now we could make use of that and avoid going deep idle just to come
back right away via the IPI. Unfortunately
On Fri, Feb 22, 2013 at 06:52:14PM +, Thomas Gleixner wrote:
On Fri, 22 Feb 2013, Lorenzo Pieralisi wrote:
On Fri, Feb 22, 2013 at 03:03:02PM +, Thomas Gleixner wrote:
On Fri, 22 Feb 2013, Lorenzo Pieralisi wrote:
On Fri, Feb 22, 2013 at 12:07:30PM +, Thomas Gleixner wrote
On Wed, Sep 12, 2012 at 08:43:33AM +0100, Shilimkar, Santosh wrote:
+ Lorenzo,
On Wed, Sep 12, 2012 at 12:48 PM, wzch w...@marvell.com wrote:
From: Wenzeng Chen w...@marvell.com
In cpu suspend function __cpu_suspend_save(), we save cp15 registers,
resume function, sp and suspend_pgd,
On Fri, Sep 28, 2012 at 04:57:46PM +0100, Dave Martin wrote:
[ Note: please aim to CC devicetree-disc...@lists.ozlabs.org with any
patches or bindings relevant to device tree. ]
[ Lorenzo, there's a question for you further down this mail. ]
[...]
+ If using the memory mapped
On Tue, Oct 02, 2012 at 12:27:04PM +0100, Dave Martin wrote:
On Fri, Sep 28, 2012 at 06:15:53PM +0100, Lorenzo Pieralisi wrote:
On Fri, Sep 28, 2012 at 04:57:46PM +0100, Dave Martin wrote:
[...]
There must be a common way for all devices to link to the topology, though.
The topology
On Mon, Jul 29, 2013 at 02:12:58PM +0100, Arjan van de Ven wrote:
The menu governor tries to deduce the next wakeup but based on events
per cpu. That means if a task with a specific behavior is migrated
across cpus, the statistics will be wrong.
btw this is largely a misunderstanding;
On Mon, Jul 29, 2013 at 03:29:20PM +0100, Arjan van de Ven wrote:
On 7/29/2013 7:14 AM, Lorenzo Pieralisi wrote:
btw this is largely a misunderstanding;
tasks are not the issue; tasks use timers and those are perfectly
predictable.
It's interrupts that are not and the heuristics
On Mon, Jul 29, 2013 at 02:36:30PM +0100, Dave Martin wrote:
On Mon, Jul 29, 2013 at 10:54:01AM +0100, Will Deacon wrote:
On Mon, Jul 29, 2013 at 10:46:06AM +0100, Vincent Guittot wrote:
On 27 July 2013 12:42, Hanjun Guo hanjun@linaro.org wrote:
Power aware scheduling needs the cpu
Hi Olof,
thanks a lot.
On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides
the
interface between the dual cluster test-chip and the M3
On Tue, Jun 18, 2013 at 05:25:22AM +0100, Nicolas Pitre wrote:
On Mon, 17 Jun 2013, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides
the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power
On Wed, Jun 19, 2013 at 01:50:57PM +0100, Tomasz Figa wrote:
On Wednesday 19 of June 2013 17:39:21 Chander Kashyap wrote:
On 18 June 2013 23:29, Kukjin Kim kgene@samsung.com wrote:
On 06/19/13 02:45, Tomasz Figa wrote:
Ccing Arnd and Olof, because I forgot to add them to git
sections warning
- Fixed two minor bugs
Lorenzo Pieralisi (1):
drivers: mfd: vexpress: add Serial Power Controller (SPC) support
Documentation/devicetree/bindings/mfd/vexpress-spc.txt | 36 ++
drivers/mfd/Kconfig| 10 +
drivers/mfd/Makefile
Johansson o...@lixom.net
Cc: Pawel Moll pawel.m...@arm.com
Cc: Amit Kucheria amit.kuche...@linaro.org
Cc: Jon Medhurst t...@linaro.org
Signed-off-by: Achin Gupta achin.gu...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage
On Wed, Jul 17, 2013 at 10:18:25AM +0100, Pawel Moll wrote:
On Tue, 2013-07-16 at 17:05 +0100, Lorenzo Pieralisi wrote:
/drivers/mfd is probably not the right place for this code as it stands (but
probably will be when the entire driver, with DVFS and config interface, is
complete
Hi Samuel,
On Wed, Jul 17, 2013 at 10:07:00PM +0100, Samuel Ortiz wrote:
Hi Lorenzo,
On Tue, Jul 16, 2013 at 05:05:42PM +0100, Lorenzo Pieralisi wrote:
Hello,
version v5 of VExpress SPC driver, please read on the changelog for major
changes and explanations.
The probing scheme
On Mon, Sep 09, 2013 at 06:22:16PM +0100, Kevin Hilman wrote:
On Mon, Sep 2, 2013 at 11:09 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Thu, Aug 29, 2013 at 06:57:15PM +0100, Olof Johansson wrote:
On Thu, Aug 29, 2013 at 06:04:25PM +1000, Stephen Rothwell wrote:
Hi all
On Sat, Feb 22, 2014 at 10:38:40AM +, Russell King - ARM Linux wrote:
On Wed, Feb 19, 2014 at 04:12:54PM +, Lorenzo Pieralisi wrote:
On Wed, Feb 19, 2014 at 01:52:09AM +, Sebastian Capella wrote:
+/*
+ * Snapshot kernel memory and reset the system.
+ * After resume
On Sat, Feb 22, 2014 at 10:16:55AM +, Russell King - ARM Linux wrote:
On Thu, Feb 20, 2014 at 04:27:55PM +, Lorenzo Pieralisi wrote:
I still do not understand why switching to idmap, which is a clone of
init_mm + 1:1 kernel mappings is required here. Why idmap ?
And while
Hi Stephen,
On Wed, Feb 19, 2014 at 12:20:43AM +, Stephen Boyd wrote:
(Sorry, this discussion stalled due to merge window + life events)
Sorry for the delay in replying on my side too.
On 01/17, Lorenzo Pieralisi wrote:
On Thu, Jan 16, 2014 at 07:26:17PM +, Stephen Boyd wrote
On Sun, Feb 23, 2014 at 08:02:08PM +, Sebastian Capella wrote:
Quoting Lorenzo Pieralisi (2014-02-22 04:09:10)
On Sat, Feb 22, 2014 at 10:38:40AM +, Russell King - ARM Linux wrote:
On Wed, Feb 19, 2014 at 04:12:54PM +, Lorenzo Pieralisi wrote:
On Wed, Feb 19, 2014 at 01:52
On Tue, Feb 25, 2014 at 05:55:31PM +, Sebastian Capella wrote:
Quoting Lorenzo Pieralisi (2014-02-25 03:32:51)
On Sun, Feb 23, 2014 at 08:02:08PM +, Sebastian Capella wrote:
I'll go with leaving the soft_restart as is unless someone feels
strongly against.
Leaving
On Tue, Feb 25, 2014 at 08:48:38PM +, Kumar Gala wrote:
On Feb 25, 2014, at 5:16 AM, Lorenzo Pieralisi lorenzo.pieral...@arm.com
wrote:
Hi Stephen,
On Wed, Feb 19, 2014 at 12:20:43AM +, Stephen Boyd wrote:
(Sorry, this discussion stalled due to merge window + life events
On Wed, Feb 26, 2014 at 05:50:55PM +, Sebastian Capella wrote:
Quoting Lorenzo Pieralisi (2014-02-26 02:24:27)
On Tue, Feb 25, 2014 at 05:55:31PM +, Sebastian Capella wrote:
Please add:
swsusp_save() is executed in the suspend finisher so that the CPU context
pointer
On Thu, Feb 27, 2014 at 11:57:58PM +, Sebastian Capella wrote:
[...]
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
new file mode 100644
index 000..a41e0e3
--- /dev/null
+++ b/arch/arm/kernel/hibernate.c
@@ -0,0 +1,113 @@
+/*
+ * Hibernation support
On Fri, Feb 28, 2014 at 08:15:57PM +, Sebastian Capella wrote:
[...]
+
+/*
+ * The framework loads the hibernation image into a linked list anchored
+ * at restore_pblist, for swsusp_arch_resume() to copy back to the proper
+ * destinations.
+ *
+ * To make this work if
On Tue, Mar 04, 2014 at 09:55:31AM +, Sebastian Capella wrote:
Quoting Sebastian Capella (2014-02-28 15:38:54)
Quoting Lorenzo Pieralisi (2014-02-28 14:49:33)
On Fri, Feb 28, 2014 at 08:15:57PM +, Sebastian Capella wrote:
This does not guarantee your stack is 8-byte
[CC'in BenH and Grant to check how this is handled in powerPC]
On Thu, Mar 06, 2014 at 10:00:10AM +, Ben Dooks wrote:
On 05/03/14 20:33, Stephen Boyd wrote:
+Lorenzo
On 02/24/14 03:22, Jürg Billeter wrote:
Skip 'disabled' cpu nodes when building the cpu logical map. This avoids
On Fri, Mar 07, 2014 at 11:08:56PM +, Stephen Boyd wrote:
On 02/26, Lorenzo Pieralisi wrote:
On Tue, Feb 25, 2014 at 08:48:38PM +, Kumar Gala wrote:
On Feb 25, 2014, at 5:16 AM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
As I mentioned, I do not like the idea
On Thu, Jan 09, 2014 at 08:52:21PM +, Stephen Boyd wrote:
On 01/08/14 02:05, Lorenzo Pieralisi wrote:
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
I have a problem with the cache level definition, and in
particular the numbering
On Wed, Feb 19, 2014 at 01:52:09AM +, Sebastian Capella wrote:
[...]
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
new file mode 100644
index 000..16f406f
--- /dev/null
+++ b/arch/arm/kernel/hibernate.c
@@ -0,0 +1,106 @@
+/*
+ * Hibernation support
On Wed, Feb 19, 2014 at 07:10:31PM +, Russ Dill wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 02/19/2014 08:12 AM, Lorenzo Pieralisi wrote:
+ * https://patchwork.kernel.org/patch/96442/
I am guessing the snippets of code your comments refer to.
I think the idea here
Hi Sebastian,
On Wed, Feb 19, 2014 at 07:33:15PM +, Sebastian Capella wrote:
Quoting Lorenzo Pieralisi (2014-02-19 08:12:54)
On Wed, Feb 19, 2014 at 01:52:09AM +, Sebastian Capella wrote:
[...]
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
new file mode
On Mon, Feb 03, 2014 at 04:17:47PM +, Arjan van de Ven wrote:
[...]
1) A latency driven one
2) A performance impact on
first one is pretty much the exit latency related time, sort of a
expected time to first instruction (currently menuidle has the
99.999% worst case number, which
On Wed, Feb 12, 2014 at 04:14:38PM +, Arjan van de Ven wrote:
sched_cpu_cache_wiped(int llc)
that would be very nice for this; the menuidle side knows this
for some cases and thus can just call it. This would be a very
small and minimal change
What do you mean by menuidle side
On Fri, Jun 07, 2013 at 03:20:20PM +0100, Rob Herring wrote:
On 06/07/2013 05:23 AM, Lorenzo Pieralisi wrote:
Hi James,
On Thu, Jun 06, 2013 at 06:11:25PM +0100, James King wrote:
If CPUs are marked as disabled in the devicetree, make sure they do
not exist in the system CPU
On Fri, Jun 07, 2013 at 12:48:58PM +0100, James King wrote:
Hi Lorenzo,
On 7 June 2013 11:23, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
Hi James,
On Thu, Jun 06, 2013 at 06:11:25PM +0100, James King wrote:
If CPUs are marked as disabled in the devicetree, make sure they do
management back-ends, your ack
would be appreciated, if you think it is worth it of course.
Thank you very much indeed,
Lorenzo
On Thu, Jun 06, 2013 at 10:59:21AM +0100, Lorenzo Pieralisi wrote:
This patch is v3 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June
:23AM +0100, Lorenzo Pieralisi wrote:
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d54e985..391eda1 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1148,3 +1148,10 @@ config VEXPRESS_CONFIG
help
Platform configuration infrastructure for the ARM
these days.
Please find a shorter suitable prefix than vexpress_spc_.* too, it's
way too long.
Ok.
On Thu, Jun 06, 2013 at 10:59:23AM +0100, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides
the
interface between the dual cluster test
to comply with the
Versatile Express config API, second patch is the SPC driver implementation.
Code extensively exercised through CPUidle and CPUfreq power states and
operating point transitions.
Lorenzo Pieralisi (1):
drivers: mfd: vexpress: add Serial Power Controller (SPC) support
Pawel Moll (1
...@lixom.net
Cc: Pawel Moll pawel.m...@arm.com
Cc: Amit Kucheria amit.kuche...@linaro.org
Cc: Jon Medhurst t...@linaro.org
Signed-off-by: Achin Gupta achin.gu...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Reviewed
From: Pawel Moll pawel.m...@arm.com
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates
: Nicolas Pitre nicolas.pi...@linaro.org
Cc: Amit Kucheria amit.kuche...@linaro.org
Cc: Jon Medhurst t...@linaro.org
Signed-off-by: Achin Gupta achin.gu...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
From: Pawel Moll pawel.m...@arm.com
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates
and
operating point transitions.
Lorenzo Pieralisi (1):
drivers: mfd: vexpress: add Serial Power Controller (SPC) support
Pawel Moll (1):
drivers: mfd: refactor the vexpress config bridge API
.../devicetree/bindings/mfd/vexpress-spc.txt | 35 ++
drivers/mfd/Kconfig
On Wed, Jun 05, 2013 at 07:08:33PM +0100, Jon Medhurst (Tixy) wrote:
On Wed, 2013-06-05 at 12:46 +0100, Lorenzo Pieralisi wrote:
[...]
+static const struct of_device_id vexpress_spc_ids[] __initconst = {
+ { .compatible = arm,vexpress-spc,v2p-ca15_a7 },
+ { .compatible = arm,vexpress
From: Pawel Moll pawel.m...@arm.com
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates
: Nicolas Pitre nicolas.pi...@linaro.org
Cc: Amit Kucheria amit.kuche...@linaro.org
Cc: Jon Medhurst t...@linaro.org
Signed-off-by: Achin Gupta achin.gu...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Reviewed
implementation.
Code extensively exercised through CPUidle and CPUfreq power states and
operating point transitions.
Lorenzo Pieralisi (1):
drivers: mfd: vexpress: add Serial Power Controller (SPC) support
Pawel Moll (1):
drivers: mfd: refactor the vexpress config bridge API
Documentation
Hi James,
On Thu, Jun 06, 2013 at 06:11:25PM +0100, James King wrote:
If CPUs are marked as disabled in the devicetree, make sure they do
not exist in the system CPU information and CPU topology information.
In this case these CPUs will not be able to be added to the system later
using
Hi Stephen,
On Wed, Jun 26, 2013 at 02:04:11AM +0100, Stephen Rothwell wrote:
Hi Lorenzo,
Today's linux-next merge of the arm-mpidr tree got a conflict in
arch/arm/kernel/suspend.c between commit 7604537bbb57 (ARM: kernel:
implement stack pointer save array through MPIDR hashing) from the
On Mon, Jun 03, 2013 at 11:15:32AM +0100, Jon Medhurst (Tixy) wrote:
On Fri, 2013-05-24 at 13:53 +0100, Lorenzo Pieralisi wrote:
In case some transactions to the Serial Power Controller (SPC) are lost
owing
to multiple operations handled at once by the M3 controller the OS needs to
rely
On Mon, Jun 03, 2013 at 01:03:50PM +0100, Jon Medhurst (Tixy) wrote:
On Mon, 2013-06-03 at 12:52 +0100, Lorenzo Pieralisi wrote:
On Mon, Jun 03, 2013 at 11:15:32AM +0100, Jon Medhurst (Tixy) wrote:
On Fri, 2013-05-24 at 13:53 +0100, Lorenzo Pieralisi wrote:
In case some transactions
patches provide changes required by SPC to comply with the
Versatile Express config API, third patch is the SPC driver implementation.
Code extensively exercised through CPUidle and CPUfreq power states and
operating point transitions.
Lorenzo Pieralisi (2):
drivers: mfd: vexpress: add timeout API
From: Pawel Moll pawel.m...@arm.com
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates
pawel.m...@arm.com
Cc: Nicolas Pitre nicolas.pi...@linaro.org
Cc: Amit Kucheria amit.kuche...@linaro.org
Cc: Jon Medhurst t...@linaro.org
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
---
drivers/mfd/vexpress-config.c | 26 +++---
include/linux/vexpress.h | 23 ++--
2 files
: Nicolas Pitre nicolas.pi...@linaro.org
Cc: Amit Kucheria amit.kuche...@linaro.org
Cc: Jon Medhurst t...@linaro.org
Signed-off-by: Achin Gupta achin.gu...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
On Wed, Aug 28, 2013 at 08:46:38PM +0100, Grant Likely wrote:
On Thu, 22 Aug 2013 14:59:30 +0100, Mark Rutland mark.rutl...@arm.com wrote:
On Mon, Aug 19, 2013 at 02:56:10PM +0100, Sudeep KarkadaNagesha wrote:
On 19/08/13 14:02, Rob Herring wrote:
On 08/19/2013 05:19 AM, Mark Rutland
On Thu, Aug 29, 2013 at 06:57:15PM +0100, Olof Johansson wrote:
On Thu, Aug 29, 2013 at 06:04:25PM +1000, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the arm-soc tree got a conflict in
drivers/cpuidle/Makefile between commits b98e01ad4ed9 (cpuidle: Add
Kconfig.arm and
On Sun, Jun 30, 2013 at 10:48:46AM +0100, Lorenzo Pieralisi wrote:
On Sat, Jun 29, 2013 at 08:38:19PM +0100, Russell King - ARM Linux wrote:
On Fri, Jun 28, 2013 at 01:05:42PM -0700, Olof Johansson wrote:
On Fri, Jun 28, 2013 at 1:03 PM, Maxime Ripard
maxime.rip...@free-electrons.com
On Fri, Jun 06, 2014 at 10:43:05PM +0100, Doug Anderson wrote:
On exynos mcpm systems the firmware is hardcoded to jump to an address
in SRAM (0x02073000) when secondary CPUs come up. By default the
firmware puts a bunch of code at that location. That code expects the
kernel to fill in a few
On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:
[...]
Cold boot and resume from suspend are detected via various special
flags in various special locations. Resume from suspend looks at
INFORM1 (0x10048004) for flags. This register is 0 during a cold boot
and has special
when targetting
other ARM instruction set versions.
This works around both issues by limiting the scope of the
Kconfig symbol to platforms that can actually build this driver
cleanly.
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Shawn Guo shawn@linaro.org
Cc: Lorenzo Pieralisi
On Mon, May 05, 2014 at 10:27:20AM +0100, Chander Kashyap wrote:
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander
On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
Hi Doug,
On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org
wrote:
On Tue, 10 Jun 2014, Doug Anderson wrote:
My S-state knowledge is not strong, but I believe that Lorenzo's
questions matter if
On Wed, Jun 11, 2014 at 01:14:21PM +0100, Chander Kashyap wrote:
On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
Hi Doug,
On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi
instead
of the software based one, now present by default.
Cc: Preeti U Murthy pre...@linux.vnet.ibm.com
Cc: Will Deacon will.dea...@arm.com
Acked-by: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
---
arch/arm64/kernel/time.c | 3 +++
1 file changed, 3
Hi Preeti,
On Thu, May 29, 2014 at 12:04:36PM +0100, Preeti U Murthy wrote:
Hi Lorenzo,
On 05/29/2014 02:53 PM, Lorenzo Pieralisi wrote:
On platforms implementing CPU power management, the CPUidle subsystem
can allow CPUs to enter idle states where local timers logic is lost on
power
no
suitable hardware clock event device is present.
Cc: Preeti U Murthy pre...@linux.vnet.ibm.com
Cc: Will Deacon will.dea...@arm.com
Acked-by: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
---
arch/arm64/kernel/time.c | 3 +++
1 file changed, 3
such that any broadcast-capable HW clock
event device present will be chosen in preference as the tick broadcast
device.
Cc: Preeti U Murthy pre...@linux.vnet.ibm.com
Acked-by: Will Deacon will.dea...@arm.com
Acked-by: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral
On Tue, May 20, 2014 at 06:43:46PM +0100, Alex Elder wrote:
Broadcom mobile SoCs use a ROM-implemented holding pen for
controlled boot of secondary cores. A special register is
used to communicate to the ROM that a secondary core should
start executing kernel code. This enable method is
On Wed, May 28, 2014 at 04:30:47AM +0100, Alex Elder wrote:
On 05/27/2014 06:49 AM, Lorenzo Pieralisi wrote:
On Tue, May 20, 2014 at 06:43:46PM +0100, Alex Elder wrote:
Broadcom mobile SoCs use a ROM-implemented holding pen for
controlled boot of secondary cores. A special register
On Wed, May 28, 2014 at 01:22:06PM +0100, Alex Elder wrote:
On 05/28/2014 05:36 AM, Lorenzo Pieralisi wrote:
On Wed, May 28, 2014 at 04:30:47AM +0100, Alex Elder wrote:
On 05/27/2014 06:49 AM, Lorenzo Pieralisi wrote:
On Tue, May 20, 2014 at 06:43:46PM +0100, Alex Elder wrote:
Broadcom
On Tue, May 13, 2014 at 12:43:31PM +0100, Chander Kashyap wrote:
[...]
+static void exynos_suspend(u64 residency)
+{
+ unsigned int mpidr, cpunr;
+
+ mpidr = read_cpuid_mpidr();
+ cpunr = exynos_pmu_cpunr(mpidr);
If I were to be picky, I would compute these values
On Wed, May 14, 2014 at 02:04:51PM +0100, Arnd Bergmann wrote:
On Wednesday 14 May 2014 13:33:55 Chander Kashyap wrote:
diff --git a/drivers/cpuidle/cpuidle-big_little.c
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
On Sat, Feb 01, 2014 at 06:00:40AM +, Brown, Len wrote:
Right now (on ARM at least but I imagine this is pretty universal), the
biggest impact on information accuracy for a CPU depends on what the
other CPUs are doing. The most obvious example is cluster power down.
For a cluster to
On Mon, Jan 20, 2014 at 05:32:53PM +, Tomasz Figa wrote:
Hi Lorenzo,
On 16.01.2014 17:34, Lorenzo Pieralisi wrote:
Hi Tomasz,
thank you for posting this series. I would like to use the DT bindings
for power domains in the bindings for C-states on ARM:
http://comments.gmane.org
On Fri, Jan 17, 2014 at 12:24:58PM +, Hanjun Guo wrote:
[...]
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index bd9bbd0..2210353 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -41,6 +41,7 @@
#include linux/memblock.h
#include
On Fri, Jan 17, 2014 at 12:25:04PM +, Hanjun Guo wrote:
[...]
+/* map logic cpu id to physical GIC id */
+extern int arm_cpu_to_apicid[NR_CPUS];
+#define cpu_physical_id(cpu) arm_cpu_to_apicid[cpu]
Sudeep already commented on this, please update it accordingly.
+
#else/*
Hi Hanjun,
On Fri, Jan 24, 2014 at 09:09:40AM +, Hanjun Guo wrote:
On 2014?01?23? 23:56, Tomasz Nowicki wrote:
Hi Lorenzo,
W dniu 22.01.2014 12:54, Lorenzo Pieralisi pisze:
On Fri, Jan 17, 2014 at 12:24:58PM +, Hanjun Guo wrote:
[...]
diff --git a/arch/arm64/kernel
On Fri, Jan 24, 2014 at 02:37:28PM +, Hanjun Guo wrote:
Hi Lorenzo,
On 2014?01?22? 23:53, Lorenzo Pieralisi wrote:
On Fri, Jan 17, 2014 at 12:25:04PM +, Hanjun Guo wrote:
[...]
+/* map logic cpu id to physical GIC id */
+extern int arm_cpu_to_apicid[NR_CPUS];
+#define
On Mon, Dec 30, 2013 at 08:14:15PM +, Stephen Boyd wrote:
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland mark.rutl
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
Not sure this binding (cache node) belongs in cpus.txt
I am working on defining cache bindings for ARM within the C-state
standardization effort:
http://lists.infradead.org/pipermail
On Tue, Jan 14, 2014 at 09:30:32PM +, Stephen Boyd wrote:
The Krait CPU/L1 error reporting device is made up a per-CPU
interrupt. While we're here, document the next-level-cache
property that's used by the Krait EDAC driver.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark
by the Krait EDAC driver.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
Documentation/devicetree/bindings/arm/cpus.txt | 58
Hi Tomasz,
thank you for posting this series. I would like to use the DT bindings
for power domains in the bindings for C-states on ARM:
http://comments.gmane.org/gmane.linux.power-management.general/41012
and in particular link a given C-state to a given power domain so that the
kernel will
On Thu, Jan 16, 2014 at 06:05:05PM +, Stephen Boyd wrote:
On 01/16, Lorenzo Pieralisi wrote:
On Thu, Jan 16, 2014 at 01:38:40AM +, Stephen Boyd wrote:
On 01/15, Stephen Boyd wrote:
Ah sorry, I forgot to put the compatible property here like in
the dts change. I'll do
On Thu, Jan 16, 2014 at 07:26:17PM +, Stephen Boyd wrote:
On 01/16, Lorenzo Pieralisi wrote:
On Thu, Jan 16, 2014 at 06:05:05PM +, Stephen Boyd wrote:
On 01/16, Lorenzo Pieralisi wrote:
Do we really want to do that ? I am not sure. A cpus node is supposed to
be a container
On Thu, Jan 30, 2014 at 05:25:27PM +, Daniel Lezcano wrote:
On 01/30/2014 05:35 PM, Peter Zijlstra wrote:
On Thu, Jan 30, 2014 at 05:27:54PM +0100, Daniel Lezcano wrote:
struct cpuidle_state *state = drv-states[rq-index];
And from the state, we have the following informations:
On Thu, Jan 30, 2014 at 09:02:15PM +, Nicolas Pitre wrote:
On Thu, 30 Jan 2014, Lorenzo Pieralisi wrote:
On Thu, Jan 30, 2014 at 05:25:27PM +, Daniel Lezcano wrote:
On 01/30/2014 05:35 PM, Peter Zijlstra wrote:
On Thu, Jan 30, 2014 at 05:27:54PM +0100, Daniel Lezcano wrote
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi lorenzo.pieral
On Fri, Apr 25, 2014 at 04:18:42AM +0100, Zi Shen Lim wrote:
Create cpu topology based on MPIDR. When hardware sets MPIDR to sane
values, this method will always work. Therefore it should also work well
as the fallback method. [1]
It has to be implemented as fallback, so you have to rebase
[added Nico in CC]
On Wed, Apr 23, 2014 at 10:25:54AM +0100, Chander Kashyap wrote:
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
On Wed, Apr 23, 2014 at 10:25:52AM +0100, Chander Kashyap wrote:
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by:
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