Add hdmi node to Dalmore device tree to supply Dalmore-specific
data: VDD and PLL regulators for HDMI port, DDC bus and HDMI
cable hotplug GPIO.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra114-dalmore.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch
This patchset adds HDMI support for the Tegra114 Dalmore board.
Tested with 1080p DVI and HDMI monitors.
Mikko Perttunen (5):
host1x: hdmi: Add Tegra114 support
host1x: hdmi: Detect whether display is connected with HDMI or DVI
clk: tegra114: Initialize clocks needed for HDMI
ARM: tegra
Add host1x, dc (display controller) and hdmi devices to Tegra114
device tree.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra114.dtsi | 43 +
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts
fer
choice.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/drm/hdmi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c
index d81fac8..140339b 100644
--- a/drivers/gpu/host1x/drm/hdmi.c
+++ b/drivers/gpu/host1x/drm/hdmi.c
Add host1x, disp1 and disp2 clocks to the clock initialization table.
These clocks are required for HDMI support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra114.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk
Add Tegra114 TMDS configuration, add new peak_current field and
use new place for drive current override bit on Tegra114 platform.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/drm/drm.c | 1 +
drivers/gpu/host1x/drm/hdmi.c | 102 +++-
drivers/gpu/host1x/drm
On 08/28/2013 03:07 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 28, 2013 at 01:40:56PM +0300, Mikko Perttunen wrote:
Use EDID data to determine whether the display supports HDMI or just DVI.
This used to be hardcoded to be HDMI, which broke support for DVI displays
On 08/28/2013 03:25 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 28, 2013 at 01:40:58PM +0300, Mikko Perttunen wrote:
Add host1x, dc (display controller) and hdmi devices to Tegra114
device tree.
"DC" and "HDMI".
Will fix.
Signed-off
On 08/28/2013 03:30 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Aug 28, 2013 at 01:40:59PM +0300, Mikko Perttunen wrote:
Add hdmi node to Dalmore device tree to supply Dalmore-specific
s/hdmi/HDMI/
Will fix.
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
b
Add host1x, disp1 and disp2 clocks to the clock initialization table.
These clocks are required for HDMI support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra114.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk
Add HDMI node to Dalmore device tree to supply Dalmore-specific
data: VDD and PLL regulators for HDMI port, DDC bus and HDMI
cable hotplug GPIO.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra114-dalmore.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch
Add host1x, DC (display controller) and HDMI devices to Tegra114
device tree.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra114.dtsi | 42 +
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts
regulator was set to be always on.
This patch moves the enable to the tegra_hdmi_drm_init function to make
sure the regulator will get enabled.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/drm/hdmi.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a
This patchset adds HDMI support for the Tegra114 Dalmore board.
Tested with 1080p DVI and HDMI monitors.
Mikko Perttunen (6):
host1x: hdmi: Add Tegra114 support
host1x: hdmi: Detect whether display is connected with HDMI or DVI
host1x: hdmi: Enable Vdd earlier for hotplug/DDC
clk
fer
choice.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/drm/hdmi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c
index d81fac8..140339b 100644
--- a/drivers/gpu/host1x/drm/hdmi.c
+++ b/drivers/gpu/host1x/drm/hdmi.c
Add Tegra114 TMDS configuration, add new peak_current field and
use new place for drive current override bit on Tegra114 platform.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 1 +
drivers/gpu/host1x/drm/drm.c | 1 +
drivers/gpu/host1x/drm/hdmi.c | 102
On 09/04/2013 09:44 PM, Stephen Warren wrote:
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
The Vdd regulator used to be enabled only at tegra_output_hdmi_enable,
which is called after a sink is detected. However, the HDMI hotplug pin
works by returning the voltage supplied by the Vdd pin, so
l.
Signed-off-by: Mikko Perttunen
---
drivers/regulator/tps51632-regulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/tps51632-regulator.c
b/drivers/regulator/tps51632-regulator.c
index 6e67be7..87c37f8 100644
--- a/drivers/regulator/tps51632-regulat
On 07/10/2013 10:37 AM, Laxman Dewangan wrote:
Make the entry of Dalmore Power Management Unit device TPS65913
in dalmore DTS file. The Palma driver support this device.
Enable following submodule of the TPS65913:
- GPIO driver
- RTC driver.
- Power regulator driver.
Signed-off-by: Laxman Dewan
On 07/17/2013 11:17 AM, Wei Ni wrote:
On 07/16/2013 07:14 PM, Wei Ni wrote:
On 07/16/2013 01:13 AM, Stephen Warren wrote:
On 07/15/2013 10:48 AM, Stephen Warren wrote:
On 07/12/2013 01:49 AM, Wei Ni wrote:
Enable thermal sensor lm90 for Tegra30 Cardhu and Tegra114 Dalmore.
I have applied th
On 07/17/2013 11:57 AM, Laxman Dewangan wrote:
On Tuesday 16 July 2013 07:21 PM, Mikko Perttunen wrote:
On 07/10/2013 10:37 AM, Laxman Dewangan wrote:
+
+ palmas_gpio: gpio {
+ compatible = "ti,palmas
The debugfs register dumping function did not enable the HDMI clock.
This led to a possible system hang when reading the debugfs entry
while no HDMI cable was connected to the system. This patch makes
sure that the clock is enabled during the read.
Signed-off-by: Mikko Perttunen
---
drivers/gpu
From: Mikko Perttunen
The FutureMax Dance Mat claims to be a SixAxis controller
but breaks if descriptor fixups are applied. Detect the
device using its USB product string and disable fixups
when it is detected.
Signed-off-by: Mikko Perttunen
---
v2: don't use usb device properties
dr
code.
The series has been tested on the Jetson TX1 (T210) and TX2 (T186)
using the host1x_test test suite available at
http://github.com/cyndis/host1x_test
The series itself is available at
http://github.com/cyndis/linux, branch host1x-t186-1
Cheers,
Mikko
Mikko Perttunen (6):
arm64: tegra
Add Tegra186 support for VIC - no changes are required except for new
firmware and compatibility string.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/vic.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/tegra
Add #power-domain-cells for the BPMP node on Tegra186 so that the power
domain provider may be used.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts
Add the node for Host1x on the Tegra186, without any subdevices
for now.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia
Add note that address/size-cells should be 2 on 64-bit systems,
and add Tegra186-specific register range properties.
Signed-off-by: Mikko Perttunen
---
.../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
a
this commit.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/Makefile| 3 +-
drivers/gpu/host1x/dev.c | 60 ++-
drivers/gpu/host1x/dev.h | 4 +
drivers/gpu/host1x/hw/cdma_hw.c| 49
Add a node for the Video Image Compositor on the Tegra186.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index
Currently genpd installs its own suspend_noirq and resume_noirq
callbacks, but never calls down to the driver's corresponding
callbacks. Add these calls.
Signed-off-by: Mikko Perttunen
---
drivers/base/power/domain.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers
On 20.06.2017 15:47, Ulf Hansson wrote:
On 20 June 2017 at 14:05, Mikko Perttunen wrote:
Currently genpd installs its own suspend_noirq and resume_noirq
callbacks, but never calls down to the driver's corresponding
callbacks. Add these calls.
Signed-off-by: Mikko Perttunen
---
drivers
Currently genpd installs its own suspend_noirq, resume_noirq,
and poweroff_noirq callbacks, but never calls down to the driver's
corresponding callbacks. Add these calls.
Signed-off-by: Mikko Perttunen
---
v2:
- Moved pm_generic_suspend_noirq to before pm_runtime_force_suspend,
On 20.06.2017 17:18, Ulf Hansson wrote:
On 20 June 2017 at 15:38, Mikko Perttunen wrote:
Currently genpd installs its own suspend_noirq, resume_noirq,
and poweroff_noirq callbacks, but never calls down to the driver's
corresponding callbacks. Add these calls.
Signed-off-by: Mikko Pert
Currently genpd installs its own noirq callbacks, but never calls down
to the driver's corresponding callbacks. Add these calls.
Signed-off-by: Mikko Perttunen
---
v3:
- Factored out common code in pm_genpd_{suspend,poweroff}_noirq
- Added pm_generic_* calls to rest of callbacks
drivers
With the new channel allocation model, multiple threads can be
allocating channels simultaneously. Therefore we need to add a lock
around the code.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/channel.c | 7 +++
drivers/gpu/host1x/channel.h | 2 ++
2 files changed, 9 insertions
ested using the host1x_test test suite, and also by running
the performance test of host1x_test in parallel.
Thanks,
Mikko
Mikko Perttunen (10):
gpu: host1x: Parameterize channel aperture size
gpu: host1x: Print MLOCK state in debug dumps on T186
gpu: host1x: Add lock around channel allocatio
Add support for dumping current MLOCK state in debug dumps also
on T186, now that MLOCKs are used by the driver.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/debug_hw_1x06.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/host1x/hw
This ensures that there are no concurrency issues when multiple users
are trying to use VIC concurrently, and also simplifies the code
slightly.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/vic.c | 47 +++--
1 file changed, 20 insertions
patch only adapts VIC to the new model.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 46 ++
drivers/gpu/drm/tegra/drm.h | 7 +++-
drivers/gpu/drm/tegra/vic.c | 79 +++--
3 files changed, 92 insertions(+), 40
Add an option to host1x_channel_request to interruptibly wait for a
free channel. This allows IOCTLs that acquire a channel to block
the userspace.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 9 +
drivers/gpu/drm/tegra/gr2d.c | 6 +++---
drivers/gpu/drm/tegra
As a preparation for each context potentially being able to have a
separate hardware channel, and thus requiring a separate syncpoint,
move syncpoints to be stored inside each context instead of global
client data.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 8
patch implements locking on all platforms from Tegra20 to
Tegra186.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/cdma.c | 1 +
drivers/gpu/host1x/cdma.h | 1 +
drivers/gpu/host1x/hw/cdma_hw.c| 122
Allow job submitters to set a callback to be called when the job has
completed. The jobs are stored and the callbacks called outside the
CDMA lock area to allow the callbacks to do CDMA-requiring operations
like freeing channels.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/cdma.c | 44
for contexts.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 27 ---
drivers/gpu/drm/tegra/drm.h | 4
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 2cdd054520bf
The size of a single channel's aperture is different on Tegra186 vs.
previous chips. Parameterize the value using a new define in the
register definition headers.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/channel_hw.c | 3 +--
drivers/gpu/host1x/hw/hw_host1x01_chan
On 10/20/2015 06:56 PM, Stephen Warren wrote:
...
In drivers/pci/host/pci-tegra.c tegra_pcie_get_resources() I see a call
to devm_phy_optional_get().
The SATA driver doesn't seem to do anything with phys at the moment,
although tegra124.dtsi does put phy-related properties into the SATA DT
node
On 08/03/2018 03:54 PM, Jassi Brar wrote:
On Mon, Jul 2, 2018 at 5:10 PM, Mikko Perttunen wrote:
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has been sent. The new option is used with the Tegra
One potential issue is with host1x clients where userspace processes can
submit jobs with invalid memory accesses (addresses not mapped to
IOMMU). If when such a failure happens, we disable the DMA for the whole
host1x client, unrelated userspace processes may see failures even
though there is
On 04.08.2018 13:45, Mikko Perttunen wrote:
On 08/03/2018 03:54 PM, Jassi Brar wrote:
On Mon, Jul 2, 2018 at 5:10 PM, Mikko Perttunen
wrote:
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has
On 08/08/2018 05:10 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 5:08 PM, Mikko Perttunen wrote:
On 04.08.2018 13:45, Mikko Perttunen wrote:
On 08/03/2018 03:54 PM, Jassi Brar wrote:
On Mon, Jul 2, 2018 at 5:10 PM, Mikko Perttunen
wrote:
Add a new TXDONE option, TXDONE_BY_BLOCK
On 08/08/2018 05:39 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 8:04 PM, Mikko Perttunen wrote:
On 08/08/2018 05:10 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 5:08 PM, Mikko Perttunen wrote:
On 04.08.2018 13:45, Mikko Perttunen wrote:
On 08/03/2018 03:54 PM, Jassi Brar wrote
while atomic. I assume this gets printed through the earlycon
as it's printing out correctly.
Thanks,
Mikko
On 08.08.2018 17:46, Mikko Perttunen wrote:
On 08/08/2018 05:39 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 8:04 PM, Mikko Perttunen wrote:
On 08/08/2018 05:10 PM, Jassi Brar w
On 20.07.2018 15:45, Aapo Vienamo wrote:
Parse the pinctrl states from the device tree and implement pad voltage
state reconfiguration in the mmc start_signal_voltage_switch() callback.
This is done in the mmc callback because the order of pad
reconfiguration and sdhci voltage switch depend on th
I would maybe say "dt-bindings: mmc: tegra: Add pad voltage control
properties" or similar for the subject - the current kind of looks like
the SDHCI controller is a pinctrl device :)
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Document the pinctrl bindin
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra210.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27 +++
1 file changed, 27
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra186.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40
1 file changed
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Set regulator-min-microvolt property of ldo2 to 1.8 V in
tegra210-p2180.dtsi. ldo2 is used by the sdmmc1 SDHCI controller and its
voltage needs to be adjusted down to 1.8 V to support faster signaling
modes. It appears that
Technically this shouldn't be required since VDD_1V8 is always on
anyway, but I think it's nicer to specify regulators anyway, so +1!
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
On p2180 sdmmc4 is powered from a fixed 1.8 V regulator.
Signed-off-by: Aa
Looks like patch 6 will probably cause tegra-sdhci to start advertising
faster modes (see " if (!IS_ERR(host->mmc->supply.vqmmc))" in
sdhci-tegra.c). With that patch and this, will the SDHCI core start to
try putting us into these higher modes? Clearly that won't work yet
before the upcoming pa
On 24.07.2018 17:29, Aapo Vienamo wrote:
Implement polling with 10 ms timeout for automatic pad drive strength
calibration.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc
On 24.07.2018 17:34, Aapo Vienamo wrote:
Configure the voltage reference used by the automatic pad drive strength
calibration procedure. The value is a magic number from the TRM.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 14 --
1 file changed, 12 insertions
Reviewed-by: Mikko Perttunen
On 24.07.2018 17:34, Aapo Vienamo wrote:
Automatic pad drive strength calibration is performed on a separate pad
identical to the ones used for driving the actual bus. Power on the
calibration pad during the calibration procedure and power it off
afterwards to save
On 24.07.2018 17:34, Aapo Vienamo wrote:
Disable the card clock during automatic pad drive strength calibration
and re-enable it aftewards.
s/aftewards/afterwards/.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 27 +++
1 file changed, 27 inserti
On 24.07.2018 17:34, Aapo Vienamo wrote:
Add bindings documentation for pad pull up and pull down offset values to be
programmed before executing automatic pad drive strength calibration.
Signed-off-by: Aapo Vienamo
---
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 32 +
On 24.07.2018 17:34, Aapo Vienamo wrote:
Parse the pad drive strength calibration offsets from the device tree.
Program the calibration offsets in accordance with the current signaling
mode.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 147 +
On 24.07.2018 17:34, Aapo Vienamo wrote:
Run the automatic pad calibration after voltage switching if
tegra_host->pad_calib_required is set.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra
This nas been NAK'd before as harder to read than the current way.
Thanks,
Mikko
On 01/23/2018 10:29 PM, Christopher Díaz Riveros wrote:
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
This issue was detected by using the Coccinelle software.
Signed-off-by: Christopher Díaz Riveros
On 11.01.2018 23:56, Rob Herring wrote:
On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to bo
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dt
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 246
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (6):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Reviewed-by: Mikko Perttunen
On 01/27/2018 04:28 PM, Julia Lawall wrote:
Check the variable that was most recently initialized.
The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
//
@@
expression x, y, f, g, e, m;
statement S1,S2,S3,S4;
@@
x = f(...);
if
On 01/16/2018 12:06 AM, Lyude Paul wrote:
It's here! After a lot of investigation, rewrites, and traces, I present
the patch series to implement all known levels of clockgating for
Kepler1 and Kepler2 GPUs.
Starting with Fermi GPUs (this is probably present on earlier GPUs as
well, but with a fa
Rob,
this binding is for a specific IP block (for measuring/aggregating input
pulses) on the Tegra186 SoC, so I don't think it fits into any generic
binding.
Thanks,
Mikko
On 03/27/2018 05:52 PM, Rob Herring wrote:
On Wed, Mar 21, 2018 at 10:10:38AM +0530, Rajkumar Rampelli wrote:
Supply D
On 04/09/2018 04:21 PM, Rob Herring wrote:
On Mon, Apr 9, 2018 at 12:38 AM, Mikko Perttunen wrote:
Rob,
Please don't top post to lists.
this binding is for a specific IP block (for measuring/aggregating input
pulses) on the Tegra186 SoC, so I don't think it fits into any gener
On 07.03.2018 16:20, Guenter Roeck wrote:
On 03/07/2018 01:47 AM, Rajkumar Rampelli wrote:
On Wednesday 28 February 2018 07:59 PM, Guenter Roeck wrote:
On 02/27/2018 11:03 PM, Mikko Perttunen wrote:
On 02/28/2018 08:12 AM, Rajkumar Rampelli wrote:
On Wednesday 28 February 2018 11:28 AM
of_xlate to skip any NULL
clocks.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-bpmp.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index a896692b74ec..01dada561c10 100644
--- a/drivers/clk/tegra
HSP interrupts can be routed through exposed "shared interrupts". These
interrupts can be mapped to various internal interrupt lines. Add
interrupt properties for shared interrupts to the tegra186-hsp device
tree bindings.
Signed-off-by: Mikko Perttunen
Acked-by: Jon Hunter
Review
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has been sent. The new option is used with the Tegra
Combined UART driver to minimize unnecessary overhead when transmitting
data.
Signed-off-by: Mikko
compatible to tegra186-hsp.
Signed-off-by: Mikko Perttunen
Acked-by: Jon Hunter
---
Notes:
v3:
- Added Jon's Acked-by.
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/n
The Tegra Combined UART is the proper primary serial port on P2888,
so use it.
Signed-off-by: Mikko Perttunen
Acked-by: Jon Hunter
---
Notes:
v2:
- Added Jon's Acked-by.
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
The HSP driver is currently in many places written with the assumption
of only supporting doorbells. Prepare for the addition of shared
mailbox support by removing these assumptions and cleaning up the code.
Signed-off-by: Mikko Perttunen
Reviewed-by: Jon Hunter
---
Notes:
v2:
- Moved
iver.
The initial use for the mailboxes is the Tegra Combined UART. For this
purpose, we use interrupts to receive data, and spinning to wait for
the transmit mailbox to be emptied to minimize unnecessary overhead.
Signed-off-by: Mikko Perttunen
Reviewed-by: Jon Hunter
---
Notes:
v3:
- Ad
Tegra HSP blocks that are already controlled by the Tegra
HSP mailbox driver.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- Removed (void) casts for unused variables.
- Changed the uart_set_options() call to be on one line, even if its
over 80 characters.
- Added defines
Add bindings for the Tegra Combined UART device used to talk to the
UART console on Tegra194 systems.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
Acked-by: Jon Hunter
---
Notes:
v2:
- Added Rob's Reviewed-by.
v3:
- Added Jon's Acked-by.
.../bindi
ion option to the mailbox
framework.
* patches 4 and 5 add support for the "shared mailbox" primitive
to the Tegra HSP driver.
* patch 6 adds the TCU driver itself
* patches 7 and 8 do the necessary device tree changes.
The series has been tested on the Tegra194 P2972 board.
Mikko Perttunen (8
On 02.07.2018 16:18, Thierry Reding wrote:
On Mon, Jul 02, 2018 at 02:40:31PM +0300, Mikko Perttunen wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
multiplexing multiple "virtual UARTs" into a single hardware serial
port. The TCU is the primary seri
On 02.07.2018 16:47, Thierry Reding wrote:
On Mon, Jul 02, 2018 at 04:30:07PM +0300, Mikko Perttunen wrote:
On 02.07.2018 16:18, Thierry Reding wrote:
On Mon, Jul 02, 2018 at 02:40:31PM +0300, Mikko Perttunen wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
Add the kfree_const call to __clk_put and add comments to both
functions to remind that the logic in them should be kept in sync.
Fixes: 253160a8ad06 ("clk: core: Copy connection id")
Signed-off-by: Mikko Perttunen
---
drivers/clk/clk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Hi,
I'm seeing the following spew during boot with Tegra210 with the patch
"regulator: core: Link consumer with regulator driver", recently applied
to linux-next:
[1.196664] [ cut here ]
[1.201480] kobject: '(null)' ((ptrval)): is not initialized,
yet
On 05/13/2018 05:16 PM, Andy Shevchenko wrote:
On Tue, May 8, 2018 at 2:44 PM, Mikko Perttunen wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
multiplexing multiple "virtual UARTs" into a single hardware serial
port. The TCU is the primary serial port o
On 05/13/2018 06:36 PM, Jassi Brar wrote:
On Tue, May 8, 2018 at 5:14 PM, Mikko Perttunen wrote:
+config SERIAL_TEGRA_TCU
+ tristate "NVIDIA Tegra Combined UART"
+ depends on ARCH_TEGRA && MAILBOX
+ select SERIAL_CORE
+ help
+ Suppo
On 14.05.2018 01:20, Andy Shevchenko wrote:
On Sun, May 13, 2018 at 9:04 PM, Mikko Perttunen wrote:
On 05/13/2018 05:16 PM, Andy Shevchenko wrote:
On Tue, May 8, 2018 at 2:44 PM, Mikko Perttunen
wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
multiplexing
On 22.05.2018 18:15, Jon Hunter wrote:
On 08/05/18 12:43, Mikko Perttunen wrote:
Non-doorbell interrupts are routed through "shared interrupts". These
interrupts can be mapped to various internal interrupt lines. Add
interrupt properties for shared interrupts to the tegra186-hsp d
On 22.05.2018 18:36, Jon Hunter wrote:
On 08/05/18 12:43, Mikko Perttunen wrote:
The HSP driver is currently in many places written with the assumption
of only supporting doorbells. Prepare for the addition of shared
mailbox support by removing these assumptions and cleaning up the code
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