Winfast remote controls.
Signed-off-by: Nicolas Boichat <[EMAIL PROTECTED]>
---
drivers/media/common/ir-common.c | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff -rpuN drivers/media.old/common/ir-common.c
drivers/media/common/ir-common.c
--- drivers/media.old/com
Hello,
On Thu, 2005-04-21 at 01:10 +0200, Alexander Nyberg wrote:
> The new out of line put_user() assembly on x86_64 changes %rcx without
> telling GCC about it causing things like:
>
> http://bugme.osdl.org/show_bug.cgi?id=4515
Thank you, this patch fixes the message queue problem.
Best rega
Hello Alexander,
I have other kind of problems with this patch...
With 2.6.12-rc2 + your patch, when I run OpenOffice (a 32-bit
application), I get this in dmesg :
Unable to handle kernel paging request at 2d9280b0 RIP:
{__put_user_4+32}
PGD 0
Oops: 0002 [1] SMP
CPU 0
Modules linked
st regards,
Nicolas Boichat
From: Nicolas Boichat <[EMAIL PROTECTED]>
---
drivers/hwmon/Kconfig| 24 +
drivers/hwmon/Makefile |1
drivers/hwmon/applesmc.c | 964 ++
3 files changed, 989 insertions(+), 0 deletions(-)
diff --git a/drive
Hello,
Cong WANG wrote:
> 2007/3/14, Cong WANG wrote:
>> I am sorry. I forgot to CC to the list.
>>
>> 2007/3/14, Nicolas Boichat wrote:
>> > Hello,
>> >
>>
>>
>>
>> > +sta
e of initialisation problem, and when
the driver is unloaded.
- Add data buffer length sanity checks.
- Improvements of SMC keys' comments (add data type reported by the device).
- Add temperature sensors to Macbook Pro.
- Add support for reading fan physical position (e.g. "Left Side")
rds,
Nicolas
Implement key enumeration in applesmc.
Signed-off-by: Nicolas Boichat <[EMAIL PROTECTED]>
---
drivers/hwmon/applesmc.c | 263 ++
1 files changed, 262 insertions(+), 1 deletions(-)
diff --git a/drivers/hwmon/applesmc.c b/drivers/hwm
egards,
Nicolas
Cannot sleep in led->brightness_set handler if it is called from a softirq.
Reduce wait_status timetout from 100ms to 2ms, as wait_status either takes less
than 1.5 ms, or fails.
Signed-off-by: Nicolas Boichat <[EMAIL PROTECTED]>
---
drivers/hwmon/applesmc.c | 25
Hi again,
Richard Purdie wrote:
> Hi,
>
> On Sat, 2007-04-14 at 16:05 +0800, Nicolas Boichat wrote:
>
>> Bradley Hook wrote:
>>
>>> Slightly off-topic, but I've been experiencing a minor bug in the
>>> keyboard backlight feature.
>>>
Hello,
Justin Piszcz wrote:
> DISCLAIMER: This patch is still experimental. AUTHOR: Rudolf Marek has
> written the coretemp module for Intel Core Duo/Solo
> processors.
>
> Without this patch, you cannot monitor your CPU temperature, at least
> not on a DG965 motherboard.
[snip]
> Commentary:
> It
Hello,
Nicolas Boichat wrote:
> Hello,
>
> I developed, a while ago, a driver the Apple System Management
> Controller, which provides an accelerometer (Apple Sudden Motion
> Sensor), light sensors, temperature sensors, keyboard backlight control
> and fan control on Intel-based
Andrew Morton wrote:
> On Mon, 19 Mar 2007 13:19:00 +0800 Nicolas Boichat <[EMAIL PROTECTED]> wrote:
>
>> This driver provides support for the Apple System Management Controller,
>> which
>> provides an accelerometer (Apple Sudden Motion Sensor), light sensors,
&g
Hello,
Andrew Morton wrote:
> On Mon, 19 Mar 2007 13:19:00 +0800 Nicolas Boichat <[EMAIL PROTECTED]> wrote:
>
>
>> This driver provides support for the Apple System Management Controller,
>> which
>> provides an accelerometer (Apple Sudden Motion Sensor), ligh
Hello,
Bob Copeland wrote:
> On 3/14/07, Nicolas Boichat <[EMAIL PROTECTED]> wrote:
>> Hello,
>>
>> I developed, a while ago, a driver the Apple System Management
>> Controller, which provides an accelerometer (Apple Sudden Motion
>> Sensor), light sensors,
atform/hdaps/position)
Thanks,
Best regards,
Nicolas
Invert x axis on applesmc input device to make it usable as a joystick.
Signed-off-by: Nicolas Boichat <[EMAIL PROTECTED]>
---
drivers/hwmon/applesmc.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/hw
, with my comments where
needed, of the dmesg output with and without this commit. You can get
the raw dmesg outputs, and my .config there:
http://www.boichat.ch/nicolas/linux/
Best regards,
Nicolas Boichat
--- dmesg-2.6.21-rc4-head-notimestamp 2007-03-26 02:19:57.0 +0800
Vanilla
Nicolas Boichat wrote:
> Hello,
>
> I'm running a Macbook Pro first generation (Core Duo, so x86).
>
> I ran accross these two problems while upgrading from 2.6.21-rc3 to the
> current git HEAD:
> 1. appletouch cannot initialize the device properly at boot time (the
Ingo Molnar wrote:
> * Nicolas Boichat <[EMAIL PROTECTED]> wrote:
>
>
>>> I found out which commit seems to cause these bugs:
>>> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=d04f41e35343f1d788551fd3f753f51794f4afcf
>>>
&g
Hi Dmitry,
Sorry I did not receive your message originally, someone else pointed it
to me recently, and I recovered it from LKML archives.
Dmitry Torokhov wrote:
> Hi Nicolas,
>
> On Monday 19 March 2007 01:19, Nicolas Boichat wrote:
>
>> + /* initiali
Hi,
Thanks for your comments.
Jean Delvare wrote:
> Hi Nicolas,
>
> Sorry for the delay.
>
> On Wed, 14 Mar 2007 17:29:39 +0800, Nicolas Boichat wrote:
>> I developed, a while ago, a driver the Apple System Management
>> Controller, which provides an acceler
ANX7688 is a transmitter to support DisplayPort over USB-C for
smartphone and tablets.
This binding only describes the HDMI to DP component of the chip.
Signed-off-by: Nicolas Boichat
---
.../devicetree/bindings/video/bridge/anx7688.txt | 32 ++
1 file changed, 32
the bridge
via 2 registers on I2C.
Signed-off-by: Nicolas Boichat
---
Hi,
I tested this driver using the Mediatek HDMI controller (MT8173) upstream
of the ANX bridge chip (Phillip sent a PULL request on June 13:
git://git.pengutronix.de/git/pza/linux.git tags/mediatek-drm-2016-06-13
).
I have 2
Hi Archit,
Thanks for your reply.
On Tue, Jun 21, 2016 at 11:39 PM, Archit Taneja wrote:
> Hi,
>
> On 6/20/2016 12:44 PM, Nicolas Boichat wrote:
>>
>> ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
>> that has an internal microcontroller.
&g
Hi Mark,
On Mon, Aug 17, 2015 at 11:52 AM, Nicolas Boichat wrote:
> chipselect (in the case of spi-gpio: spi_gpio_chipselect, which
> calls gpiod_set_raw_value_cansleep) can sleep, so we should not
> hold a spinlock while calling it from spi_bitbang_setup.
>
> This issue was int
On Mon, Aug 31, 2015 at 9:44 PM, Leilk Liu wrote:
> This patch adds MT8173 spi bus controllers into device tree.
The corresponding SPI driver has already been merged in
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git .
> Signed-off-by: Leilk Liu
Reviewed-and-Tested-by: N
when using
allmodconfig on some architectures, and we do not want to break these
builds by default.
Signed-off-by: Nicolas Boichat
Change-Id: Ic346706e3297c9f0d790e3552aa94e5cff9897a6
---
I'm trying to revive this old patch. When it was first submitted [1],
Jonathan got the following fee
when using
allmodconfig on some architectures, and we do not want to break these
builds by default.
Signed-off-by: Nicolas Boichat
Change-Id: Ic346706e3297c9f0d790e3552aa94e5cff9897a6
---
v2 (Rusty Russell feedback):
- Renamed flag from -f to -E (-f means force, so we pick -E for error
multitouch driver.
Signed-off-by: Wei-Ning Huang
Signed-off-by: Nicolas Boichat
---
Changes since v3:
- Rebase on latest linux-next/master, which moved the quirk list from
hid-core.c to hid-quirks.c. Also, completely rework the logic to make
it possible to bind google-hammer driver to keyboard
On Thu, Nov 22, 2018 at 4:03 PM Jjian Zhou wrote:
>
> MT8183 need SDIO driver. So it need add new code
> to support it.
The description does not seem to match what is going on below: I don't
see anything that is obviously MT8183-specific. At first glance, this
seems like a patch that makes it pos
On Tue, Nov 27, 2018 at 11:43 AM Weiyi Lu wrote:
>
> From: Owen Chen
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new
On Tue, Nov 27, 2018 at 11:43 AM Weiyi Lu wrote:
>
> From: Owen Chen
>
> Both MT8183 & MT6765 add more bus protect node than previous project,
> therefore we add two more register for setup bus protect, which reside
> at INFRA_CFG & SMI_COMMON.
>
> With the following change
> 1. bus protect need
On Tue, Nov 27, 2018 at 11:43 AM Weiyi Lu wrote:
>
> Add scpsys driver for MT8183
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 227 +-
> 1 file changed, 226 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c
> b
On Wed, Nov 28, 2018 at 4:37 AM Sean Wang wrote:
>
> Weiyi Lu 於 2018年11月26日 週一 下午7:45寫道：
> >
> > From: Owen Chen
> >
> > PLLs with tuner_en bit, such as APLL1, need to disable
> > tuner_en before apply new frequency settings, or the new frequency
> > settings (pcw) will not be applied.
> > The t
On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new A
On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
>add a variable to indicate this change and
>backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>1.5Ghz, add a var
(not a complete review...)
On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> Both MT8183 & MT6765 add more bus protect node than previous project,
> therefore we add two more register for setup bus protect, which reside
> at INFRA_CFG & SMI_COMMON.
>
> With the following ch
On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote:
>
> Add scpsys driver for MT8183
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 226 ++
> 1 file changed, 226 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c
> b/drivers/soc/med
On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
>
> Add MT8183 clock support, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/clk/mediatek/Kconfig | 75 ++
> drivers/clk/mediatek/Makefile | 12 +
>
On Wed, Dec 5, 2018 at 8:18 PM Wei Yang wrote:
>
> On Wed, Dec 05, 2018 at 03:39:51PM +0800, Nicolas Boichat wrote:
> >On Wed, Dec 5, 2018 at 3:25 PM Wei Yang wrote:
> >>
> >> On Wed, Dec 05, 2018 at 01:48:27PM +0800, Nicolas Boichat wrote:
> >> >In so
calls will continue to
trigger a warning, as we keep GFP_DMA32 in GFP_SLAB_BUG_MASK.
This implies that calls to kmem_cache_*alloc on a SLAB_CACHE_DMA32
kmem_cache must _not_ use GFP_DMA32 (it is anyway redundant and
unnecessary).
Signed-off-by: Nicolas Boichat
---
Changes since v2:
- Clarified
the hunks to PATCH v5 3/3, so that maintainer can decide whether
to pick the change independently.
Nicolas Boichat (3):
mm: Add support for kmem caches in DMA32 zone
iommu/io-pgtable-arm-v7s: Request DMA32 memory, and improve debugging
mm: Add /sys/kernel/slab/cache/cache_dma32
A previous patch in this series adds support for SLAB_CACHE_DMA32
kmem caches. This adds the corresponding
/sys/kernel/slab/cache/cache_dma32 entries, and fixes slabinfo
tool.
Signed-off-by: Nicolas Boichat
---
There were different opinions on whether this sysfs entry should
be added, so I&#x
in the future.
Fixes: ad67f5a6545f ("arm64: replace ZONE_DMA with ZONE_DMA32")
Signed-off-by: Nicolas Boichat
---
Changes since v2:
- Commit message
(v3 used the page_frag approach)
Changes since v4:
- Do not pass ARM_V7S_TABLE_GFP_DMA to kmem_cache_zalloc, as this
is unnece
On Fri, Dec 7, 2018 at 4:05 PM Matthew Wilcox wrote:
>
> On Fri, Dec 07, 2018 at 02:16:19PM +0800, Nicolas Boichat wrote:
> > +#ifdef CONFIG_ZONE_DMA32
> > +#define ARM_V7S_TABLE_GFP_DMA GFP_DMA32
> > +#define ARM_V7S_TABLE_SLAB_CACHE SLAB_CACHE_DMA32
>
> This nam
On Tue, Nov 27, 2018 at 5:27 PM Jjian Zhou wrote:
>
> On Mon, 2018-11-26 at 19:47 +0800, Nicolas Boichat wrote:
> > On Thu, Nov 22, 2018 at 4:03 PM Jjian Zhou wrote:
> > >
> > > MT8183 need SDIO driver. So it need add new code
> > > to support it.
> &g
A previous patch in this series adds support for SLAB_CACHE_DMA32
kmem caches. This adds the corresponding
/sys/kernel/slab/cache/cache_dma32 entries, and fixes slabinfo
tool.
Cc: sta...@vger.kernel.org
Signed-off-by: Nicolas Boichat
---
There were different opinions on whether this sysfs entry
in the future.
Cc: sta...@vger.kernel.org
Fixes: ad67f5a6545f ("arm64: replace ZONE_DMA with ZONE_DMA32")
Signed-off-by: Nicolas Boichat
---
Changes since v2:
- Commit message
(v3 used the page_frag approach)
Changes since v4:
- Do not pass ARM_V7S_TABLE_GFP_DMA to kmem_cache_zallo
calls will continue to
trigger a warning, as we keep GFP_DMA32 in GFP_SLAB_BUG_MASK.
This implies that calls to kmem_cache_*alloc on a SLAB_CACHE_DMA32
kmem_cache must _not_ use GFP_DMA32 (it is anyway redundant and
unnecessary).
Cc: sta...@vger.kernel.org
Signed-off-by: Nicolas Boichat
Acked-by
hunks that added cache_dma32 sysfs file, and moved
the hunks to PATCH v5 3/3, so that maintainer can decide whether
to pick the change independently.
Changes since v5:
- Rename ARM_V7S_TABLE_SLAB_CACHE to ARM_V7S_TABLE_SLAB_FLAGS.
- Add stable@ to cc.
Nicolas Boichat (3):
mm: Add suppor
On Fri, May 25, 2018 at 12:21 AM, Greg Kroah-Hartman
wrote:
> On Thu, May 24, 2018 at 07:42:00AM +0800, Nicolas Boichat wrote:
>> On Thu, May 24, 2018 at 12:39 AM, Greg Kroah-Hartman
>> wrote:
>> > On Wed, May 23, 2018 at 10:03:55AM -0400, Alan Stern wrote:
>> &
o reduce the time to what the USB specification
requires: 10 ms.
Signed-off-by: Nicolas Boichat
---
Reduces enumeration time by ~40ms in conjunction with previous
patch/quirk (or ~80ms on its own).
Documentation/ABI/testing/sysfs-bus-usb | 4
drivers/usb/core/hub.c | 6 +
port only.
Signed-off-by: Nicolas Boichat
---
Changes since v1:
- Added documentation in Documentation/ABI
- Updated timing in commit message to account for recent improvement
in USB core (74072bae88fb3b)
Documentation/ABI/testing/sysfs-bus-usb | 18 ++
drivers/usb/
On Mon, Dec 10, 2018 at 3:33 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new A
On Mon, Dec 10, 2018 at 3:33 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> Both MT8183 & MT6765 add more bus protect node than previous project,
> therefore we add two more register for setup bus protect, which reside
> at INFRA_CFG & SMI_COMMON.
>
> With the following change
> 1. bus protect need n
On Mon, Dec 10, 2018 at 3:32 PM Weiyi Lu wrote:
>
> Add MT8183 clock support, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/clk/mediatek/Kconfig | 75 ++
> drivers/clk/mediatek/Makefile | 12 +
>
On Sat, Dec 8, 2018 at 4:42 PM Yong Wu wrote:
>
> The larb-id may be remapped in the smi-common, this means the
> larb-id reported in the mtk_iommu_isr isn't the real larb-id,
>
> Take mt8183 as a example:
>M4U
> |
> -
On Sat, Dec 8, 2018 at 4:42 PM Yong Wu wrote:
>
> The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
> the ARM Short-descriptor like mt8173, and most of the HW registers
> are the same.
>
> Here list main differences between mt8183 and mt8173/mt2712:
> 1) mt8183 has only one M4U H
On Sat, Dec 8, 2018 at 4:43 PM Yong Wu wrote:
>
> There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
> mmu0 or mmu1 to balance the bandwidth via the smi-common register
> SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
>
> In mt8183, For better performance, we switch larb1/2/5/7 t
On Fri, Dec 21, 2018 at 4:02 PM Yong Wu wrote:
>
> On Fri, 2018-12-21 at 12:43 +0800, Nicolas Boichat wrote:
> > On Sat, Dec 8, 2018 at 4:42 PM Yong Wu wrote:
> > >
> > > The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
> > > the A
Hi all,
On Mon, Dec 10, 2018 at 9:15 AM Nicolas Boichat wrote:
>
> This is a follow-up to the discussion in [1], [2].
>
> IOMMUs using ARMv7 short-descriptor format require page tables
> (level 1 and 2) to be allocated within the first 4GB of RAM, even
> on 64-bit systems.
>
-id
> remapping relationship in this patch.
>
> If there is no this larb-id remapping in some SoCs, use the linear
> mapping array instead.
>
> This also is a preparing patch for mt8183.
>
> Signed-off-by: Yong Wu
I think it's a little cleaner this way, thanks.
Reviewe
On Tue, Jan 1, 2019 at 11:58 AM Yong Wu wrote:
>
> The protect memory setting is a little different in the different SoCs.
> In the register REG_MMU_CTRL_REG(0x110), the TF_PROT(translation fault
> protect) shift bit is normally 4 while it shift 5 bits only in the
> mt8173. This patch delete the c
ty.
>
> It is a preparing patch for mt8183.
>
> Signed-off-by: Yong Wu
Reviewed-by: Nicolas Boichat
> ---
> drivers/iommu/mtk_iommu.c | 4 ++--
> drivers/iommu/mtk_iommu.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/mt
On Tue, Jan 1, 2019 at 11:58 AM Yong Wu wrote:
>
> Both mt8173 and mt8183 don't have this vld_pa_rng(valid physical address
> range) register while mt2712 have. Move it into the plat_data.
>
> Signed-off-by: Yong Wu
> ---
> drivers/iommu/mtk_iommu.c | 3 ++-
> drivers/iommu/mtk_iommu.h | 1 +
>
On Tue, Jan 1, 2019 at 11:59 AM Yong Wu wrote:
>
> The register VLD_PA_RNG(0x118) was forgot to backup while adding 4GB
> mode support for mt2712. this patch add it.
>
> Fixes: 30e2fccf9512 ("iommu/mediatek: Enlarge the validate PA range
> for 4GB mode")
> Signed-off-by: Yong Wu
> ---
> drivers/
On Wed, Jan 2, 2019 at 10:13 AM Long Cheng wrote:
>
> In DMA engine framework, add 8250 uart dma to support MediaTek uart.
> If MediaTek uart enabled(SERIAL_8250_MT6577), and want to improve
> the performance, can enable the function.
>
> Signed-off-by: Long Cheng
> ---
> drivers/dma/mediatek/82
On Wed, Jan 2, 2019 at 10:01 PM Henry Chen wrote:
>
> Support power domain performance state, add header file for scp event.
>
> Signed-off-by: Henry Chen
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 60
> +++
> drivers/soc/mediatek/mtk-scpsys.h | 22 +
On Wed, Jan 2, 2019 at 10:01 PM Henry Chen wrote:
>
> Add dvfsrc driver for MT8183
>
> Signed-off-by: Henry Chen
> ---
> drivers/soc/mediatek/Kconfig | 15 ++
> drivers/soc/mediatek/Makefile | 1 +
> drivers/soc/mediatek/mtk-dvfsrc.c | 473
> ++
>
On Thu, Jan 3, 2019 at 10:16 PM Henry Chen wrote:
>
> On Thu, 2019-01-03 at 09:48 +0800, Nicolas Boichat wrote:
> > On Wed, Jan 2, 2019 at 10:01 PM Henry Chen wrote:
> > >
> > > Support power domain performance state, add header file for scp event.
> &g
On Thu, Jan 3, 2019 at 10:16 PM Henry Chen wrote:
>
> On Thu, 2019-01-03 at 10:16 +0800, Nicolas Boichat wrote:
> > On Wed, Jan 2, 2019 at 10:01 PM Henry Chen wrote:
> > >
> > > Add dvfsrc driver for MT8183
> > >
> > > Signed-off-by: Henry Che
On Mon, Dec 24, 2018 at 6:52 PM Yongqiang Niu
wrote:
>
> This patch redefine mtk_ddp_sout_sel
Can you describe a bit more why you are making this change?
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 32
> 1 file changed, 20 in
On Mon, Dec 24, 2018 at 6:53 PM Yongqiang Niu
wrote:
>
> This patch add gmc_bits for ovl private data
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +--
> 1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm
On Mon, Dec 24, 2018 at 6:53 PM Yongqiang Niu
wrote:
>
> This patch add function mtk_ddp_comp_get_type
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 11 insertions(+)
>
On Mon, Dec 24, 2018 at 6:52 PM Yongqiang Niu
wrote:
>
> This patch add ovl0/ovl0_2l usecase
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 38
> ++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu
Not a full review, a few comments below.
Thanks,
On Tue, Dec 25, 2018 at 9:27 AM Long Cheng wrote:
>
> In DMA engine framework, add 8250 uart dma to support MediaTek uart.
> If MediaTek uart enabled(SERIAL_8250_MT6577), and want to improve
> the performance, can enable the function.
>
> Signed-o
On Fri, Dec 21, 2018 at 8:59 PM qii wang wrote:
>
> New i2c registers would have different offsets, so we use different
> offsets array to distinguish different i2c registers version.
>
> Signed-off-by: qii wang
Reviewed-by: Nicolas Boichat
> ---
> drivers/i2c/busse
On Fri, Dec 21, 2018 at 8:59 PM qii wang wrote:
>
> Different speeds have been defined by macros,
> so we use macros definitions.
>
> Signed-off-by: qii wang
Reviewed-by: Nicolas Boichat
> ---
> drivers/i2c/busses/i2c-mt65xx.c |4 ++--
> 1 file changed, 2 in
On Tue, Dec 25, 2018 at 8:06 PM Long Cheng wrote:
>
> Thanks for your comments.
>
> On Tue, 2018-12-25 at 15:16 +0800, Nicolas Boichat wrote:
> > Not a full review, a few comments below.
> >
> > Thanks,
> >
>
> would you like help to full review at th
On Wed, Dec 26, 2018 at 2:35 PM Long Cheng wrote:
>
> On Wed, 2018-12-26 at 08:05 +0800, Nicolas Boichat wrote:
>
> thanks.
>
> > On Tue, Dec 25, 2018 at 8:06 PM Long Cheng wrote:
> > >
> > > Thanks for your comments.
> > >
> > >
If the PMIC ID is unknown, the current code would call
irq_domain_remove and panic, as pmic->irq_domain is only
initialized by mt6397_irq_init.
Return immediately with an error, if the chip ID is unsupported.
Signed-off-by: Nicolas Boichat
---
drivers/mfd/mt6397-core.c | 3 +--
1 file chan
On Tue, Apr 20, 2021 at 11:33 PM Neil Armstrong wrote:
>
> On 26/01/2021 02:17, Nicolas Boichat wrote:
> > Add a basic GPU node for mt8183.
> >
> > Signed-off-by: Nicolas Boichat
> > ---
> > The binding we use with out-of-tree Mali drivers includes more
>
On Tue, Apr 20, 2021 at 9:01 PM Rob Herring wrote:
>
> On Mon, Jan 25, 2021 at 7:18 PM Nicolas Boichat wrote:
> >
> > Define a compatible string for the Mali Bifrost GPU found in
> > Mediatek's MT8183 SoCs.
> >
> > Signed-off-by: Nicolas Boichat
>
gulators and 3 power domains.
Changes in v2:
- Use sram instead of mali_sram as SRAM supply name.
- Rename mali@ to gpu@.
Nicolas Boichat (4):
dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
arm64: dts: mt8183: Add node for the Mali GPU
drm/panfrost: devfreq: Disable devfreq whe
Define a compatible string for the Mali Bifrost GPU found in
Mediatek's MT8183 SoCs.
Signed-off-by: Nicolas Boichat
---
Changes in v12:
- binding: Fix min/maxItems logic (Rob Herring)
Changes in v11:
- binding: power-domain-names not power-domainS-names
Changes in v10:
- Fix the bindi
r now on those GPUs.
Signed-off-by: Nicolas Boichat
Reviewed-by: Tomeu Vizoso
Reviewed-by: Steven Price
---
(no changes since v9)
Changes in v9:
- Explain why devfreq needs to be disabled for GPUs with >1
regulators.
Changes in v8:
- Use DRM_DEV_INFO instead of ERROR
Changes in v7
Add a basic GPU node for mt8183.
Signed-off-by: Nicolas Boichat
---
The binding we use with out-of-tree Mali drivers includes more
clocks, this is used for devfreq: the out-of-tree driver switches
clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
switches clk_mux back to
Add support for MT8183's G72 Bifrost.
Signed-off-by: Nicolas Boichat
Reviewed-by: Tomeu Vizoso
Reviewed-by: Steven Price
---
(no changes since v7)
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- Context conflicts, reflow the code.
- Use ARRAY_SIZE for power domain
On Mon, Feb 15, 2021 at 9:12 AM Ian Lance Taylor wrote:
>
> On Sun, Feb 14, 2021 at 4:38 PM Dave Chinner wrote:
> >
> > On Fri, Feb 12, 2021 at 03:54:48PM -0800, Darrick J. Wong wrote:
> > > On Sat, Feb 13, 2021 at 10:27:26AM +1100, Dave Chinner wrote:
> > >
> > > > If you can't tell from userspa
On Mon, Feb 15, 2021 at 11:42 PM Luis Henriques wrote:
>
> Nicolas Boichat reported an issue when trying to use the copy_file_range
> syscall on a tracefs file. It failed silently because the file content is
> generated on-the-fly (reporting a size of zero) and copy_file_range needs
On Wed, Feb 24, 2021 at 6:44 PM Nicolas Boichat wrote:
>
> On Wed, Feb 24, 2021 at 6:22 PM Luis Henriques wrote:
> >
> > On Tue, Feb 23, 2021 at 08:00:54PM -0500, Olga Kornievskaia wrote:
> > > On Mon, Feb 22, 2021 at 5:25 AM Luis Henriques wrote:
> > > >
h
documentation]
Signed-off-by: Nicolas Boichat
---
I'm trying to revive Antti's patch [1], as we are hitting similar issue
with rt5677 driver. I only updated the commit message and documentation,
I kept both Signed-off-by and From lines, with a small note highlighting
my changes, let me kn
1e4
[2.569613] [] kernel_init+0x10/0xd4
Signed-off-by: Nicolas Boichat
---
sound/soc/codecs/rt5677.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index 31d969a..3007d13 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc
port only.
Signed-off-by: Nicolas Boichat
---
There are other "quirks" that we could add to reduce further
enumeration time (e.g. reduce USB debounce time, reduce TRSTRCY
to 10ms instead of 50ms as used currently), but the logic is quite
similar, so it'd be good to have this reviewed
On Thu, May 24, 2018 at 12:39 AM, Greg Kroah-Hartman
wrote:
> On Wed, May 23, 2018 at 10:03:55AM -0400, Alan Stern wrote:
>> On Wed, 23 May 2018, Nicolas Boichat wrote:
>>
>> > The "old" enumeration scheme is considerably faster (it takes
>> > ~29
d set
device back to NORMAL mode once this call returns.
Signed-off-by: Haridhar Kalvala
Reviewed-by: Dmitry Torokhov
Signed-off-by: Nicolas Boichat
---
drivers/hid/hid-google-hammer.c | 14 ++
1 file changed, 14 insertions(+)
Changes from version on Chromium OS gerrit
(https://chr
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu wrote:
>
> From: Owen Chen
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new AP
On Mon, Mar 11, 2019 at 11:48 AM Hsin-Hsiung Wang
wrote:
>
> In order to support different types of irq design, we decide to add
> separate irq drivers for different design and keep mt6397 mfd core
> simple and reusable to all generations of PMICs so far.
>
> Signed-off-by: Hsin-Hsiung Wang
> ---
+Claire Chang who found some issue with this patch.
On Mon, Mar 11, 2019 at 11:48 AM Hsin-Hsiung Wang
wrote:
>
> This adds support for the MediaTek MT6358 PMIC. This is a
> multifunction device with the following sub modules:
>
> - Regulator
> - RTC
> - Codec
> - Interrupt
>
> It is interfaced to
[2.863922] arm_v7s_alloc_pgtable+0x114/0x17c
[2.868354] alloc_io_pgtable_ops+0x3c/0x78
...
Fixes: e5fc9753b1a8314 ("iommu/io-pgtable: Add ARMv7 short descriptor support")
Signed-off-by: Nicolas Boichat
---
I only tested this on top of my other series
(https://patchwork.kernel.org/patc
On Fri, Mar 29, 2019 at 2:46 PM Andrew-sh.Cheng
wrote:
>
> This API will get voltage as input parameter.
> Search all opp items for the item which with max frequency,
> and the voltae is smaller than provided voltage.
>
> Signed-off-by: Andrew-sh.Cheng
> ---
> drivers/opp/core.c | 55
>
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