Re: [PATCH] mips: Remove uneeded line in cmp_smp_finish

2014-07-21 Thread Paul Burton
On Sat, Jul 19, 2014 at 05:33:16PM -0400, Nick Krause wrote: On Sat, Jul 19, 2014 at 8:05 AM, Paul Bolle pebo...@tiscali.nl wrote: On Sat, 2014-07-19 at 01:10 -0400, Nicholas Krause wrote: This patch removes a unneeded line from this file as stated by the fix me in this file.

Re: smp-cmp.c: CDFIXMES

2014-07-23 Thread Paul Burton
On Wed, Jul 23, 2014 at 12:40:59AM -0400, Nick Krause wrote: Are the lines with CDFIXME still needed? If not please tell me as I will send in a patch removing these two from this file in order to help you guys out :). Cheers Nick Hi Nick, I imagine the only answer any of us can give you is

Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.

2014-10-08 Thread Paul Burton
On Tue, Oct 07, 2014 at 04:59:03PM -0700, David Daney wrote: On 10/07/2014 04:20 PM, Ralf Baechle wrote: On Mon, Oct 06, 2014 at 02:18:19PM -0700, David Daney wrote: As an alternative, if the space of possible instruction with a delay slot is sufficiently small, all such instructions could

Re: [PATCH 2/3] MIPS: Setup an instruction emulation in VDSO protected page instead of user stack

2014-10-06 Thread Paul Burton
On Fri, Oct 03, 2014 at 08:17:30PM -0700, Leonid Yegoshin wrote: Historically, during FPU emulation MIPS runs live BD-slot instruction in stack. This is needed because it was the only way to correctly handle branch exceptions with unknown COP2 instructions in BD-slot. Now there is an

Re: [PATCH] MIPS: mips-cm: CM regions are disabled at boot

2014-11-20 Thread Paul Burton
On Thu, Nov 20, 2014 at 01:29:00PM +0100, Niklas Svensson wrote: Each CM_REGION_TARGET is set to disabled at boot, That part is true... so there is no need to disable the matching CM_GCR_REG explicitly. ...however there is no guarantee that the bootloader, or another kernel, or some other

[PATCH 01/10] binfmt_elf: hoist ELF program header loading to a function

2014-09-11 Thread Paul Burton
duplication, this is part of preparing to load the ELF interpreter headers earlier such that they can be examined before it's too late to return an error from an exec syscall. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- fs/binfmt_elf.c | 99

[PATCH 06/10] MIPS: ensure Config5.UFE is clear on boot

2014-09-11 Thread Paul Burton
As is done for UFR, ensure that userland cannot directly manipulate the mode by clearing the UFE bit during boot. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/kernel/cpu-probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/cpu-probe.c b

[PATCH 07/10] MIPS: support for hybrid FPRs

2014-09-11 Thread Paul Burton
the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/elf.h | 3 +++ arch/mips/include/asm/fpu.h | 49 +++-- arch/mips

[PATCH 08/10] MIPS: ELF: add definition for the .MIPS.abiflags section

2014-09-11 Thread Paul Burton
expectations of the floating point mode. This patch introduces a definition of the structure of this section and the program header, for use in a subsequent patch. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/elf.h | 25 + 1 file changed, 25 insertions

[PATCH 02/10] binfmt_elf: load interpreter program headers earlier

2014-09-11 Thread Paul Burton
is intended. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- fs/binfmt_elf.c | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c index 64ca110..61dabe0 100644 --- a/fs/binfmt_elf.c +++ b/fs/binfmt_elf.c

[PATCH 04/10] MIPS: define bits introduced for hybrid FPRs

2014-09-11 Thread Paul Burton
Add definitions for the FRE UFE bits in Config5, and the FREP bit in FPIR. These bits are used to support a hybrid FPR scheme allowing a mixture of FP32 FP64 code to execute within a task. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/mipsregs.h | 3 +++ 1 file

[PATCH 00/10] MIPS O32 new FP ABI support

2014-09-11 Thread Paul Burton
to test the implementation of hybrid FPRs by forcing all code that can operate in that mode to do so, which is usually avoided due to the overhead of trapping emulating. Paul Burton (10): binfmt_elf: hoist ELF program header loading to a function binfmt_elf: load interpreter program headers

[PATCH 05/10] MIPS: detect presence of the FRE UFR bits

2014-09-11 Thread Paul Burton
Detect the presence of the Config5 FRE UFE bits, as indicated by the FREP bit in FPIR. Record this as a CPU option bit, and provide a cpu_has_fre macro to ease checking of that option bit. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/cpu-features.h | 4 arch

[PATCH 03/10] binfmt_elf: allow arch code to examine PT_LOPROC ... PT_HIPROC headers

2014-09-11 Thread Paul Burton
state observed from the architecture specific program headers. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- fs/Kconfig.binfmt | 3 +++ fs/binfmt_elf.c | 36 -- include/linux/elf.h | 73 + 3 files changed, 110

[PATCH 09/10] MIPS: ELF: set FP mode according to .MIPS.abiflags

2014-09-11 Thread Paul Burton
This patch reads the .MIPS.abiflags section when it is present, and sets the FP mode of the task accordingly. Any loaded ELF files which do not contain a .MIPS.abiflags section will continue to observe the previous behaviour, that is FR=1 if EF_MIPS_FP64 is set else FR=0. Signed-off-by: Paul

[PATCH 10/10] MIPS: Kconfig option to better exercise/debug hybrid FPRs

2014-09-11 Thread Paul Burton
FPR scheme, so debugging the hybrid FPR implementation can be eased by forcing all such code to use it. This is undesirable in general due to the trap emulate overhead of the hybrid FPR implementation, but is a very useful option to have for debugging. Signed-off-by: Paul Burton paul.bur

Re: [PATCH v2 0/3] MIPS executable stack protection

2014-10-09 Thread Paul Burton
On Thu, Oct 09, 2014 at 03:18:56PM -0700, Leonid Yegoshin wrote: The recent discussions on this subject, including many comments from Imgtec e-mail addresses, brought to light the need to use an instruction set emulator for newer MIPSr6 ISA processors. In Imgtec I am only one who works on

Re: [PATCH 2/3] MIPS: Add full ISA emulator.

2014-12-04 Thread Paul Burton
Nice work David, I like this approach. It's so much simpler than hacking atop the current dsemul code. I also imagine this could be reused for emulation of instructions removed in r6, when running pre-r6 userland binaries on r6 systems. On Wed, Dec 03, 2014 at 06:21:36PM -0800, David Daney wrote:

Re: [PATCH_V2 00/34] jz4780 CI20 support

2015-02-04 Thread Paul Burton
made but which the patches indicate I authored. So please, if you should see fit to modify any of my patches in the future, do the above things first. Thanks, Paul Paul Burton (34): dt: Add Ingenic Semiconductor vendor prefix MIPS: jz4740: require include DT MIPS: irq_cpu: declare

Re: [PATCH] MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS

2015-01-18 Thread Paul Burton
On Tue, Jan 13, 2015 at 01:12:22PM +, Markos Chandras wrote: Hi, I think the MIPS,prctl in the title should be MIPS: prctl I used the comma to denote a list - that is, this change affects both MIPS the generic prctl code. To me your MIPS: prctl suggestion would indicate that the changes

Re: [PATCH 0/2] New fix for icache coherency race

2015-04-08 Thread Paul Burton
On Thu, Feb 26, 2015 at 02:16:01PM +0100, Lars Persson wrote: This patch set proposes an improved fix for the race condition that originally was fixed in commit 2a4a8b1e5d9d (MIPS: Remove race window in page fault handling). I have used the flush_icache_page API that is marked as deprecated

Re: [PATCH 1/2] MIPS: MSA: bugfix - disable MSA during thread switch correctly

2015-05-21 Thread Paul Burton
On Tue, May 19, 2015 at 02:13:51PM -0700, Leonid Yegoshin wrote: During thread cloning the new (child) thread should have MSA disabled even at first thread entry. So, the code to disable MSA is moved from macro 'switch_to' to assembler function 'resume' before it switches kernel stack to

[PATCH v3 1/3] MIPS: declare MSA MI10 instruction formats

2015-06-22 Thread Paul Burton
From: Leonid Yegoshin leonid.yegos...@imgtec.com Declare a struct describing the MSA MI10 instruction format used for ld st instructions, for use by subsequent patches. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- Changes in v3: - Split this out into a separate patch Changes in v2

[PATCH v3 3/3] MIPS: MSA unaligned memory access support

2015-06-22 Thread Paul Burton
message. - General formatting cleanups.] Signed-off-by: Paul Burton paul.bur...@imgtec.com --- Changes in v3: - Remove #ifdef's. - Move msa_op into enum major_op rather than #define. - Replace msa_{to,from}_wd with {read,write}_msa_wr_{b,h,w,l} and the format-agnostic wrappers, removing the custom

[PATCH v3 2/3] MIPS: introduce accessors for MSA vector registers

2015-06-22 Thread Paul Burton
. The accessors will be used in a later patch. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- Changes in v3: - New patch Changes in v2: None arch/mips/include/asm/asmmacro.h | 114 +++ arch/mips/include/asm/msa.h | 80 +++ arch/mips

[PATCH v3 0/3] MSA unaligned memory access support

2015-06-22 Thread Paul Burton
MSA MI10 instruction formats MIPS: MSA unaligned memory access support Paul Burton (1): MIPS: introduce accessors for MSA vector registers arch/mips/include/asm/asmmacro.h | 114 ++ arch/mips/include/asm/msa.h | 80 ++ arch

Re: [PATCH 1/3] MIPS: R6: Use lightweight SYNC instruction in smp_* memory barriers

2015-06-02 Thread Paul Burton
Hi Leonid, On Mon, Jun 01, 2015 at 05:09:34PM -0700, Leonid Yegoshin wrote: This instructions were specifically designed to work for smp_*() sort of memory barriers in MIPS R2/R3/R5 and R6. Unfortunately, it's description is very cryptic and is done in HW engineering style which prevents

[PATCH v5 00/37] JZ4780 CI20 support

2015-05-24 Thread Paul Burton
/mips/jz4740 can be shared. The series applies atop v4.1-rc4. Review appreciated, and hopefully this can make it in for v4.2. Paul Burton (37): devicetree/bindings: add Ingenic Semiconductor vendor prefix devicetree/bindings: add Qi Hardware vendor prefix MIPS: JZ4740: introduce

[PATCH v5 04/37] MIPS: ingenic: add newer vendor IDs

2015-05-24 Thread Paul Burton
from the JZ4740. Signed-off-by: Paul Burton paul.bur...@imgtec.com Co-authored-by: Paul Cercueil p...@crapouillou.net Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ralf Baechle r...@linux-mips.org Cc: linux-m...@linux-mips.org --- Changes in v5: None Changes in v4: None Changes in v3: - New patch

[PATCH v5 14/37] MIPS: JZ4740: drop intc debugfs code

2015-05-24 Thread Paul Burton
The debugfs code becomes a nuisance when attempting to avoid globals, since the interrupt controller probe function run too early for it to be safe to create the debugfs files. Drop it. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner t

[PATCH v5 03/37] MIPS: JZ4740: introduce CONFIG_MACH_INGENIC

2015-05-24 Thread Paul Burton
In preparation for supporting Ingenic SoCs other than the JZ4740, introduce MACH_INGENIC to Kconfig move MACH_JZ4740 to a separate entry selected by the board when appropriate. This allows MACH_INGENIC to be used to enable things generic across Ingenic SoCs. Signed-off-by: Paul Burton paul.bur

[PATCH v5 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix

2015-05-24 Thread Paul Burton
Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based SoCs. Simply use 'ingenic'. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v5 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller

2015-05-24 Thread Paul Burton
When probing the interrupt controller, register an IRQ domain such that the interrupts can be translated by devicetree code thus used from devicetree. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner t...@linutronix.de Cc: Jason Cooper

[PATCH v5 35/37] MIPS: JZ4740: use Ingenic SoC UART driver

2015-05-24 Thread Paul Burton
Remove the serial support from arch/mips/jz4740 make use of the new Ingenic SoC UART driver. This is done for both regular early console output. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter

[PATCH] MIPS: optimise non-EVA kernel user memory accesses

2015-05-24 Thread Paul Burton
(CONFIG_EVA). This reduces the size of a malta_defconfig kernel built using GCC 4.9.2 by approximately 33KB (from 5995072 to 5962304 bytes). Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Markos Chandras markos.chand...@imgtec.com Cc: Ralf Baechle r...@linux-mips.org Cc: linux-kernel

[PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support

2015-05-24 Thread Paul Burton
Support the Ingenic JZ4780 SoC using the existing code under arch/mips/jz4740 now that it has been generalised sufficiently. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de

[PATCH v5 32/37] MIPS: JZ4740: only detect RAM size if not specified in DT

2015-05-24 Thread Paul Burton
. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ralf Baechle r...@linux-mips.org Cc: linux-m...@linux-mips.org --- Changes in v5: None Changes in v4: None Changes in v3: - Rebase. Changes in v2: None arch/mips/Kconfig | 1 + arch/mips/jz4740

[PATCH v5 37/37] MIPS: ingenic: initial MIPS Creator CI20 support

2015-05-24 Thread Paul Burton
Add an initial device tree for the Ingenic JZ4780 based MIPS Creator CI20 board. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mark Rutland mark.rutl...@arm.com Cc

[PATCH v5 33/37] devicetree: document Ingenic SoC UART binding

2015-05-24 Thread Paul Burton
Add binding documentation for the UARTs found in Ingenic SoCs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mark Rutland

[PATCH v5 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks

2015-05-24 Thread Paul Burton
for the aforementioned further commits to make use of. Signed-off-by: Paul Burton paul.bur...@imgtec.com Co-authored-by: Paul Cercueil p...@crapouillou.net Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mike Turquette mturque...@linaro.org Cc: Stephen Boyd sb...@codeaurora.org Cc: linux-...@vger.kernel.org

[PATCH v5 20/37] MIPS: JZ4740: support newer SoC interrupt controllers

2015-05-24 Thread Paul Burton
Allow the interrupt controllers of the JZ4770, JZ4775 JZ4780 SoCs to be probed via devicetree, supporting the 64 interrupts they provide. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner t...@linutronix.de Cc: Jason Cooper ja

[PATCH v5 30/37] clk: ingenic: add JZ4780 CGU support

2015-05-24 Thread Paul Burton
Add support for the clocks provided by the CGU in the Ingenic JZ4780 SoC, making use of the SoC-agnostic CGU code to do the heavy lifting. Signed-off-by: Paul Burton paul.bur...@imgtec.com Co-authored-by: Paul Cercueil p...@crapouillou.net Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mike Turquette

[PATCH v5 28/37] MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu

2015-05-24 Thread Paul Burton
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions there for such consistency. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc

[PATCH v5 27/37] MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu

2015-05-24 Thread Paul Burton
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move jz4740_clock_set_wait_mode for such consistency. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc

[PATCH v5 31/37] MIPS: JZ4740: remove clock.h

2015-05-24 Thread Paul Burton
The only thing remaining in arch/mips/jz4740/clock.h is declarations of the jz4740_clock_{suspend,resume} functions. Move these to arch/mips/include/asm/mach-jz4740/clock.h for consistency with similar functions, and remove the redundant arch/mips/jz4740/clock.h header. Signed-off-by: Paul Burton

[PATCH v5 22/37] MIPS: JZ4740: call jz4740_clock_init earlier

2015-05-24 Thread Paul Burton
Call jz4740_clock_init before any uses of jz4740_clock_bdata occur. This is in preparation for replacing uses of that struct with calls to clk_get_rate, which will allow the clocks to be migrated towards common clock framework devicetree. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc

[PATCH v5 23/37] MIPS: JZ4740: replace use of jz4740_clock_bdata

2015-05-24 Thread Paul Burton
Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate for the appropriate clock. This is in preparation for migrating the clocks towards common clock framework devicetree. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ralf Baechle

[PATCH v5 21/37] irqchip: move Ingenic SoC intc driver to drivers/irqchip

2015-05-24 Thread Paul Burton
Move the driver for Ingenic SoC interrupt controllers into drivers/irqchip where it belongs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner t...@linutronix.de Cc: Jason Cooper ja...@lakedaemon.net Cc: Ralf Baechle r...@linux-mips.org

[PATCH v5 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT

2015-05-24 Thread Paul Burton
Use the generic irqchip_init function to probe irqchip drivers using DT, and add the appropriate node to the JZ4740 devicetree in place of the call to mips_cpu_irq_init. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v5 08/37] MIPS: JZ4740: use generic plat_irq_dispatch

2015-05-24 Thread Paul Burton
Make use of the generic plat_irq_dispatch function introduced by commit 85f7cdacbb81 MIPS: Provide a generic plat_irq_dispatch, in order to reduce unnecessary code duplication. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ralf Baechle r...@linux

[PATCH v5 12/37] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT

2015-05-24 Thread Paul Burton
Rather than hardcoding the IRQ number used to cascade interrupts from the SoC interrupt controller to the CPU interrupt controller, read that IRQ number from the DT describing the system. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner

[PATCH v5 10/37] devicetree: document Ingenic SoC interrupt controller binding

2015-05-24 Thread Paul Burton
Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Jason Cooper ja...@lakedaemon.net Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen

[PATCH v5 05/37] MIPS: JZ4740: require include DT

2015-05-24 Thread Paul Burton
Require a DT for JZ4740 based systems, and add a stub one for the qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed via this DT over time. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc

[PATCH v5 06/37] MIPS: irq_cpu: declare irqchip table entry

2015-05-24 Thread Paul Burton
Allow the MIPS CPU interrupt controller to be probed from DT using the generic __irqchip_of_table for platforms which use irqchip_init. This will avoid such platforms needing to duplicate the compatible string init function pointer. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars

[PATCH v5 34/37] serial: 8250_ingenic: support for Ingenic SoC UARTs

2015-05-24 Thread Paul Burton
is the same as that in arch/mips/jz4740/serial.c - which will shortly be removed. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org Cc: Jiri Slaby jsl...@suse.cz Cc: Lars-Peter Clausen l...@metafoo.de Cc: linux-ser...@vger.kernel.org --- Changes in v5

[PATCH v5 29/37] MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu

2015-05-24 Thread Paul Burton
is removed. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mike Turquette mturque...@linaro.org Cc: Ralf Baechle r...@linux-mips.org Cc: Stephen Boyd sb...@codeaurora.org Cc: linux-...@vger.kernel.org Cc: linux-m...@linux-mips.org --- Changes in v5

[PATCH v5 17/37] MIPS: JZ4740: define IRQ numbers based on number of intc IRQs

2015-05-24 Thread Paul Burton
For interrupts numbered after those of the interrupt controller, define their numbers based upon the number of interrupts provided by the SoC interrupt controller. This is in preparation for supporting newer Ingenic SoCs which provide more interrupts. Signed-off-by: Paul Burton paul.bur

[PATCH v5 18/37] MIPS: JZ4740: read intc base address from DT

2015-05-24 Thread Paul Burton
Read the base address of the SoC interrupt controller from the device tree rather than relying upon the JZ4740_INTC_BASE_ADDR macro, in order to remove the dependency on the asm/mach-jz4740/base.h header. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc

[PATCH v5 02/37] devicetree/bindings: add Qi Hardware vendor prefix

2015-05-24 Thread Paul Burton
Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote (qi_lb60) among other open devices. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v5 16/37] MIPS: JZ4740: support 32 interrupts

2015-05-24 Thread Paul Burton
to register from the interrupt controller probe function. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner t...@linutronix.de Cc: Jason Cooper ja...@lakedaemon.net Cc: Ralf Baechle r...@linux-mips.org Cc: linux-m...@linux-mips.org --- Changes

[PATCH v5 19/37] MIPS: JZ4740: avoid JZ4740-specific naming

2015-05-24 Thread Paul Burton
Rename the functions including jz4740 in their names to be more generic in preparation for supporting further SoCs, and for moving this interrupt controller code to drivers/irqchip. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ralf Baechle r...@linux-mips.org Cc: linux-m...@linux

[PATCH v5 09/37] MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c

2015-05-24 Thread Paul Burton
In preparation for moving the JZ4740 interrupt controller driver to drivers/irqchip, move arch_init_irq into setup.c such that everything remaining in irq.c is related to said JZ4740 interrupt controller. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc

[PATCH v5 11/37] MIPS: JZ4740: probe interrupt controller via DT

2015-05-24 Thread Paul Burton
Declare the JZ4740 interrupt controller for probe via DT using the standard irqchip_init function, and make use of that function to probe the controller by adding the appropriate node to the JZ4740 dtsi. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet

[PATCH v5 15/37] MIPS: JZ4740: remove jz_intc_base global

2015-05-24 Thread Paul Burton
Avoid the need for the global variable jz_intc_base by introducing a struct ingenic_intc_data and passing it around as the IRQ handler data. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Thomas Gleixner t...@linutronix.de Cc: Jason Cooper ja

[PATCH v5 26/37] MIPS,clk: migrate JZ4740 to common clock framework

2015-05-24 Thread Paul Burton
Migrate the JZ4740 the qi_lb60 board to use common clock framework via the new Ingenic SoC CGU driver. Note that the JZ4740-specific debugfs code is removed since common clock framework provides its own debug capabilities. Signed-off-by: Paul Burton paul.bur...@imgtec.com Co-authored-by: Paul

[PATCH v5 24/37] devicetree: add Ingenic CGU binding documentation

2015-05-24 Thread Paul Burton
Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 JZ4780 CGU blocks. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars

[PATCH v6 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT

2015-05-24 Thread Paul Burton
Use the generic irqchip_init function to probe irqchip drivers using DT, and add the appropriate node to the JZ4740 devicetree in place of the call to mips_cpu_irq_init. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

Re: [PATCH 00/15] MIPS Malta DT Conversion

2015-05-25 Thread Paul Burton
On Mon, May 25, 2015 at 02:59:31AM -0500, Rob Landley wrote: On Fri, May 22, 2015 at 10:50 AM, Paul Burton paul.bur...@imgtec.com wrote: This series begins converting the MIPS Malta board to use device tree, which is done with a few goals in mind: - To modernise the Malta board support

Re: [PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support

2015-05-26 Thread Paul Burton
On Mon, May 25, 2015 at 01:03:54PM +0200, Hauke Mehrtens wrote: diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c index 1bed3cb..510fc0d 100644 --- a/arch/mips/jz4740/setup.c +++ b/arch/mips/jz4740/setup.c @@ -83,6 +83,9 @@ arch_initcall(populate_machine); const

[PATCH v2] MIPS: tidy up FPU context switching

2015-05-22 Thread Paul Burton
to the disable_msa call in switch_to not being executed, as reported by Leonid. Signed-off-by: Paul Burton paul.bur...@imgtec.com Reported-by: Leonid Yegoshin leonid.yegos...@imgtec.com --- How about this (lightly tested for the moment) alternative to 10082? Changes in v2: - Introduce lose_fpu_inatomic to skip

[PATCH 15/15] MIPS: malta: setup post-I/O hole RAM on non-EVA

2015-05-22 Thread Paul Burton
without needing to manually specify mem= parameters on the kernel command line. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/mti-malta/malta-dtshim.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta

[PATCH 08/15] of_serial: support for UARTs on I/O ports

2015-05-22 Thread Paul Burton
If the address provided for the UART is of an I/O port rather than a regular memory address, then set the port iotype appropriately and write the address to iobase rather than mapbase. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- drivers/tty/serial/of_serial.c | 7 ++- 1 file

[PATCH 03/15] MIPS: malta: basic DT plumbing

2015-05-22 Thread Paul Burton
Build a DT for the Malta platform into the kernel, load it probe devices from it. The DT is essentially empty at this point, devices will be added in further patches. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/Kconfig | 2 ++ arch/mips/boot/dts/mti

[PATCH 06/15] MIPS: malta: probe interrupt controllers via DT

2015-05-22 Thread Paul Burton
at compile time. In order to support both cases the malta_dt_shim code is added in order to detect whether a GIC is present, adjusting the DT to route interrupts correctly and nop out the GIC node if no GIC is found. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/Kconfig

[PATCH 14/15] MIPS: malta: setup RAM regions via DT

2015-05-22 Thread Paul Burton
line) then generate the DT memory node using the provided values. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts | 4 ++ arch/mips/mti-malta/malta-dtshim.c | 104 + arch/mips/mti-malta/malta-memory.c | 88

[PATCH 02/15] MIPS: include errno.h for ENODEV in mips-cm.h

2015-05-22 Thread Paul Burton
A later patch in this series will include mips-cm.h but does not require errno.h. This leads to a build failure with ENODEV undeclared. Include errno.h from mips-cm.h to pull in the appropriate definition and avoid the build failure. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch

[PATCH 00/15] MIPS Malta DT Conversion

2015-05-22 Thread Paul Burton
maintainable kernel through a combination of the above. Paul Burton (15): MIPS: define GCR_GIC_STATUS register fields MIPS: include errno.h for ENODEV in mips-cm.h MIPS: malta: basic DT plumbing MIPS: i8259: DT support irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE

[PATCH 10/15] MIPS: malta: probe RTC via DT

2015-05-22 Thread Paul Burton
Add the DT node required to probe the RTC, and remove the platform code that was previously doing it. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts | 8 arch/mips/mti-malta/malta-platform.c | 20 2 files changed, 8

[PATCH 07/15] MIPS: remove [SR]ocIt(2) IRQ handling code

2015-05-22 Thread Paul Burton
it. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/msc01_ic.h | 147 arch/mips/kernel/Makefile| 1 - arch/mips/kernel/irq-msc01.c | 159 --- arch/mips/mti-malta/malta-int.c | 53

[PATCH 13/15] MIPS: malta: remove nonsense memory limit

2015-05-22 Thread Paul Burton
are not enabled at once which makes the comment about highmem macros nonsensical. - I can think of no good reason for it, and nor could anyone else I asked. So remove this memsize limit. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/mti-malta/malta-memory.c | 4 1 file

[PATCH 09/15] MIPS: malta: probe UARTs using DT

2015-05-22 Thread Paul Burton
. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts| 51 + arch/mips/configs/malta_defconfig | 1 + arch/mips/configs/malta_kvm_defconfig | 1 + arch/mips/configs/malta_kvm_guest_defconfig | 1 + arch/mips

[PATCH 12/15] MIPS: malta: remove fw_memblock_t abstraction

2015-05-22 Thread Paul Burton
The fw_getmdesc function fw_memblock_t abstraction is only used by Malta, and so far as I can tell serves no purpose beyond making the code less clear than it could be. Remove the useless level of abstraction. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/fw/fw.h

[PATCH 11/15] MIPS: malta: probe pflash via DT

2015-05-22 Thread Paul Burton
CONFIG_MTD_PHYSMAP_OF rather than CONFIG_MTD_PHYSMAP in order to preserve their behaviour. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts| 25 arch/mips/configs/malta_defconfig | 2 +- arch/mips/configs/malta_kvm_defconfig

[PATCH 04/15] MIPS: i8259: DT support

2015-05-22 Thread Paul Burton
Support probing the i8259 programmable interrupt controller, as found on the Malta board, and using its interrupts via device tree. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/i8259.h | 1 + arch/mips/kernel/i8259.c | 43

[PATCH 01/15] MIPS: define GCR_GIC_STATUS register fields

2015-05-22 Thread Paul Burton
Add definitions for the GICEX field in the GCR_GIC_STATUS register to mips-cm.h for use in a later patch. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/mips-cm.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips

[PATCH 05/15] irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE

2015-05-22 Thread Paul Burton
. This leads to conflicts between the GIC interrupts and other interrupt controllers. TODO: convert Malta ( SEAD3) to drop the hardcoded numbers instead Signed-off-by: Paul Burton paul.bur...@imgtec.com --- drivers/irqchip/irq-mips-gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH] MIPS: tidy up FPU context switching

2015-05-21 Thread Paul Burton
Rather than saving the scalar FP or vector context in the assembly resume function, simply call lose_fpu(1) from the switch_to macro in order to save the appropriate context, disabling the FPU MSA. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- How about this (lightly tested

[PATCH v3] MIPS: tidy up FPU context switching

2015-08-03 Thread Paul Burton
to is_msa_enabled()/cpu_has_msa being known-zero at compile time for kernels without MSA support. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- Changes in v3: - Rebase atop current mips-for-linux-next. Changes in v2: - Introduce lose_fpu_inatomic to skip the preempt_{en,dis}able calls and operate

[PATCH] MIPS: c-r4k: remove cpu_foreign_map

2015-08-03 Thread Paul Burton
for MT cores), leaving only the change for systems with a CM. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/smp.h | 1 - arch/mips/kernel/smp.c | 44 +--- arch/mips/mm/c-r4k.c| 2 +- 3 files changed, 2

[PATCH] MIPS: select CONFIG_ARCH_USE_CMPXCHG_LOCKREF for MIPS64

2015-07-30 Thread Paul Burton
loops: 251666 Post-patch: Total loops: 273728 Total loops: 269932 Total loops: 269341 Total loops: 275004 Total loops: 270208 Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/Kconfig| 1 + arch/mips/include/asm/spinlock.h | 5 + 2 files

Re: [PATCH v4 3/3] MIPS: set stack/data protection as non-executable

2015-08-05 Thread Paul Burton
On Wed, Aug 05, 2015 at 04:49:36PM -0700, Leonid Yegoshin wrote: This is a last step of 3 patches which shift FPU emulation out of stack into protected area. So, it disables a default executable stack. Additionally, it sets a default data area non-executable protection. Signed-off-by:

[PATCH 0/6] MIPS CPS SMP fixes, debug cleanups

2015-08-05 Thread Paul Burton
as v3.16, so the fixes in this series are marked likewise. Applies atop v4.2-rc5. Paul Burton (6): MIPS: CPS: use 32b accesses to GCRs MIPS: CPS: stop dangling delay slot from has_mt MIPS: CPS: don't include MT code in non-MT kernels MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than

[PATCH 1/6] MIPS: CPS: use 32b accesses to GCRs

2015-08-05 Thread Paul Burton
necessarily match that of the CPU. The registers accessed (GCR_CL_COHERENCE GCR_CL_ID) should be safe to simply always access using 32b instructions, so do so in order to avoid issues when using a 32b CM with a 64b CPU. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Markos Chandras markos.chand

[PATCH 2/6] MIPS: CPS: stop dangling delay slot from has_mt

2015-08-05 Thread Paul Burton
the mips_cps_boot_vpes caller appropriately. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Markos Chandras markos.chand...@imgtec.com Cc: sta...@vger.kernel.org # 3.16+ --- arch/mips/kernel/cps-vec.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/cps

[PATCH 3/6] MIPS: CPS: don't include MT code in non-MT kernels

2015-08-05 Thread Paul Burton
ASE instructions by later patches. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Markos Chandras markos.chand...@imgtec.com Cc: sta...@vger.kernel.org # 3.16+ --- arch/mips/kernel/cps-vec.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel

[PATCH 5/6] MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2

2015-08-05 Thread Paul Burton
-by: Paul Burton paul.bur...@imgtec.com Cc: Markos Chandras markos.chand...@imgtec.com Cc: sta...@vger.kernel.org # 3.16+ --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index cee5f93..ef248cf 100644 --- a/arch/mips

[PATCH 6/6] MIPS: CPS: drop .set mips64r2 directives

2015-08-05 Thread Paul Burton
are built with a suitable -march= compiler flag. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Markos Chandras markos.chand...@imgtec.com Cc: sta...@vger.kernel.org # 3.16+ --- arch/mips/kernel/cps-vec.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/kernel/cps-vec.S b/arch

[PATCH 4/6] MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT

2015-08-05 Thread Paul Burton
The CONFIG_MIPS_MT symbol can be selected by CONFIG_MIPS_VPE_LOADER in addition to CONFIG_MIPS_MT_SMP. We only want MT code in the CPS SMP boot vector if we're using MT for SMP. Thus switch the config symbol we ifdef against to CONFIG_MIPS_MT_SMP. Signed-off-by: Paul Burton paul.bur...@imgtec.com

Re: [PATCH v4 3/3] MIPS: set stack/data protection as non-executable

2015-08-05 Thread Paul Burton
On Wed, Aug 05, 2015 at 05:23:55PM -0700, Leonid Yegoshin wrote: It is actually any application which requests non-executable stack protection and needs some emulation BEFORE GLIBC cancels that non-executable stack protection due to libraries. If you build all libraries with PT_GNU_STACK

Re: Crash in -next due to 'MIPS: Move FP usage checks into protected_{save, restore}_fp_context'

2015-07-27 Thread Paul Burton
On Mon, Jul 27, 2015 at 08:06:52AM -0700, Guenter Roeck wrote: On Wed, Jul 15, 2015 at 09:09:18AM -0700, Guenter Roeck wrote: Hi, my qemu test for mipsel crashes with next-20150715 as follows. ping ... problem is still seen as of next-20150727. Hi Guenter, Apologies for the delay.

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