Hi,
> -Original Message-
> From: Peter Ujfalusi [mailto:peter.ujfal...@ti.com]
> Sent: Tuesday, April 24, 2018 3:21 PM
> To: Vinod Koul <vinod.k...@intel.com>
> Cc: Lars-Peter Clausen <l...@metafoo.de>; Radhey Shyam Pandey
> <radh...@xilinx.com>; m
This patchset fixes checkpatch and kernel-doc warnings in
xilinx emaclite driver. No functional change.
Radhey Shyam Pandey (5):
net: emaclite: Use __func__ instead of hardcoded name
net: emaclite: Balance braces in else statement
net: emaclite: update kernel-doc comments
net: emaclite
To ensure MDIO bus is not double freed in remove() path
assign lp->mii_bus after MDIO bus registration.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --
Errors are already reported in xemaclite_mdio_setup so avoid
reporting it again.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet
The AXI VDMA core supports Vertical Flip with S2MM as the path when
Enable Vertical Flip (Advanced tab) is selected. This patch series add
DT property for vertical flip and program its state in VDMA start_transfer.
Radhey Shyam Pandey (2):
dt-bindings: dmaengine: xilinx_dma: Add VDMA vertical
Vertical flip state is exported in xilinx_vdma_config and depending
on IP configuration(c_enable_vert_flip) vertical flip state is
programmed in hardware.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
drivers/dma/xilinx/xilinx_dma.c | 22 ++
include
The AXI VDMA core supports Vertical flip in S2MM path when Enable
Vertical Flip (Advanced tab) is selected. To allow vertical flip
programming define an optional 'xlnx,enable-vert-flip' channel
child node property.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
Hi,
> -Original Message-
> From: Peter Ujfalusi [mailto:peter.ujfal...@ti.com]
> Sent: Tuesday, May 29, 2018 8:35 PM
> To: Radhey Shyam Pandey ; Vinod Koul
>
> Cc: Lars-Peter Clausen ; michal.si...@xilinx.com; linux-
> ker...@vger.kernel.org; dmaeng...@vger.kern
> -Original Message-
> From: Peter Ujfalusi [mailto:peter.ujfal...@ti.com]
> Sent: Friday, June 1, 2018 3:54 PM
> To: Radhey Shyam Pandey ; vinod.k...@intel.com
> Cc: l...@metafoo.de; michal.si...@xilinx.com; linux-
> ker...@vger.kernel.org; dmaeng...@vger.kernel.
> -Original Message-
> From: Andrea Merello [mailto:andrea.mere...@gmail.com]
> Sent: Wednesday, June 20, 2018 7:02 PM
> To: Radhey Shyam Pandey
> Cc: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ; dmaeng...@vger.kernel.
h eventually adjusts the transfer size in order to make sure
> all operations start from an aligned address.
>
> Signed-off-by: Andrea Merello
> ---
> Changes in v2:
> - don't introduce copy_mask field, rather rely on already-esistent
> copy_align field. Su
> -Original Message-
> From: Radhey Shyam Pandey
> Sent: Wednesday, June 20, 2018 7:13 PM
> To: Andrea Merello ; vk...@kernel.org;
> dan.j.willi...@intel.com; Michal Simek ; Appana Durga
> Kedareswara Rao ; dmaeng...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infrad
> -Original Message-
> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
> ow...@vger.kernel.org] On Behalf Of Andrea Merello
> Sent: Wednesday, June 20, 2018 2:07 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ;
> -Original Message-
> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
> ow...@vger.kernel.org] On Behalf Of Andrea Merello
> Sent: Wednesday, June 20, 2018 2:07 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ;
> -Original Message-
> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
> ow...@vger.kernel.org] On Behalf Of Andrea Merello
> Sent: Wednesday, June 20, 2018 2:07 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ;
This patchset fixes 64-bit simple CDMA transfer.
It also does some trivial code refactoring.
Radhey Shyam Pandey (3):
dmaengine: xilinx_dma: Refactor axidma channel allocation
dmaengine: xilinx_dma: Refactor axidma channel validation
dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
In AXI CDMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. This fixes simple CDMA operation
mode using 64-bit addressing.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
drivers/dma/xilinx/xilinx_dma.c |6 --
1 files
In axidma start_transfer, prefer checking channel states before
other params i.e pending_list.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx
In axidma alloc_chan_resources merge BD and cyclic BD allocation.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
drivers/dma/xilinx/xilinx_dma.c | 36 ++--
1 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/dma/xilinx
-by: Radhey Shyam Pandey
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index
and receive channels.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 449 +++-
1 file changed, 440 insertions(+), 9 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index c124423..f136e5a 100644
/documentation/ip_documentation/axi_mcdma/v1_0/pg288-axi-mcdma.pdf
Radhey Shyam Pandey (2):
dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP
dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 10 +-
drivers/dma
Hi Rob,
Thanks for the review.
> -Original Message-
> From: Rob Herring
> Sent: Tuesday, August 14, 2018 9:43 PM
> To: Radhey Shyam Pandey
> Cc: vk...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; dan.j.willi...@intel.com; Appana Durga Kedareswara
> Rao ; l.
> -Original Message-
> From: Peter Ujfalusi
> Sent: Wednesday, August 15, 2018 4:27 PM
> To: dan.j.willi...@intel.com; vk...@kernel.org
> Cc: dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org;
> l...@metafoo.de; Radhey Shyam Pandey
> Subject: [RFC] dmaeng
> -Original Message-
> From: Vinod
> Sent: Tuesday, August 21, 2018 9:20 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; Michal Simek ; Appana
> Durga Kedareswara Rao ; l...@metafoo.de;
> dmaeng...@vger.kernel.org; linux-arm-ker...@lists.infrad
> -Original Message-
> From: Vinod
> Sent: Tuesday, August 21, 2018 9:26 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; Michal Simek ; Appana
> Durga Kedareswara Rao ; l...@metafoo.de;
> dmaeng...@vger.kernel.org; linux-arm-ker...@lists.infrad
> -Original Message-
> From: Vinod
> Sent: Wednesday, August 29, 2018 9:31 AM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; Michal Simek ; Appana
> Durga Kedareswara Rao ; l...@metafoo.de;
> dmaeng...@vger.kernel.org; linux-arm-ker...@lists.infrad
> Vinod,
>
> On 2018-08-29 19:22, Vinod wrote:
> + * 2. use dmaengine_desc_attach_metadata() to attach the buffer to
> the
> + * descriptor
> + * 3. submit the transfer
> + * - DMA_DEV_TO_MEM:
> + * 1. prepare the descriptor (dmaengine_prep_*)
> + * 2.
> > > > > - xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw-
> > > > >src_addr);
> > > > > - xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw-
> > > > >dest_addr);
> > > > > + xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
> > > > (dma_addr_t)
> > > > > +
> > > > Yeah that part was clear but the implementation can be better..
> > I thought over it and it seems having a new interface dma_ctrl_write_64
> > taking lsb and msb bits input looks better and scalable. It will be similar
> > to existing vdma_desc_write_64 impl. I will send v2 if it looks
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:42 PM
> To: Radhey Shyam Pandey <radh...@xilinx.com>
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Kedareswara Rao <
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:35 PM
> To: Radhey Shyam Pandey <radh...@xilinx.com>; Rob Herring
> <r...@kernel.org>; devicet...@vger.kernel.org
> Cc: dan.j.willi...@inte
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:41 PM
> To: Radhey Shyam Pandey <radh...@xilinx.com>
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Kedareswara Rao <
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:39 PM
> To: Radhey Shyam Pandey <radh...@xilinx.com>
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Kedareswara Rao <
Schedule tasklet with high priority to ensure that callback processing
is prioritized. It improves throughput for netdev dma clients.
Signed-off-by: Radhey Shyam Pandey <radh...@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Increase AXI DMA transaction segments count to ensure that even in
high load we always get a free segment in prepare descriptor for a
DMA_SLAVE transaction.
Signed-off-by: Radhey Shyam Pandey <radh...@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c |2 +-
1 files changed, 1 insertions
Read DT property to check if AXI DMA is connected to axithernet.
If connected pass AXI4-Stream control words to netdev dma client.
It is mandatory that netdev dma client reserve initial memory for
max supported control words in callback_param.
Signed-off-by: Radhey Shyam Pandey <r
-by: Radhey Shyam Pandey <radh...@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 36e1ab9..518465e 100644
--- a/drivers/dma/xilinx/xilinx
Add an optional AXI DMA property 'has_axieth_connected'. This can be
specified to indicate that AXI DMA is connected to AXI Ethernet in
hardware design and dma driver needs to do some additional handling.
Signed-off-by: Radhey Shyam Pandey <radh...@xilinx.com>
---
.../devicetree/bindin
integration with axiethernet network driver. Once this patchset
is reviewed I will send separate patchset for axiethernet driver.
Radhey Shyam Pandey (6):
dt-bindings: dma: xilinx_dma: Add optional property
has_axieth_connected
dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured.
Signed-off-by: Radhey Shyam Pandey <radh...@xilinx.
> -Original Message-
> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
> ow...@vger.kernel.org] On Behalf Of Andrea Merello
> Sent: Wednesday, June 20, 2018 2:07 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ;
This patch fixes below checkpatch warnings-
WARNING: Block comments use a trailing */ on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: networking block comments don't use an empty /* line,
use /* Comment
Signed-off-by: Radhey Shyam Pandey
---
Changes from v1
y_id=%i, reg=%x) == %x\n",
WARNING: Prefer using '"%s...", __func__' to using 'xemaclite_mdio_write',
this function's name, in a string
+ "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
Cha
This patch fixes below checkpatch checks-
CHECK: spaces preferred around that '*' (ctx:VxV)
CHECK: No space is necessary after a cast
Signed-off-by: Radhey Shyam Pandey
---
Changes from v1:
- None
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 27 +
1
> -Original Message-
> From: Vinod Koul
> Sent: Sunday, November 11, 2018 2:30 AM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; Michal Simek ; Appana
> Durga Kedareswara Rao ; dmaeng...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-k
.
Radhey Shyam Pandey (4):
dmaengine: xilinx_dma: Refactor axidma channel allocation
dmaengine: xilinx_dma: Refactor axidma channel validation
dmaengine: xilinx_dma: Introduce helper macro for preparing dma
address
dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
drivers/dma
In axidma start_transfer, prefer checking channel states before
other params i.e pending_list. No functional change.
Signed-off-by: Radhey Shyam Pandey
---
Changes for v2:
Modified the commit message to mark it as non-functional change.
---
drivers/dma/xilinx/xilinx_dma.c |4 ++--
1 files
In axidma alloc_chan_resources merge BD and cyclic BD allocation.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
Changes for v2:
None
---
drivers/dma/xilinx/xilinx_dma.c | 36 ++--
1 files changed, 18 insertions(+), 18 deletions(-)
diff
This patch introduces the xilinx_prep_dma_addr_t macro which prepares
dma_addr_t from hardware buffer descriptor LSB and MSB fields. It will
be used in simple dma 64-bit programming sequence.
Signed-off-by: Radhey Shyam Pandey
---
Changes for v2:
New patch- Preparatory change for 4/4 fix
In AXI CDMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. This fixes simple CDMA operation
mode using 64-bit addressing.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
Changes for v2:
Use helper macro for preparing dma_addr_t
Thanks for the review.
> On 31-07-18, 23:16, Radhey Shyam Pandey wrote:
> > struct xilinx_dma_config {
> > @@ -402,6 +470,7 @@ struct xilinx_dma_config {
> > int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
> > struct clk **t
> -Original Message-
> From: Andrea Merello
> Sent: Friday, November 16, 2018 7:26 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; dmaeng...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; Radhey Shyam Pandey
> ; Andrea Merello
> Subject: [
Hi,
> -Original Message-
> From: Peter Ujfalusi [mailto:peter.ujfal...@ti.com]
> Sent: Tuesday, April 24, 2018 3:21 PM
> To: Vinod Koul
> Cc: Lars-Peter Clausen ; Radhey Shyam Pandey
> ; michal.si...@xilinx.com; linux-
> ker...@vger.kernel.org; dmaeng...@vger.kern
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:35 PM
> To: Radhey Shyam Pandey ; Rob Herring
> ; devicet...@vger.kernel.org
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Ked
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:39 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Kedareswara Rao ; Radhey Shyam Pandey
> ; l.
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:41 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Kedareswara Rao ; Radhey Shyam Pandey
> ; l.
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Wednesday, April 11, 2018 2:42 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; michal.si...@xilinx.com; Appana Durga
> Kedareswara Rao ; Radhey Shyam Pandey
> ; l.
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma
-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 36e1ab9..518465e 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma
Add an optional AXI DMA property 'has_axieth_connected'. This can be
specified to indicate that AXI DMA is connected to AXI Ethernet in
hardware design and dma driver needs to do some additional handling.
Signed-off-by: Radhey Shyam Pandey
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt
integration with axiethernet network driver. Once this patchset
is reviewed I will send separate patchset for axiethernet driver.
Radhey Shyam Pandey (6):
dt-bindings: dma: xilinx_dma: Add optional property
has_axieth_connected
dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev
Schedule tasklet with high priority to ensure that callback processing
is prioritized. It improves throughput for netdev dma clients.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dma
Increase AXI DMA transaction segments count to ensure that even in
high load we always get a free segment in prepare descriptor for a
DMA_SLAVE transaction.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff
Read DT property to check if AXI DMA is connected to axithernet.
If connected pass AXI4-Stream control words to netdev dma client.
It is mandatory that netdev dma client reserve initial memory for
max supported control words in callback_param.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma
> -Original Message-
> From: Paul Thomas
> Sent: Saturday, January 16, 2021 1:00 AM
> To: Radhey Shyam Pandey
> Cc: Dan Williams ; Vinod Koul
> ; Michal Simek ; Matthew Murrian
> ; Romain Perier
> ; Krzysztof Kozlowski ; Marc
> Ferland ; Sebastian von Ohr
&g
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
Changes for v2:
- Include fixes tag.
- Keep typecasting changes in the same line to increase readability.
---
drivers/dma/xilinx/xilinx_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xi
incompatible_param.
Fixes: 1a9e7a03c761 ("dmaengine: vdma: Add support for mulit-channel dma mode")
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
Changes for v2:
- Include fixes tag.
---
drivers/dma/xilinx/xilinx_dma.c | 3 ++-
1 file changed, 2 insertions(+),
ccess Engine
driver support")
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
Changes for v2:
- Include fixes tag.
---
drivers/dma/xilinx/xilinx_dma.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/
This patch series fix coverity warnings for xilinx_dma driver.
No functional change. These patches are picked from xilinx
linux tree and posted for upstream.
Changes for v2:
- Include fixes tag.
- In 3/3 patch keep typecasting changes in the same line.
Shravya Kumbham (3):
dmaengine:
This patch series fix coverity warnings for xilinx_dma driver.
No functional change. These patches are picked from xilinx
linux tree and posted for upstream.
Shravya Kumbham (3):
dmaengine: xilinx_dma: check dma_async_device_register return value
dmaengine: xilinx_dma: fix incompatible param
From: Shravya Kumbham
dma_async_device_register() can return non-zero error code. Add
condition to check the return value of dma_async_device_register
function and handle the error path.
Addresses-Coverity: Event check_return.
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
From: Shravya Kumbham
Typecast the fls(width -1) with (enum dmaengine_alignment) in
xilinx_dma_chan_probe function to fix the coverity warning.
Addresses-Coverity: Event mixed_enum_type.
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 3
incompatible_param.
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index e41435be5b79..cf75e2af6381 100644
> -Original Message-
> From: Denis Kirjanov
> Sent: Tuesday, November 17, 2020 6:43 PM
> To: Radhey Shyam Pandey
> Cc: da...@davemloft.net; net...@vger.kernel.org; k...@kernel.org;
> Michal Simek ; mchehab+sams...@kernel.org;
> gre...@linuxfoundation.org; nicola
> -Original Message-
> From: Paul Thomas
> Sent: Monday, December 28, 2020 10:14 AM
> To: Dan Williams ; Vinod Koul
> ; Michal Simek ; Radhey Shyam
> Pandey ; Matthew Murrian
> ; Romain Perier
> ; Krzysztof Kozlowski ; Marc
> Ferland ; Sebastian von Ohr
&g
> -Original Message-
> From: Jakub Kicinski
> Sent: Sunday, November 8, 2020 1:05 AM
> To: Radhey Shyam Pandey
> Cc: da...@davemloft.net; Michal Simek ;
> net...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; git ; Shravya Kum
Signed-off-by: Radhey Shyam Pandey
---
Changes for v2:
- Change subject_prefix to target net tree.
- Add error handling for mdio_setup and remove phy_read changes.
Error checking of phy_read will be added along with phy_write
in a followup patch. Document the changes in commit description
> -Original Message-
> From: Zhang Changzhong
> Sent: Monday, September 7, 2020 6:32 PM
> To: Radhey Shyam Pandey ; da...@davemloft.net;
> k...@kernel.org; Michal Simek
> Cc: net...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH net-next] net: xil
Introduce helper functions to enable/disable MDIO interface clock. This
change serves a preparatory patch for the coming feature to dynamically
control the management bus clock.
Signed-off-by: Radhey Shyam Pandey
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 ++
drivers/net
as dynamic MDC enable/disable is not supported in hw
we are implementing it in sw. This change doesn't affect any existing
functionality.
Clayton Rayment (1):
net: xilinx: axiethernet: Enable dynamic MDIO MDC
Radhey Shyam Pandey (1):
net: xilinx: axiethernet: Introduce helper functions for MDC
in device reset sequence.
Signed-off-by: Clayton Rayment
Signed-off-by: Radhey Shyam Pandey
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 21 --
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c | 27 ++-
2 files changed, 25 insertions(+), 23 deletions
From: Shravya Kumbham
Add ret variable, conditions to check the return value and it's error
path for of_address_to_resource() and phy_read() functions.
Addresses-Coverity: Event check_return value.
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
drivers/net/ethernet
of
readl_poll_timeout variant.
Signed-off-by: Marc Ferland
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 5429497d3560
This patchset fixes usage of mcdma tx segment and SG capability.
It also make use of readl_poll_timeout_atomic variant.
Marc Ferland (1):
dmaengine: xilinx_dma: use readl_poll_timeout_atomic variant
Matthew Murrian (2):
dmaengine: xilinx_dma: Fix usage of xilinx_aximcdma_tx_segment
ngine driver
support")
Signed-off-by: Matthew Murrian
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_d
t;)
Signed-off-by: Matthew Murrian
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index ade4e6e1a5bd..993297d585c0 100644
--- a/d
> -Original Message-
> From: Markus Elfring
> Sent: Wednesday, September 18, 2019 7:01 PM
> To: net...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; David S.
> Miller ; Hans Ulli Kroll ;
> Hauke Mehrtens ; Linus Walleij
> ; Michal Simek ; Radhey
>
This patchset fixes axidma simple mode 64-bit transfer.
It clears vdma control registers before update, in probe
use devm_platform API and remove clk_get error in case of
EPROBE_DEFER.
Radhey Shyam Pandey (4):
dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer
dmaengine: xilinx_dma
In vdma_channel_set_config clear the delay, frame count and master mask
before updating their new values. It avoids programming incorrect state
when input parameters are different from default.
Signed-off-by: Radhey Shyam Pandey
Acked-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
In AXI DMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. It fixes simple AXI DMA operation
mode using 64-bit addressing.
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions
In dma probe, the driver checks for devm_clk_get return and print error
message in the failing case. However for -EPROBE_DEFER this message is
confusing so avoid it.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
drivers/dma/xilinx/xilinx_dma.c | 19 ++-
1
Replace the chain of platform_get_resource() and devm_ioremap_resource()
with devm_platform_ioremap_resource(). It simplifies the flow and there
is no functional change.
Fixes below cocinelle warning-
WARNING: Use devm_platform_ioremap_resource for xdev -> regs
Signed-off-by: Radhey Shyam Pan
> -Original Message-
> From: Vinod Koul
> Sent: Thursday, September 26, 2019 10:48 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; Michal Simek ;
> nick.graum...@gmail.com; andrea.mere...@gmail.com; Appana Durga
> Kedareswara Rao ; mcg...
> -Original Message-
> From: Vinod Koul
> Sent: Thursday, September 26, 2019 10:51 PM
> To: Radhey Shyam Pandey
> Cc: dan.j.willi...@intel.com; Michal Simek ;
> nick.graum...@gmail.com; andrea.mere...@gmail.com; Appana Durga
> Kedareswara Rao ; mcg...
> -Original Message-
> From: Nicholas Graumann
> Sent: Friday, September 27, 2019 7:27 PM
> To: Radhey Shyam Pandey
> Cc: Vinod Koul ; dan.j.willi...@intel.com; Michal Simek
> ; andrea.mere...@gmail.com; Appana Durga
> Kedareswara Rao ; mcg...@kernel.org;
> d
> -Original Message-
> From: Radhey Shyam Pandey
> Sent: Friday, September 27, 2019 10:46 AM
> To: Vinod Koul
> Cc: dan.j.willi...@intel.com; Michal Simek ;
> nick.graum...@gmail.com; andrea.mere...@gmail.com; Appana Durga
> Kedareswara Rao ; mcg...@kernel.org;
> d
> -Original Message-
> From: Markus Elfring
> Sent: Friday, September 20, 2019 5:01 PM
> To: net...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; David S.
> Miller ; Michal Simek ;
> Radhey Shyam Pandey
> Cc: LKML ; kernel-janit...@vger.kernel.org
> Subj
xilinx axi_emac driver is supported on ZynqMP UltraScale platform(ARM64).
So enable it in kconfig. Basic sanity testing is done on zu+ mpsoc zcu102
evaluation board.
Signed-off-by: Radhey Shyam Pandey
---
drivers/net/ethernet/xilinx/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3
Trivial formatting(keep compatible string one per line, caps change etc).
It doesn't modify the content of the binding.
Signed-off-by: Radhey Shyam Pandey
---
Changes since RFC:
New patch. Trivial formatting (compatible string one per line) as
suggested by Rob in MCDMA RFC series
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