Re: [alsa-devel] [PATCH v3 00/15] ASoC: OMAP: Convert to use dmaengine

and this causes a build break with omap2plus_defconfig. Not sure if this is expected, Most likely not. Tested-by: Ricardo Neri ricardo.n...@ti.com Ricardo -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo

[PATCH 4/6] x86/efi: remove __init attribute from memory mapping functions

Even though these functions are called at kernel boot, they will also be used by the page fault handler to fixup access to BOOT_SERVICES_* regions, which do not have the __init attribute. Signed-off-by: Ricardo Neri ricardo.neri-calde...@linux.intel.com --- arch/x86/include/asm/efi.h | 4

[PATCH 1/6] x86/efi: find mem descriptor from phys address

is consolidated into a single function that three functions mentioned above may call. When checking the validity of the validity of the memory map, use efi_enabled(), provided for this purpose. Signed-off-by: Ricardo Neri ricardo.neri-calde...@linux.intel.com --- arch/x86/platform/efi/efi.c | 21

[PATCH 0/6] Warn about illegal accesses to EFI_BOOT_SERVICES_* memory

for code reuse of the convenience functions that look for the descriptor of a physical memory address when then be used by the proposed solution. Ricardo Neri (6): x86/efi: Add function to obtain mem descriptor from phys address x86/efi: Use efi_memory_descriptor in mem convenience functions x86/efi

[PATCH 2/6] x86/efi: use efi_memory_descriptor in convenience functions

Rather than duplicating the code to lookup for the memory descriptor of a given physical address, use the utility function efi_memory_descriptor. Signed-off-by: Ricardo Neri ricardo.neri-calde...@linux.intel.com --- arch/x86/platform/efi/efi.c | 26 ++ drivers/firmware

[PATCH 3/6] x86/efi: add code to fixup page faults in BOOT_SERVICES_* regions

will not impact a reboot from kexec, as kexec is only concerned about runtime memory regions. Signed-off-by: Ricardo Neri ricardo.neri-calde...@linux.intel.com --- arch/x86/platform/efi/efi.c | 29 + include/linux/efi.h | 8 2 files changed, 37 insertions

[PATCH 5/6] yx86/efi: fixup faults from UEFI firmware

that we will not have false positives as those memory regions are reserved and the kernel cannot use them. Signed-off-by: Ricardo Neri ricardo.neri-calde...@linux.intel.com --- arch/x86/mm/fault.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c

[PATCH 6/6] x86/efi: introduce EFI_BOOT_SERVICES_WARN

service code until after switching to virtual mode). Being more verbose about this kind of illegal access from the firmware increases the likelihood of this kind firmware bugs to be fixed. Signed-off-by: Ricardo Neri ricardo.neri-calde...@linux.intel.com --- arch/x86/Kconfig| 12

Re: [PATCH v2] x86/mm: warn on W+x mappings

On Thu, 2015-10-15 at 12:33 +0200, Borislav Petkov wrote: > Yeah, that's actually a good idea. Why not upstream it for the wider > audience so that people can actually start reporting b0rked UEFIs? > With > a big and nice FW_BUG splat in there... We attempted to upstream in the past but later I

Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM

On Fri, 2017-01-27 at 16:53 +0900, Masami Hiramatsu wrote: > On Wed, 25 Jan 2017 22:07:16 -0800 > Ricardo Neri <ricardo.neri-calde...@linux.intel.com> wrote: > > > Hi Masami, > > > > On Thu, 2017-01-26 at 11:11 +0900, Masami Hiramatsu wrote: > > > On Wed

Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings (fwd)

signed expression compared > >> with zero: seg < 0 > > git remote add linux-review https://github.com/0day-ci/linux > git remote update linux-review > git checkout 574de0de238ef30c816985006f02f7a1dbba92aa > vim +267 arch/x86/lib/insn-kernel.c > > 574de0de Ricar

Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings

On Thu, 2017-01-26 at 09:05 -0800, Andy Lutomirski wrote: > On Wed, Jan 25, 2017 at 9:50 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > On Wed, 2017-01-25 at 13:58 -0800, Andy Lutomirski wrote: > >> On Wed, Jan 25, 2017 at 12:23 PM, Ricardo Ne

Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings

On Wed, 2017-01-25 at 13:58 -0800, Andy Lutomirski wrote: > On Wed, Jan 25, 2017 at 12:23 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > Tasks running in virtual-8086 mode will use 16-bit addressing form > > encodings as described in the Intel 6

Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention

Hi Peter, On Wed, 2017-01-25 at 12:34 -0800, H. Peter Anvin wrote: > On 01/25/17 12:23, Ricardo Neri wrote: > > * SMSW returns the value with which the CR0 register is programmed in > >head_32/64.S at boot time. This is, the following bits are enabed: > >CR0.0 for Pr

Re: [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions

On Wed, 2017-01-25 at 12:38 -0800, H. Peter Anvin wrote: > On 01/25/17 12:23, Ricardo Neri wrote: > > + case UMIP_SMSW: > > + dummy_value = CR0_STATE; > > Unless the user space process is running in 64-bit mode this value > should be & 0x. But wouldn

Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM

Hi Masami, On Thu, 2017-01-26 at 11:11 +0900, Masami Hiramatsu wrote: > On Wed, 25 Jan 2017 12:23:47 -0800 > Ricardo Neri <ricardo.neri-calde...@linux.intel.com> wrote: > > > The function insn_get_reg_offset requires a type to indicate whether > > the re

[v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings

gt; Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricard

[v3 PATCH 10/10] selftests/x86: Add tests for User-Mode Instruction Prevention

kar <ravi.v.shan...@intel.com> Cc: Shuah Khan <sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- tools/testing/selftests/x86/entry_from_vm86.c | 39 ++- 1 file changed,

[v3 PATCH 08/10] x86/traps: Fixup general protection faults caused by UMIP

; Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/kernel/traps.c | 4

[v3 PATCH 09/10] x86: Enable User-Mode Instruction Prevention

Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/Kconfig | 10 ++ arch/x86/kernel/cpu/common.c | 16 +++-

[v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel

com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kern

[v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM

er <adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan.

[v3 PATCH 01/10] x86/mpx: Do not use SIB index if index points to R/ESP

<dave.han...@linux.intel.com> Cc: Adam Buchbinder <adam.buchbin...@gmail.com> Cc: Colin Ian King <colin.k...@canonical.com> Cc: Lorenzo Stoakes <lstoa...@gmail.com> Cc: Qiaowei Ren <qiaowei@intel.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@ke

[v3 PATCH 02/10] x86/mpx: Fail decoding when SIB baseR/EBP is and no displacement is used

lin Ian King <colin.k...@canonical.com> Cc: Lorenzo Stoakes <lstoa...@gmail.com> Cc: Qiaowei Ren <qiaowei@intel.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x8

[v3 PATCH 06/10] x86/cpufeature: Add User-Mode Instruction Prevention definitions

.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.

[v3 PATCH 07/10] x86: Add emulation code for UMIP instructions

org> Cc: Vlastimil Babka <vba...@suse.cz> Cc: Tony Luck <tony.l...@intel.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: lin

[v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention

.shan...@intel.com> Cc: Vlastimil Babka <vba...@suse.cz> Cc: Shuah Khan <sh...@kernel.org> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z Li <liang.z...@intel.com> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Ricardo Neri (10): x86/mpx: Do not use SIB inde

Re: [PATCH v4 03/17] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel

On Thu, 2017-02-23 at 18:54 +0800, kbuild test robot wrote: > >> arch/x86/lib/insn-eval.c:106:21: error: static declaration of > 'insn_get_addr_ref' follows non-static declaration > static void __user *insn_get_addr_ref(struct insn *insn, struct > pt_regs *regs) >

Re: [PATCH v4 01/17] x86/mpx: Do not use SIB index if index points to R/ESP

On Thu, 2017-02-23 at 18:33 -0800, Joe Perches wrote: > On Thu, 2017-02-23 at 14:17 -0800, Ricardo Neri wrote: > > On Thu, 2017-02-23 at 08:24 +0100, Peter Zijlstra wrote: > > > On Wed, Feb 22, 2017 at 10:36:50PM -0800,

Re: [PATCH v4 01/17] x86/mpx: Do not use SIB index if index points to R/ESP

On Thu, 2017-02-23 at 08:24 +0100, Peter Zijlstra wrote: > On Wed, Feb 22, 2017 at 10:36:50PM -0800, Ricardo Neri wrote: > > + /* > > +* A negative offset generally means a error, except > > +* -EDOM, which me

Re: [PATCH v4 15/17] x86/traps: Fixup general protection faults caused by UMIP

On Thu, 2017-02-23 at 10:27 +0100, Peter Zijlstra wrote: > On Wed, Feb 22, 2017 at 10:37:04PM -0800, Ricardo Neri wrote: > > @@ -492,6 +493,9 @@ do_general_protection(struct pt_regs *regs, long > > error_code) > > RCU_LOCKDEP_WARN(!rcu_is_watching(), "

Re: [PATCH v4 15/17] x86/traps: Fixup general protection faults caused by UMIP

On Fri, 2017-02-24 at 11:11 -0800, Andy Lutomirski wrote: > > In a previous version Andy Lutomirsky suggested that > > if (user_mode(regs) && (fixup_umip_exception(regs) == 0)) > > > > was easier to read :). Although at the time fixup_umip_exception > > returned a numeric value. Now it

Re: [PATCH v4 01/17] x86/mpx: Do not use SIB index if index points to R/ESP

On Fri, 2017-02-24 at 09:47 -0500, Nathan Howard wrote: > Also, this code would read better with the inner test > reversed or done first > > if (indx_offset < 0) { > if (indx_offset != -EDOM) >

[PATCH v4 15/17] x86/traps: Fixup general protection faults caused by UMIP

; Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/kernel/traps.c | 4

[PATCH v4 05/17] x86/insn-eval: Add utility function to get segment selector

romium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Rica

[PATCH v4 03/17] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel

adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc

[PATCH v4 16/17] x86: Enable User-Mode Instruction Prevention

Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/Kconfig | 10 ++ arch/x86/kernel/cpu/common.c | 16 +++-

[PATCH v4 11/17] x86/insn-eval: Add support to resolve 16-bit addressing encodings

v <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/lib/insn-eval.c | 156 ++- 1 fi

[PATCH v4 08/17] x86/insn-eval: Add functions to get default operand and address sizes

homas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-ca

[PATCH v4 06/17] x86/insn-eval: Add utility function to get segment descriptor

v <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/lib/insn-eval.c | 61 1

[PATCH v4 14/17] x86/umip: Force a page fault when unable to copy emulated result to user

with SEGV_MAPERR with the offending address. A new function is inspired in force_sig_info_fault is introduced to model the page fault. Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/kernel/umip.c | 45 +++-- 1 file changed, 43 inse

[PATCH v4 12/17] x86/cpufeature: Add User-Mode Instruction Prevention definitions

.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.

[PATCH v4 17/17] selftests/x86: Add tests for User-Mode Instruction Prevention

kar <ravi.v.shan...@intel.com> Cc: Shuah Khan <sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- tools/testing/selftests/x86/entry_from_vm86.c | 39 ++- 1 file changed,

[PATCH v4 10/17] insn/eval: Incorporate segment base in address computation

Adrian Hunter <adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v

[PATCH v4 04/17] x86/insn-eval: Add utility functions to get register offsets

rnel.org> Cc: Adrian Hunter <adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shan

[PATCH v4 13/17] x86: Add emulation code for UMIP instructions

t;sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Cc: Tony Luck <tony.l...@intel.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@ke

[PATCH v4 09/17] x86/insn-eval: Do not use R/EBP as base if mod in ModRM is zero

rnel.org> Cc: Adrian Hunter <adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shan

[PATCH v4 00/17] x86: Enable User-Mode Instruction Prevention

t decodes operands. Ricardo Neri (17): x86/mpx: Do not use SIB index if index points to R/ESP x86/mpx: Do not use R/EBP as base in the SIB byte with Mod = 0 x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel x86/insn-eval: Add utility functions to get register offsets x86/

[PATCH v4 07/17] x86/insn-eval: Add utility function to get segment descriptor base address

tra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.co

[PATCH v4 02/17] x86/mpx: Do not use R/EBP as base in the SIB byte with Mod = 0

m> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/mm/mpx.c | 30 +++--- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c index 6a034bc..f660ddf 100644 --- a

[PATCH v4 01/17] x86/mpx: Do not use SIB index if index points to R/ESP

com> Cc: Adam Buchbinder <adam.buchbin...@gmail.com> Cc: Colin Ian King <colin.k...@canonical.com> Cc: Lorenzo Stoakes <lstoa...@gmail.com> Cc: Qiaowei Ren <qiaowei@intel.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-

Re: [PATCH 0/4] x86: enable User-Mode Instruction Prevention

On Tue, 2016-11-08 at 17:52 +0100, Thomas Gleixner wrote: > On Tue, 8 Nov 2016, Andy Lutomirski wrote: > > On Tue, Nov 8, 2016 at 5:16 AM, Peter Zijlstra <pet...@infradead.org> wrote: > > > On Mon, Nov 07, 2016 at 10:12:09PM -0800, Ricardo Neri wrote: > > >>

Re: [PATCH 2/4] x86: Prepare vm86 tasks to handle User-Mode Instruction Prevention

On Tue, 2016-11-08 at 18:00 +0100, Peter Zijlstra wrote: > > > + } > > > +#endif > > > + > > > > NAK. If this code is going to exist, it needs to be deeply buried > in > > some unlikely if statement that already exists. There's no good > > reason to penalize all context switches to

Re: [PATCH 0/4] x86: enable User-Mode Instruction Prevention

On Tue, 2016-11-08 at 07:34 -0800, Andy Lutomirski wrote: > > Would it not be better to emulate these instructions for them? What > way > > we can verify they're not malicious. > > Forget malice -- if they are really needed for some silly vm86-using > program, let's trap them and emulate them so

Re: [PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions

On Tue, 2016-11-08 at 07:32 -0800, Andy Lutomirski wrote: > > diff --git a/arch/x86/include/asm/disabled-features.h > b/arch/x86/include/asm/disabled-features.h > > index 85599ad..4707445 100644 > > --- a/arch/x86/include/asm/disabled-features.h > > +++ b/arch/x86/include/asm/disabled-features.h >

Re: [PATCH 0/4] x86: enable User-Mode Instruction Prevention

On Wed, 2016-11-09 at 03:05 -0800, Andy Lutomirski wrote: > On Tue, Nov 8, 2016 at 8:31 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > On Tue, 2016-11-08 at 07:34 -0800, Andy Lutomirski wrote: > >> > Would it not be better to emulate the

Re: [PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions

On Wed, 2016-11-09 at 03:02 -0800, Andy Lutomirski wrote: > On Tue, Nov 8, 2016 at 8:25 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > On Tue, 2016-11-08 at 07:32 -0800, Andy Lutomirski wrote: > >> > diff --git a/arch/x86/include/asm/disab

[PATCH 2/4] x86: Prepare vm86 tasks to handle User-Mode Instruction Prevention

@redhat.com> Cc: Paul Gortmaker <paul.gortma...@windriver.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: Shuah Khan <sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Signed-off-by: Ricardo Neri <ricard

[PATCH 4/4] selftests/x86: Add tests for User-Mode Instruction Prevention

gt; Cc: Paul Gortmaker <paul.gortma...@windriver.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: Shuah Khan <sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Signed-off-by: Ricardo Neri <ricardo.neri-calde.

[PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions

i Slaby <jsl...@suse.cz> Cc: Jonathan Corbet <cor...@lwn.net> Cc: Michael S. Tsirkin <m...@redhat.com> Cc: Paul Gortmaker <paul.gortma...@windriver.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: Shuah Khan <sh.

[PATCH 3/4] x86: Enable User-Mode Instruction Prevention

chael S. Tsirkin <m...@redhat.com> Cc: Paul Gortmaker <paul.gortma...@windriver.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: Shuah Khan <sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Signed-off-by: Ricardo

[PATCH 0/4] x86: enable User-Mode Instruction Prevention

@infradead.org> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: Vlastimil Babka <vba...@suse.cz> Cc: Shuah Khan <sh...@kernel.org> [1]. http://www.dosemu.org/ [2]. https://wiki.winehq.org/Main_Page Ricardo Neri (4): x86/cpufeature: Add User-Mode Instruction Prevention definiti

Re: [PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions

On Thu, 2016-11-10 at 09:58 +0100, Borislav Petkov wrote: > On Wed, Nov 09, 2016 at 07:24:43PM -0800, Ricardo Neri wrote: > > I intended this feature to be configurable at build time in case someone > > wants to build a kernel without it; similar to other features s

Re: [PATCH 0/4] x86: enable User-Mode Instruction Prevention

On Thu, 2016-11-10 at 11:52 +0300, Stas Sergeev wrote: > Hi! > > I don't know the context of that discussion, so I'll only > comment on the dosemu part. I'm sorry! I will cc you and the linux-msdos list in my v2. > > 10.11.2016 09:46, Ricardo Neri пишет: > > I took a c

Re: [PATCH] x86: add UMIP support

Hi Jan, On Thu, 2016-11-17 at 07:52 +0100, Ingo Molnar wrote: > * Jan Beulich wrote: > > > This is a small aid to security, hiding in particular the kernel address > > information otherwise available through SGDT/SIDT. > > > > Signed-off-by: Jan Beulich >

Re: [PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions

On Fri, 2016-11-11 at 11:22 +0100, Borislav Petkov wrote: > On Thu, Nov 10, 2016 at 08:08:07PM -0800, Ricardo Neri wrote: > > UMIP is enabled by setting a bit in CR4. If that bit is not supposed > > to be set, that could cause a #GP fault. > > Yeah, you do check CPUID first,

Re: [PATCH 0/4] x86: enable User-Mode Instruction Prevention

On Fri, 2016-11-11 at 23:51 +0300, Stas Sergeev wrote: > 11.11.2016 07:14, Ricardo Neri пишет: > >> 10.11.2016 09:46, Ricardo Neri пишет: > >>> I took a closer look at the dosemu code. It appears that it does not > >>> purposely utilize SGDT to obtai

Re: [v2 2/7] x86/mpx: Fail when implicit zero-displacement is used along with R/EBP

On Tue, 2017-01-03 at 08:41 -0800, Dave Hansen wrote: > On 12/27/2016 02:33 PM, Ricardo Neri wrote: > >>> diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c > >>> index 6a75a75..71681d0 100644 > >>> --- a/arch/x86/mm/mpx.c > >>> +++ b/arch

Re: [v2 3/7] x86/mpx, x86/insn: Relocate insn util functions to a new insn-utils

On Tue, 2017-01-03 at 08:44 -0800, Dave Hansen wrote: > On 12/23/2016 05:37 PM, Ricardo Neri wrote: > > Other kernel submodules can benefit from using the utility functions > > defined in mpx.c to obtain the addresses and values of operands contained > > in the gene

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

On Fri, 2016-12-30 at 18:07 -0800, Andy Lutomirski wrote: > On Thu, Dec 29, 2016 at 9:23 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: > >> > >> >

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: > On Tue, Dec 27, 2016 at 4:39 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > >> On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Ne

[v2 0/7] x86: enable User-Mode Instruction Prevention

detect the absence of SIGSEGV signals when running in virtual-8086 mode. * Reused code from MPX to decode instructions operands. For this purpose code was put in a common location. * Fixed two bugs in MPX code that decodes operands. Ricardo Neri (7): x86/mpx: Do not use SIB index if index poi

[v2 4/7] x86/cpufeature: Add User-Mode Instruction Prevention definitions

.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.

[v2 5/7] x86: Add emulation code for UMIP instructions

z...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/include/a

[v2 7/7] x86: Enable User-Mode Instruction Prevention

Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/Kconfig | 10 ++ arch/x86/kernel/cpu/common.c | 16 +++-

[v2 2/7] x86/mpx: Fail when implicit zero-displacement is used along with R/EBP

Cc: Qiaowei Ren <qiaowei@intel.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/mm/mpx.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.

[v2 6/7] x86/traps: Fixup general protection faults caused by UMIP

;tony.l...@intel.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-c

[v2 1/7] x86/mpx: Do not use SIB index if index points to R/ESP

stoa...@gmail.com> Cc: Qiaowei Ren <qiaowei@intel.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/mm/mpx.c | 12 +++- 1 file changed, 11 insertions(+), 1 del

[v2 3/7] x86/mpx, x86/insn: Relocate insn util functions to a new insn-utils

rnel.org> Cc: Adrian Hunter <adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V.

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

On Mon, 2016-12-26 at 00:49 +0900, Masami Hiramatsu wrote: > On Fri, 23 Dec 2016 17:37:43 -0800 > Ricardo Neri <ricardo.neri-calde...@linux.intel.com> wrote: > > > +static int __identify_insn(struct insn *insn) > > +{ > > + /* by getting modrm we also get the

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > The feature User-Mode Instruction Prevention present in recent Intel > > processor prevents a group of instruct

Re: [v2 2/7] x86/mpx: Fail when implicit zero-displacement is used along with R/EBP

On Fri, 2016-12-23 at 17:58 -0800, Andy Lutomirski wrote: > On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software > > Developer's Manual volume 2A states tha

Re: [v2 6/7] x86/traps: Fixup general protection faults caused by UMIP

On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > If the User-Mode Instruction Prevention CPU feature is available and > > enabled, a general protect

Re: [v2 3/7] x86/mpx, x86/insn: Relocate insn util functions to a new insn-utils

On Sun, 2016-12-25 at 15:17 +0900, Masami Hiramatsu wrote: > Hi Ricado, > > On Fri, 23 Dec 2016 17:37:41 -0800 > Ricardo Neri <ricardo.neri-calde...@linux.intel.com> wrote: > > > Other kernel submodules can benefit from using the utility functions > > defined

Re: [v2 1/7] x86/mpx: Do not use SIB index if index points to R/ESP

On Fri, 2016-12-23 at 17:57 -0800, Andy Lutomirski wrote: > On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > <ricardo.neri-calde...@linux.intel.com> wrote: > > Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software > > Developer's Manual volume 2A states tha

Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention

On Wed, 2017-03-29 at 23:55 +0300, Stas Sergeev wrote: > 29.03.2017 07:38, Ricardo Neri пишет: > >> Probably you could also remove > >> the sldt and str emulation for protected mode, because, > >> as I understand from this thread, wine does not > >> need th

Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention

On Tue, 2017-03-28 at 12:38 +0300, Stas Sergeev wrote: > 28.03.2017 02:46, Ricardo Neri пишет: > > On Tue, 2017-03-14 at 00:25 +0300, Stas Sergeev wrote: > >> 11.03.2017 02:59, Ricardo Neri пишет: > >>> On Fri, 2017-03-10 at 14:33 +0300, Stas Sergeev wrote: >

Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention

On Tue, 2017-03-14 at 00:25 +0300, Stas Sergeev wrote: > 11.03.2017 02:59, Ricardo Neri пишет: > > On Fri, 2017-03-10 at 14:33 +0300, Stas Sergeev wrote: > > > >> Why would you need one? > >> Or do you really want to allow these instructions > >&g

Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention

On Fri, 2017-03-31 at 16:11 +0200, Alexandre Julliard wrote: > Ricardo Neri <ricardo.neri-calde...@linux.intel.com> writes: > > > On Thu, 2017-03-30 at 13:10 +0300, Stas Sergeev wrote: > >> 30.03.2017 08:14, Ricardo Neri пишет: > >> >>>> But at leas

Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention

On Sat, 2017-04-01 at 16:08 +0300, Stas Sergeev wrote: > 30.03.2017 08:14, Ricardo Neri пишет: > >>>>>> You know the wine's > >>>>>> requirements now - they are very small. And > >>>>>> dosemu doesn't need anything at all bu

Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention

On Thu, 2017-03-30 at 13:10 +0300, Stas Sergeev wrote: > 30.03.2017 08:14, Ricardo Neri пишет: > >>>> But at least dosemu implements it, so probably it is needed. > >>> Right. > >>> > >>>> Of course if it is used by one of 100 DOS prog

[v5 15/20] x86/cpufeature: Add User-Mode Instruction Prevention definitions

.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@kernel.org Cc: linux-ms...@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.

[v5 14/20] x86/insn-eval: Add wrapper function for 16-bit and 32-bit address encodings

gle.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/lib/insn-eval.c | 45 - 1 file changed, 40 insertions(+), 5 deletions(-) diff

[v5 13/20] x86/insn-eval: Add support to resolve 16-bit addressing encodings

Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/lib/insn-ev

[v5 11/20] insn/eval: Incorporate segment base in address computation

..@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/lib/insn-eval.c | 10 --

[v5 16/20] x86: Add emulation code for UMIP instructions

t;sh...@kernel.org> Cc: Vlastimil Babka <vba...@suse.cz> Cc: Tony Luck <tony.l...@intel.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Liang Z. Li <liang.z...@intel.com> Cc: Alexandre Julliard <julli...@winehq.org> Cc: Stas Sergeev <s...@list.ru> Cc: x...@ke

[v5 12/20] x86/insn: Support both signed 32-bit and 64-bit effective addresses

er <adrian.hun...@intel.com> Cc: Kees Cook <keesc...@chromium.org> Cc: Thomas Garnier <thgar...@google.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan.

[v5 00/20] x86: Enable User-Mode Instruction Prevention

ks and BR, Ricardo Ricardo Neri (20): x86/mpx: Use signed variables to compute effective addresses x86/mpx: Do not use SIB index if index points to R/ESP x86/mpx: Do not use R/EBP as base in the SIB byte with Mod = 0 x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel x86/

[v5 08/20] x86/insn-eval: Add utility function to get segment descriptor base address

..@infradead.org> Cc: Borislav Petkov <b...@suse.de> Cc: Dmitry Vyukov <dvyu...@google.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/include/asm/insn-eval.h | 2 ++ arch/

[v5 01/20] x86/mpx: Use signed variables to compute effective addresses

lt;adanhawth...@gmail.com> Cc: Joe Perches <j...@perches.com> Cc: Ravi V. Shankar <ravi.v.shan...@intel.com> Cc: x...@kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- arch/x86/mm/mpx.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-)

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