Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

know the previous packet is exception handling packet so need to generate sample for exception flow. Fixes: e573e978fb12 ("perf cs-etm: Inject capabilitity for CoreSight traces") Cc: Mike Leach <mike.le...@arm.com> Cc: Robert Walker <robert.wal...@arm.com> Cc: Mathieu Poirier <

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

Hi Leo, On 22/05/18 10:52, Leo Yan wrote: On Tue, May 22, 2018 at 04:39:20PM +0800, Leo Yan wrote: [...] Rather than the patch I posted in my previous email, I think below new patch is more reasonable for me. In the below change, 'etmq->prev_packet' is only used to store the previous

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

Hi Leo, On 23/05/18 14:22, Leo Yan wrote: Hi Rob, On Wed, May 23, 2018 at 12:21:18PM +0100, Robert Walker wrote: Hi Leo, On 22/05/18 10:52, Leo Yan wrote: On Tue, May 22, 2018 at 04:39:20PM +0800, Leo Yan wrote: [...] Rather than the patch I posted in my previous email, I think below new

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

inject to generate instruction samples for AutoFDO, so I am happy with that. Regards Rob Reviewed-by: Robert Walker <robert.wal...@arm.com> On 22/05/18 09:39, Leo Yan wrote: Hi Rob, On Mon, May 21, 2018 at 12:27:42PM +0100, Robert Walker wrote: Hi Leo, On 21/05/18 09:52, Leo Yan

Re: [PATCH v2 21/27] coresight: Convert driver messages to dev_dbg

On 02/05/18 04:55, Kim Phillips wrote: On Tue, 1 May 2018 10:10:51 +0100 Suzuki K Poulose wrote: Convert component enable/disable messages from dev_info to dev_dbg. This is required to prevent LOCKDEP splats when operating in perf mode where we could be called with

[PATCH v2 1/3] perf tools: inject capabilitity for CoreSight traces

inally-by: Sebastian Pop <s@samsung.com> Signed-off-by: Robert Walker <robert.wal...@arm.com> Acked-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 65 +++- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 +

[PATCH v2 2/3] perf inject: Emit instruction records on ETM trace discontinuity

is added, which is emitted by the low level decoder when a TRACE ON occurs. The higher level decoder flushes the branch stack when this packet is emitted. Signed-off-by: Robert Walker <robert.wal...@arm.com> Acked-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/util/cs-et

[PATCH v2 0/3] Perf inject for ETM trace

into separate patch * Added null pointer check * Moved some changes from patch 2 to patch 1 Regards Rob Walker Robert Walker (3): perf tools: inject capabilitity for CoreSight traces perf inject: Emit instruction records on ETM trace discontinuity coresight: Update documentation for perf usage

[PATCH v2 3/3] coresight: Update documentation for perf usage

Add notes on using perf to collect and analyze CoreSight trace Signed-off-by: Robert Walker <robert.wal...@arm.com> --- Documentation/trace/coresight.txt | 51 +++ 1 file changed, 51 insertions(+) diff --git a/Documentation/trace/coresight.

[PATCH 0/2] Perf inject for ETM trace

Hi, These patches add support for using perf inject to generate branch events, instruction events and branch stacks from CoreSight ETM traces. They apply to linus's tree with the memory cleanup fix from https://lkml.org/lkml/2018/1/25/432 Regards Rob Walker Robert Walker (2): perf tools

[PATCH 0/2] Perf inject for ETM trace

Hi, These patches add support for using perf inject to generate branch events, instruction events and branch stacks from CoreSight ETM traces. They apply to linus's tree with the memory cleanup fix from https://lkml.org/lkml/2018/1/25/432 Regards Rob Walker Robert Walker (2): perf tools

[PATCH 2/2] perf inject: Emit instruction records on ETM trace discontinuity

is added, which is emitted by the low level decoder when a TRACE ON occurs. The higher level decoder flushes the branch stack when this packet is emitted. Signed-off-by: Robert Walker <robert.wal...@arm.com> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 +++ tools/perf/util/cs-etm-d

[PATCH 1/2] perf tools: inject capabilitity for CoreSight traces

inally-by: Sebastian Pop <s@samsung.com> Signed-off-by: Robert Walker <robert.wal...@arm.com> --- Documentation/trace/coresight.txt | 51 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 65 +++- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/

RE: [PATCH 2/2] perf inject: Emit instruction records on ETM trace discontinuity

> -Original Message- > From: Arnaldo Carvalho de Melo [mailto:a...@kernel.org] > Sent: 15 February 2018 14:57 > To: Mathieu Poirier <mathieu.poir...@linaro.org> > Cc: Robert Walker <robert.wal...@arm.com>; linux- > ker...@vger.kernel.org; linux-arm-ker...

[PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.9.1 of OpenCSD. A check for the new struct member has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- v2: Minor fixes following review comments from Mathieu Rebased on v4.19-rc1 tools/build/feature/test-libopencsd.c | 7 +++ tools/perf

[PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.9.1 of OpenCSD. A check for the new struct member has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- tools/build/feature/test-libopencsd.c | 7 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 27 ++ tools/perf/util/cs-etm-decoder

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

Hi Kim, On 29/08/18 14:49, Kim Phillips wrote: On Wed, 29 Aug 2018 10:44:23 +0100 Robert Walker wrote: This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2 or 4 byte instruction size, so

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

0100 Robert Walker wrote: Hi Kim, Hi Robert, On 29/08/18 14:49, Kim Phillips wrote: On Wed, 29 Aug 2018 10:44:23 +0100 Robert Walker wrote: This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2

Re: [PATCH v3 07/10] pert tools: Add queue management functionality

On 01/17/2018 05:52 PM, Mathieu Poirier wrote: Add functionatlity to setup trace queues so that traces associated with CoreSight auxtrace events found in the perf.data file can be classified properly. The decoder and memory callback associated with each queue are then used to decode the

[PATCH v4] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- tools/build/feature/test-libopencsd.c | 8 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++ tools/perf/util/cs-etm

[PATCH v5] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- Changes since v4: Formatting of comment block tools/build/feature/test-libopencsd.c | 8 +++ tools/perf/util/cs-etm-decoder/cs-etm

[PATCH v5 RESEND] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- Hi Arnaldo, Please add this patch to the queue for 4.21 (originally sent as https://lkml.org/lkml/2018/11/9/965) Mathieu has reviewed it: https

[PATCH v2 2/3] perf inject: Emit instruction records on ETM trace discontinuity

is added, which is emitted by the low level decoder when a TRACE ON occurs. The higher level decoder flushes the branch stack when this packet is emitted. Signed-off-by: Robert Walker Acked-by: Mathieu Poirier --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 +++ tools/perf/util/cs-etm

[PATCH v2 0/3] Perf inject for ETM trace

into separate patch * Added null pointer check * Moved some changes from patch 2 to patch 1 Regards Rob Walker Robert Walker (3): perf tools: inject capabilitity for CoreSight traces perf inject: Emit instruction records on ETM trace discontinuity coresight: Update documentation for perf usage

[PATCH v2 1/3] perf tools: inject capabilitity for CoreSight traces

-by: Robert Walker Acked-by: Mathieu Poirier --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 65 +++- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c| 434 +--- 3 files changed, 436 insertions(+), 64 deletions

[PATCH v2 3/3] coresight: Update documentation for perf usage

Add notes on using perf to collect and analyze CoreSight trace Signed-off-by: Robert Walker --- Documentation/trace/coresight.txt | 51 +++ 1 file changed, 51 insertions(+) diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight.txt

RE: [PATCH 2/2] perf inject: Emit instruction records on ETM trace discontinuity

> -Original Message- > From: Arnaldo Carvalho de Melo [mailto:a...@kernel.org] > Sent: 15 February 2018 14:57 > To: Mathieu Poirier > Cc: Robert Walker ; linux- > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > coresi...@lists.linaro.org > Subje

Re: [PATCH v2 21/27] coresight: Convert driver messages to dev_dbg

On 02/05/18 04:55, Kim Phillips wrote: On Tue, 1 May 2018 10:10:51 +0100 Suzuki K Poulose wrote: Convert component enable/disable messages from dev_info to dev_dbg. This is required to prevent LOCKDEP splats when operating in perf mode where we could be called with locks held to enable a

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

know the previous packet is exception handling packet so need to generate sample for exception flow. Fixes: e573e978fb12 ("perf cs-etm: Inject capabilitity for CoreSight traces") Cc: Mike Leach Cc: Robert Walker Cc: Mathieu Poirier Signed-off-by: Leo Yan

[PATCH 0/2] Perf inject for ETM trace

Hi, These patches add support for using perf inject to generate branch events, instruction events and branch stacks from CoreSight ETM traces. They apply to linus's tree with the memory cleanup fix from https://lkml.org/lkml/2018/1/25/432 Regards Rob Walker Robert Walker (2): perf tools

[PATCH 0/2] Perf inject for ETM trace

Hi, These patches add support for using perf inject to generate branch events, instruction events and branch stacks from CoreSight ETM traces. They apply to linus's tree with the memory cleanup fix from https://lkml.org/lkml/2018/1/25/432 Regards Rob Walker Robert Walker (2): perf tools

[PATCH 2/2] perf inject: Emit instruction records on ETM trace discontinuity

is added, which is emitted by the low level decoder when a TRACE ON occurs. The higher level decoder flushes the branch stack when this packet is emitted. Signed-off-by: Robert Walker --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1

[PATCH 1/2] perf tools: inject capabilitity for CoreSight traces

-by: Robert Walker --- Documentation/trace/coresight.txt | 51 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 65 +++- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c| 433 +--- 4 files changed, 486

Re: [PATCH v3 07/10] pert tools: Add queue management functionality

On 01/17/2018 05:52 PM, Mathieu Poirier wrote: Add functionatlity to setup trace queues so that traces associated with CoreSight auxtrace events found in the perf.data file can be classified properly. The decoder and memory callback associated with each queue are then used to decode the

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

Hi Leo, On 22/05/18 10:52, Leo Yan wrote: On Tue, May 22, 2018 at 04:39:20PM +0800, Leo Yan wrote: [...] Rather than the patch I posted in my previous email, I think below new patch is more reasonable for me. In the below change, 'etmq->prev_packet' is only used to store the previous

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

Hi Leo, On 23/05/18 14:22, Leo Yan wrote: Hi Rob, On Wed, May 23, 2018 at 12:21:18PM +0100, Robert Walker wrote: Hi Leo, On 22/05/18 10:52, Leo Yan wrote: On Tue, May 22, 2018 at 04:39:20PM +0800, Leo Yan wrote: [...] Rather than the patch I posted in my previous email, I think below new

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

inject to generate instruction samples for AutoFDO, so I am happy with that. Regards Rob Reviewed-by: Robert Walker On 22/05/18 09:39, Leo Yan wrote: Hi Rob, On Mon, May 21, 2018 at 12:27:42PM +0100, Robert Walker wrote: Hi Leo, On 21/05/18 09:52, Leo Yan wrote: Commit e573e978fb12

[PATCH] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.9.1 of OpenCSD. A check for the new struct member has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- tools/build/feature/test-libopencsd.c | 7 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 27 ++ tools/perf/util/cs-etm-decoder

[PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.9.1 of OpenCSD. A check for the new struct member has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- v2: Minor fixes following review comments from Mathieu Rebased on v4.19-rc1 tools/build/feature/test-libopencsd.c | 7 +++ tools/perf

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

Hi Kim, On 29/08/18 14:49, Kim Phillips wrote: On Wed, 29 Aug 2018 10:44:23 +0100 Robert Walker wrote: This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2 or 4 byte instruction size, so

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

0100 Robert Walker wrote: Hi Kim, Hi Robert, On 29/08/18 14:49, Kim Phillips wrote: On Wed, 29 Aug 2018 10:44:23 +0100 Robert Walker wrote: This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets. T32 has variable 2

Re: [PATCH v1 1/2] perf cs-etm: Always allocate memory for cs_etm_queue::prev_packet

Hi, On 28/04/2019 09:32, Leo Yan wrote: Robert Walker reported a segmentation fault is observed when process CoreSight trace data; this issue can be easily reproduced by the command 'perf report --itrace=i1000i' for decoding tracing data. If neither the 'b' flag (synthesize branches events

Re: [PATCH v1 2/2] perf cs-etm: Don't check cs_etm_queue::prev_packet validity

(+), 5 deletions(-) Tested-by: Robert Walker Regards Rob diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 054b480aab04..de488b43f440 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -979,7 +979,6 @@ static int cs_etm__sample(struct cs_etm_queue *etmq

[PATCH v5 RESEND] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- Hi Arnaldo, Please add this patch to the queue for 4.21 (originally sent as https://lkml.org/lkml/2018/11/9/965) Mathieu has reviewed it: https

[PATCH v5] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- Changes since v4: Formatting of comment block tools/build/feature/test-libopencsd.c | 8 +++ tools/perf/util/cs-etm-decoder/cs-etm

[PATCH v4] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

version 0.10.0 of OpenCSD. A check for the OpenCSD library version has been added to the feature check for OpenCSD. Signed-off-by: Robert Walker --- tools/build/feature/test-libopencsd.c | 8 +++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++ tools/perf/util/cs-etm

[tip:perf/core] perf cs-etm: Inject capabilitity for CoreSight traces

Commit-ID: e573e978fb12e16094c0b39fad3dc4e6b4803c2c Gitweb: https://git.kernel.org/tip/e573e978fb12e16094c0b39fad3dc4e6b4803c2c Author: Robert Walker <robert.wal...@arm.com> AuthorDate: Wed, 14 Feb 2018 11:24:39 + Committer: Arnaldo Carvalho de Melo <a...@redhat.com> Com

[tip:perf/core] perf inject: Emit instruction records on ETM trace discontinuity

Commit-ID: 256e751cac78739a4de2232450d3681b68b5845e Gitweb: https://git.kernel.org/tip/256e751cac78739a4de2232450d3681b68b5845e Author: Robert Walker <robert.wal...@arm.com> AuthorDate: Wed, 14 Feb 2018 11:24:40 + Committer: Arnaldo Carvalho de Melo <a...@redhat.com> Com

[tip:perf/core] coresight: Update documentation for perf usage

Commit-ID: 6673016f874adee171690f95540ead5efddb5351 Gitweb: https://git.kernel.org/tip/6673016f874adee171690f95540ead5efddb5351 Author: Robert Walker <robert.wal...@arm.com> AuthorDate: Wed, 14 Feb 2018 11:24:41 + Committer: Arnaldo Carvalho de Melo <a...@redhat.com> Com

[tip:perf/core] perf cs-etm: Inject capabilitity for CoreSight traces

Commit-ID: e573e978fb12e16094c0b39fad3dc4e6b4803c2c Gitweb: https://git.kernel.org/tip/e573e978fb12e16094c0b39fad3dc4e6b4803c2c Author: Robert Walker AuthorDate: Wed, 14 Feb 2018 11:24:39 + Committer: Arnaldo Carvalho de Melo CommitDate: Fri, 16 Feb 2018 14:55:44 -0300 perf cs-etm

[tip:perf/core] perf inject: Emit instruction records on ETM trace discontinuity

Commit-ID: 256e751cac78739a4de2232450d3681b68b5845e Gitweb: https://git.kernel.org/tip/256e751cac78739a4de2232450d3681b68b5845e Author: Robert Walker AuthorDate: Wed, 14 Feb 2018 11:24:40 + Committer: Arnaldo Carvalho de Melo CommitDate: Fri, 16 Feb 2018 14:55:45 -0300 perf inject

[tip:perf/core] coresight: Update documentation for perf usage

Commit-ID: 6673016f874adee171690f95540ead5efddb5351 Gitweb: https://git.kernel.org/tip/6673016f874adee171690f95540ead5efddb5351 Author: Robert Walker AuthorDate: Wed, 14 Feb 2018 11:24:41 + Committer: Arnaldo Carvalho de Melo CommitDate: Fri, 16 Feb 2018 14:55:46 -0300 coresight

[tip:perf/core] perf cs-etm: Support for ARM A32/T32 instruction sets in CoreSight trace

Commit-ID: c7d74f860abca8027ec77e0801a95a90a5d9bf90 Gitweb: https://git.kernel.org/tip/c7d74f860abca8027ec77e0801a95a90a5d9bf90 Author: Robert Walker AuthorDate: Mon, 3 Dec 2018 12:18:46 + Committer: Arnaldo Carvalho de Melo CommitDate: Mon, 3 Dec 2018 12:02:51 -0300 perf cs-etm

[tip:perf/core] perf cs-etm: Support for ARM A32/T32 instruction sets in CoreSight trace

Commit-ID: a7ee4d625ede4f62146ff3bb2aeee074e4cf5fa1 Gitweb: https://git.kernel.org/tip/a7ee4d625ede4f62146ff3bb2aeee074e4cf5fa1 Author: Robert Walker AuthorDate: Mon, 3 Dec 2018 12:18:46 + Committer: Arnaldo Carvalho de Melo CommitDate: Mon, 17 Dec 2018 14:56:18 -0300 perf cs-etm