be explicitly ordered by sfence or mfence.
The inline assembly for clflushopt was implemented using %P so that the
generated addresses will always be absolute instead of sometimes being RIP
relative. This is necessary for the alternatives code to behave correctly.
Ross Zwisler (4):
x86: Add support
Add support for the new clflushopt instruction. This instruction was
announced in the document Intel Architecture Instruction Set Extensions
Programming Reference with Ref # 319433-018.
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Signed-off-by: Ross
If clflushopt is available on the system, use it instead of clflush in
drm_clflush_virt_range.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
---
drivers/gpu/drm
If clflushopt is available on the system, use it instead of clflush in
clflush_cache_range.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
---
arch/x86/mm/pageattr.c |8
If clflushopt is available on the system, use it instead of clflush in
drm_clflush_page.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
---
drivers/gpu/drm/drm_cache.c
On Mon, 3 Mar 2014, Dave Chinner wrote:
On Fri, Feb 28, 2014 at 03:20:31PM -0500, Matthew Wilcox wrote:
On Fri, Feb 28, 2014 at 10:49:31AM -0700, Toshi Kani wrote:
The original code,
xip_file_fault(), jumps to found: and calls vm_insert_mixed() when
get_xip_mem(,,0,,) succeeded. If
On Wed, 15 Jan 2014, Matthew Wilcox wrote:
From: Ross Zwisler ross.zwis...@linux.intel.com
This is a port of the XIP functionality found in the current version of
ext2.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Reviewed-by: Andreas Dilger andreas.dil...@intel.com
[heavily
On Wed, 15 Jan 2014, Matthew Wilcox wrote:
Instead of separate read and write methods, use the generic AIO
infrastructure. In addition to giving us support for AIO, this adds
the locking between read() and truncate() that was missing.
Signed-off-by: Matthew Wilcox matthew.r.wil...@intel.com
On Tue, 11 Feb 2014, Ross Zwisler wrote:
On Wed, 15 Jan 2014, Matthew Wilcox wrote:
From: Ross Zwisler ross.zwis...@linux.intel.com
This is a port of the XIP functionality found in the current version of
ext2.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Reviewed
On Tue, 25 Feb 2014, Matthew Wilcox wrote:
From: Ross Zwisler ross.zwis...@linux.intel.com
This is a port of the DAX functionality found in the current version of
ext2.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Reviewed-by: Andreas Dilger andreas.dil...@intel.com
[heavily
arch/x86/include/asm
The comment explaining their interaction was retained and is now present
in arch/x86/include/uapi/asm/e820.h. This comment is no longer correct,
so delete it.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi
clflush call to clflushopt.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Reported-by: Matthew Wilcox matthew.r.wil...@intel.com
Cc: David Airlie airl...@linux.ie
Cc: dri-de...@lists.freedesktop.org
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas
-= first;
This is needed so that we don't overrun the XIP buffer we are given in the
event that our user buffer = our XIP buffer and the start of our I/O isn't
block aligned.
You can add my
Reviewed-by: Ross Zwisler ross.zwis...@linux.intel.com
Thanks,
- Ross
--
To unsubscribe from this list
On Thu, 23 Jan 2014, Matthew Wilcox wrote:
On Wed, Jan 22, 2014 at 03:51:56PM -0700, Ross Zwisler wrote:
+ if (hole) {
addr = NULL;
- hole = true;
size = bh-b_size;
+ } else
On Wed, 15 Jan 2014, Matthew Wilcox wrote:
+#ifdef CONFIG_FS_XIP
+const struct file_operations ext4_xip_file_operations = {
+ .llseek = ext4_llseek,
+ .read = do_sync_read,
+ .write = do_sync_write,
I think we may always need to define
On Thu, 23 Jan 2014, Matthew Wilcox wrote:
On Wed, Jan 22, 2014 at 03:51:56PM -0700, Ross Zwisler wrote:
+ if (hole) {
addr = NULL;
- hole = true;
size = bh-b_size;
+ } else
On Fri, 31 Jan 2014, Dave Chinner wrote:
The read/write path is broken, Willy. We can't map arbitrary byte
ranges to the DIO subsystem. I'm now certain that the data
corruptions I'm seeing are in sub-sector regions from unaligned IOs
from userspace. We still need to use the buffered IO path
On Wed, 2014-07-30 at 17:15 +0300, Boaz Harrosh wrote:
With current code after a call to:
bdev = blkdev_get_by_path(dev_name, mode, fs_type);
size = i_size_read(bdev-bd_inode);
part_size = bdev-bd_part-nr_sects 9;
I get the following bad results:
dev_name == /dev/ram0
CONFIG_FS_XIP to CONFIG_FS_DAX
ext2: Remove ext2_aops_xip
Get rid of most mentions of XIP in ext2
xip: Add xip_zero_page_range
brd: Rename XIP to DAX
Ross Zwisler (1):
ext4: Add DAX functionality
Documentation/filesystems/Locking | 3 -
Documentation/filesystems/dax.txt | 91
On Mon, 2014-05-19 at 11:50 -0600, Ross Zwisler wrote:
A comment introduced by this commit:
028b785888c5 x86 boot: extend some internal memory map arrays to handle
larger EFI input
had to do with some nested preprocessor directives. The directives were
split into separate files
On Wed, 2014-07-23 at 15:50 -0400, Matthew Wilcox wrote:
On Wed, Jul 23, 2014 at 06:58:38PM +0300, Boaz Harrosh wrote:
Have you please pushed this tree to git hub. It used to be on the prd
tree, if you could just add another branch there, it would be cool.
(https://github.com/01org/prd)
On Wed, 6 Aug 2014, Boaz Harrosh wrote:
From: Ross Zwisler ross.zwis...@linux.intel.com
Some programs require HDIO_GETGEO work, which requires we implement
getgeo. Based off of the work done to the NVMe driver in this commit:
4cc09e2dc4cb NVMe: Add getgeo to block ops
[Boaz] Converted
On Wed, 2014-08-06 at 14:35 +0300, Boaz Harrosh wrote:
Because of the direct_access() API which returns a PFN. partitions
better start on 4K boundary, else offset ZERO of a partition will
not be aligned and blk_direct_access() will fail the call.
By setting
On Wed, 2014-08-06 at 14:33 +0300, Boaz Harrosh wrote:
This patch fixes up brd's partitions scheme, now enjoying all worlds.
The MAIN fix here is that currently if one fdisks some partitions,
a BAD bug will make all partitions point to the same start-end sector
ie: 0 - brd_size And an mkfs
On Thu, 2014-08-07 at 12:11 +0300, Boaz Harrosh wrote:
On 08/07/2014 02:06 AM, Ross Zwisler wrote:
Also, it looks like you can still create a new device with this patch, but
you
can't create partitions on that device. Not sure if this is just what you
get
when you dynamically create
applies with minors as with the pre-created ones.
TODO: dynamic grow of device size, maybe through sysfs. So each
device can have it's own size.
Signed-off-by: Boaz Harrosh b...@plexistor.com
Tested-by: Ross Zwisler ross.zwis...@linux.intel.com
--
To unsubscribe from this list
/27/31
Specifically, my implementation of pmem_direct_access() in patch 4/4 uses API
enhancements introduced in Matthew's DAX patch v10 02/21:
https://lkml.org/lkml/2014/8/27/48
Ross Zwisler (4):
pmem: Initial version of persistent memory driver
pmem: Add support for getgeo()
pmem: Add
PMEM is a new driver that presents a reserved range of memory as a
block device. This is useful for developing with NV-DIMMs, and
can be used with volatile memory as a development platform.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
---
MAINTAINERS| 6 +
drivers
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
---
drivers/block/pmem.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/block/pmem.c b/drivers/block/pmem.c
index 0be3669..d63bc96 100644
--- a/drivers/block/pmem.c
+++ b/drivers/block/pmem.c
@@ -74,6
Some programs require HDIO_GETGEO work, which requires we implement
getgeo. Based off of the work done to the NVMe driver in this commit:
commit 4cc09e2dc4cb (NVMe: Add getgeo to block ops)
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
---
drivers/block/pmem.c | 10 ++
1
Based on commit a72132c31d58 (brd: add support for rw_page())
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
---
drivers/block/pmem.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/block/pmem.c b/drivers/block/pmem.c
index 60bbe0d..0be3669 100644
--- a/drivers
while it is still in the CPU cache, giving us a performance
boost.
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: David Airlie airl...@linux.ie
Cc: dri-de...@lists.freedesktop.org
Cc: x...@kernel.org
Ross Zwisler (6):
x86
If clwb is available on the system, use it in drm_clflush_virt_range.
If clwb is not available, fall back to clflushopt if you can.
If clflushopt is not supported, fall all the way back to clflush.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
.
Based on this, I don't believe I need to account for this extra prefix when
dealing with the assembly language created for clwb. Please correct me if
I'm wrong.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi
If clwb is available on the system, use it in clflush_cache_range.
If clwb is not available, fall back to clflushopt if you can.
If clflushopt is not supported, fall all the way back to clflush.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc
If clwb is available on the system, use it in drm_clflush_page.
If clwb is not available, fall back to clflushopt if you can.
If clflushopt is not supported, fall all the way back to clflush.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc
Add support for the new pcommit instruction. This instruction was
announced in the document Intel Architecture Instruction Set Extensions
Programming Reference with reference number 319433-022.
https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
Signed-off-by: Ross
Add alternative_io_2 in the spirit of alternative_input_2 and
alternative_io. This will allow us to have instructions with an output
parameter that vary based on two CPU features.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar
On Tue, 2014-11-11 at 20:19 +0100, Borislav Petkov wrote:
On Tue, Nov 11, 2014 at 08:12:39PM +0100, Borislav Petkov wrote:
+ .byte 0x66; xsaveopt %P0,
Huh, XSAVEOPT?!? Shouldn't that be CLWB??
Bah, the same opcodes, only 0x66 prefix makes it into CLWB. Could use a
On Tue, 2014-11-11 at 20:12 +0100, Borislav Petkov wrote:
On Tue, Nov 11, 2014 at 11:43:13AM -0700, Ross Zwisler wrote:
Add support for the new clwb instruction. This instruction was
announced in the document Intel Architecture Instruction Set Extensions
Programming Reference
On Tue, 2014-11-11 at 20:46 +0100, Borislav Petkov wrote:
On Tue, Nov 11, 2014 at 12:40:00PM -0700, Ross Zwisler wrote:
Yep, it's weird, I know. :)
But sure, saving opcode space, makes sense to me.
Btw, I'd still be interested about this:
+static inline void clwb(volatile void *__p
On Wed, 2014-11-12 at 15:12 +0100, Borislav Petkov wrote:
On Wed, Nov 12, 2014 at 01:38:45PM +, Anvin, H Peter wrote:
No, it doesn't. x86 requires 3.4+ at a minimum.
The only test I see is:
#if GCC_VERSION 30200
# error Sorry, your compiler is too old - please upgrade it.
#endif
This patch adds 64 bit ULL constants to include/linux/sizes.h. These
sizes range from SZ_4G (4 gibibyte) through SZ_8E (8 exbibyte).
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
---
include/linux/sizes.h | 35 +++
1 file changed, 35 insertions
On Wed, 2014-11-12 at 19:25 -0800, Andy Lutomirski wrote:
On 11/11/2014 10:43 AM, Ross Zwisler wrote:
Add support for the new pcommit instruction. This instruction was
announced in the document Intel Architecture Instruction Set Extensions
Programming Reference with reference number 319433
On Tue, 2014-11-04 at 16:26 +, Elliott, Robert (Server Storage)
wrote:
-Original Message-
From: Boaz Harrosh [mailto:b...@plexistor.com]
Sent: Tuesday, 04 November, 2014 4:38 AM
To: Wilcox, Matthew R; Elliott, Robert (Server Storage); Ross
Zwisler; Jens Axboe; Nick Piggin
this right.
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Borislav Petkov b...@alien8.de
Ross Zwisler (2):
x86: Add support for the pcommit instruction
x86: Add support for the clwb instruction
arch/x86/include/asm
Add support for the new pcommit instruction. This instruction was
announced in the document Intel Architecture Instruction Set Extensions
Programming Reference with reference number 319433-022.
https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
Signed-off-by: Ross
-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Borislav Petkov b...@alien8.de
---
arch/x86/include/asm/cpufeature.h| 1 +
arch/x86/include/asm/special_insns.h | 14
On Fri, 2015-01-23 at 15:03 -0800, H. Peter Anvin wrote:
On 01/23/2015 12:40 PM, Ross Zwisler wrote:
This patch set adds support for two new persistent memory instructions,
pcommit
and clwb. These instructions were announced in the document Intel
Architecture Instruction Set Extensions
On Sat, 2015-01-24 at 12:14 +0100, Borislav Petkov wrote:
On Fri, Jan 23, 2015 at 03:03:41PM -0800, H. Peter Anvin wrote:
For the specific case of CLWB, we can use an m input rather than a
+m output, simply because CLWB (or CLFLUSH* used as a standin for CLWB
doesn't need to be ordered with
On Mon, 2015-01-26 at 22:34 +0100, Borislav Petkov wrote:
On Mon, Jan 26, 2015 at 12:59:29PM -0700, Ross Zwisler wrote:
/*
* sfence to order pcommit
* mfence via mb() also works
*/
wmb();
Doc says PCOMMIT is not ordered
On Tue, 2015-01-27 at 09:53 -0700, Ross Zwisler wrote:
This patch set adds support for two new persistent memory instructions,
pcommit
and clwb. These instructions were announced in the document Intel
Architecture Instruction Set Extensions Programming Reference with reference
number 319433
On Tue, 2015-01-20 at 15:54 -0200, Fabio Estevam wrote:
On Tue, Jan 20, 2015 at 3:39 PM, Paul Moore pmo...@redhat.com wrote:
Thanks for testing this and reporting the problem, especially such a small
bisection. Unfortunately nothing is immediately obvious to me, would you
mind
sharing
.
This patch applies cleanly to v3.19, and fixes the screen flicker issue
on my system. Here is the hardware that I'm using (from lspci):
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Seymour [Radeon HD 6400M/7400M Series]
Signed-off-by: Ross Zwisler ross.zwis
On Sat, 2015-02-14 at 06:25 +, Deucher, Alexander wrote:
-Original Message-
From: Ross Zwisler [mailto:ross.zwis...@linux.intel.com]
Sent: Friday, February 13, 2015 10:55 PM
To: Michel Dänzer
Cc: linux-kernel@vger.kernel.org; dri-de...@lists.freedesktop.org; Deucher
On Mon, 2015-02-16 at 13:24 +0200, Boaz Harrosh wrote:
With old Kernels there was a bug in x86 where any unknown
memory chip type would come up BUSY when calling
request_mem_region_exclusive().
So for pmem to work with old Kernels and real NvDIMM chips
we have a new Kconfig option
On Thu, 2015-02-19 at 02:15 +0100, Ingo Molnar wrote:
* tip-bot for Ross Zwisler tip...@zytor.com wrote:
Commit-ID: a71ef01336f2228dc9d47320492360d6848e591e
Gitweb:
http://git.kernel.org/tip/a71ef01336f2228dc9d47320492360d6848e591e
Author: Ross Zwisler ross.zwis
*/
/*
* sfence to order pcommit
* mfence via mb() also works
*/
wmb();
}
This is still correct, but now you've got two fences separated
by only a nop. With the commit and the fence together in
pcommit_sfence() you avoid the final unneeded fence.
Signed-off-by: Ross Zwisler
On Thu, 2015-02-19 at 18:33 +0100, Borislav Petkov wrote:
On Thu, Feb 19, 2015 at 10:21:53AM -0700, Ross Zwisler wrote:
Interesting, it looks like I need to include asm/nops.h explicitly for
UML. New patch on the way.
You'd need to do an incremental fix ontop, though.
Oh, instead of just
On Wed, 2015-01-28 at 18:21 +0100, Borislav Petkov wrote:
On Wed, Jan 28, 2015 at 05:10:46PM +, Elliott, Robert (Server Storage)
wrote:
Should this patch series also add defines for the virtual
machine control data structure changes?
1. Add the new VM-Execution Controls bit 21 as
on the platform
both the pcommit and the sfence will be nops.
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Borislav Petkov b...@alien8.de
Ross Zwisler (2):
x86: Add support for the pcommit instruction
x86: Add support
*/
/*
* sfence to order pcommit
* mfence via mb() also works
*/
wmb();
}
This is still correct, but now you've got two fences separated by only a
nop. With the commit and the fence together in pcommit_sfence() you
avoid the final unneeded fence.
Signed-off-by: Ross Zwisler
to assemble the clwb instruction itself, the next closest thing is to
have an xsaveopt instruction with a 0x66 prefix. Unfortunately xsaveopt
itself is also relatively new, and isn't included by all the GCC
versions that the kernel needs to support.
Signed-off-by: Ross Zwisler ross.zwis
On Mon, 2015-01-26 at 23:39 +0100, Borislav Petkov wrote:
On Mon, Jan 26, 2015 at 02:50:07PM -0700, Ross Zwisler wrote:
We can use MFENCE, but I don't think we need to. With SFENCE we will
be ordered with respect to stores, and the flushes and pcommit will be
ordered with respect to one
On Mon, 2015-01-12 at 15:10 -0800, Andrew Morton wrote:
On Fri, 24 Oct 2014 17:20:50 -0400 Matthew Wilcox
matthew.r.wil...@intel.com wrote:
Signed-off-by: Matthew Wilcox matthew.r.wil...@intel.com
[ported to 3.13-rc2]
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
I never
On Fri, 2015-02-13 at 11:41 +0900, Michel Dänzer wrote:
On 13.02.2015 05:30, Ross Zwisler wrote:
This patch reverts the changes made in this commit:
deadcb36f49b (drm/radeon: Use two-ended allocation by size, v2)
That patch caused a regression on my system where the bottom
discontinuous memory regions
in the next patch
Signed-off-by: Boaz Harrosh b...@plexistor.com
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: linux-nvd...@lists.01.org
Cc: linux-fsde...@vger.kernel.org
Cc: ax...@kernel.dk
Cc: h...@infradead.org
Cc: r...@redhat.com
---
drivers/block
Harrosh (1):
pmem: Let each device manage private memory region
Ross Zwisler (5):
pmem: Initial version of persistent memory driver
pmem: Add support for getgeo()
pmem: Add support for rw_page()
pmem: Add support for direct_access()
pmem: Clean up includes
MAINTAINERS| 6
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: linux-nvd...@lists.01.org
Cc: linux-fsde...@vger.kernel.org
Cc: ax...@kernel.dk
Cc: h...@infradead.org
Cc: r...@redhat.com
---
drivers/block/pmem.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/block
Some programs require HDIO_GETGEO work, which requires we implement
getgeo. Based off of the work done to the NVMe driver in this commit:
commit 4cc09e2dc4cb (NVMe: Add getgeo to block ops)
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: linux-nvd...@lists.01.org
Cc: linux-fsde
PMEM is a new driver that presents a reserved range of memory as a
block device. This is useful for developing with NV-DIMMs, and
can be used with volatile memory as a development platform.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: linux-nvd...@lists.01.org
Cc: linux-fsde
Based on commit a72132c31d58 (brd: add support for rw_page())
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: linux-nvd...@lists.01.org
Cc: linux-fsde...@vger.kernel.org
Cc: ax...@kernel.dk
Cc: h...@infradead.org
Cc: r...@redhat.com
---
drivers/block/pmem.c | 11 +++
1 file
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: linux-nvd...@lists.01.org
Cc: linux-fsde...@vger.kernel.org
Cc: ax...@kernel.dk
Cc: h...@infradead.org
Cc: r...@redhat.com
---
drivers/block/pmem.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers
On Thu, 2015-03-05 at 13:55 +0200, Boaz Harrosh wrote:
From: Ross Zwisler ross.zwis...@linux.intel.com
PMEM is a new driver That supports any physical contiguous iomem range
as a single block device. The driver has support for as many as needed
iomem ranges each as its own device
-by: Ross Zwisler ross.zwis...@linux.intel.com
Reported-by: Hugh Daschbach hugh.daschb...@enmotus.com
Cc: Roger C. Pao (Enmotus) rcpao.enmo...@gmail.com
Cc: Boaz Harrosh b...@plexistor.com
Cc: linux-nvd...@lists.01.org
Cc: Nick Piggin npig...@kernel.dk
---
drivers/block/brd.c | 1 +
1 file changed, 1
of the base C standards.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Reported-by: H. Peter Anvin h...@zytor.com
Cc: H. Peter Anvin h...@zytor.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: x...@kernel.org
Cc: Dan Williams dan.j.willi...@intel.com
Cc
Add kerneldoc comments for pcommit_sfence() describing the purpose of
the pcommit instruction and demonstrating the usage of that instruction.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t
On Wed, 2015-03-11 at 19:17 +0200, Boaz Harrosh wrote:
On 03/11/2015 07:02 PM, Ross Zwisler wrote:
The functions copy_from_brd() and copy_to_brd() are written with an
assumption that the bio_vec they are given has size = PAGE_SIZE. This
assumption is not enforced in any way
On Thu, 2015-03-05 at 13:58 +0200, Boaz Harrosh wrote:
From: Yigal Korman yi...@plexistor.com
Refactored the arguments of sparse_add_one_section / sparse_remove_one_section
to use node id instead of struct zone * - A memory section has no direct
connection to zones, all that was needed from
On Thu, 2015-03-05 at 12:32 +0200, Boaz Harrosh wrote:
There are already NvDIMMs and other Persistent-memory devices in the market,
and
lots more of them will be coming in near future.
Current stack is coming along very nice, and filesystems support for
leveraging this
technologies has
On Thu, 2015-03-12 at 11:58 +0100, Ingo Molnar wrote:
+/**
+ * pcommit_sfence() - persistent commit and fence
+ *
+ * The pcommit instruction ensures that data that has been flushed from
the
+ * processor's cache hierarchy with clwb, clflushopt or clflush is
accepted to
+
On Thu, 2015-03-12 at 12:09 +0100, Ingo Molnar wrote:
* Ross Zwisler ross.zwis...@linux.intel.com wrote:
The current algorithm used in clflush_cache_range() can cause the last
cache line of the buffer to be flushed twice.
Fix that algorithm so that each cache line will only be flushed
On Wed, 2015-03-25 at 17:04 +0100, Christoph Hellwig wrote:
From: Ross Zwisler ross.zwis...@linux.intel.com
PMEM is a new driver that presents a reserved range of memory as a
block device. This is useful for developing with NV-DIMMs, and
can be used with volatile memory as a development
On Wed, 2015-03-25 at 21:19 +0100, Paul Bolle wrote:
The same license nit I found in the previous two versions of this patch.
On Wed, 2015-03-25 at 17:04 +0100, Christoph Hellwig wrote:
--- /dev/null
+++ b/drivers/block/pmem.c
+ * This program is free software; you can redistribute it
On Wed, 2015-03-25 at 17:04 +0100, Christoph Hellwig wrote:
Various recent bioses support NVDIMMs or ADR using a non-standard
e820 memory type, and Intel supplied reference Linux code using this
type to various vendors.
Wire this e820 table type up to export platform devices for the pmem
their own preferre method to
do it, which I'd like to discuss once we have the basic driver in.
This has been tested both with a real NVDIMM on a system with a type 12
capable bios, as well as with fake persistent memory using the memmap=
option.
For the series:
Tested-by: Ross Zwisler ross.zwis
On Wed, 2015-03-25 at 17:04 +0100, Christoph Hellwig wrote:
Various recent bioses support NVDIMMs or ADR using a non-standard
e820 memory type, and Intel supplied reference Linux code using this
type to various vendors.
Wire this e820 table type up to export platform devices for the pmem
On Wed, 2015-02-18 at 13:02 +0100, Christian König wrote:
Well, what the patch does is just changing where buffers are placed in
memory. E.g. now we place the buffer at the end of memory as well.
So I can imagine at least three possible causes for the issues you see:
1. We haven't
On Tue, 2015-02-24 at 13:41 -0800, H. Peter Anvin wrote:
On 02/24/2015 01:40 PM, H. Peter Anvin wrote:
On 02/24/2015 01:30 AM, Borislav Petkov wrote:
On Mon, Feb 23, 2015 at 03:14:01PM -0800, H. Peter Anvin wrote:
That may cause the same line to be flushed twice. I would suggest,
with Christoph's comments, but overall I think these changes are
great. Please send out as a series you can add:
Reviewed-by: Ross Zwisler ross.zwis...@linux.intel.com
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On Thu, 2015-03-26 at 15:35 +0100, Christoph Hellwig wrote:
On Thu, Mar 26, 2015 at 07:12:23AM -0700, Dan Williams wrote:
+ struct resource *res_mem;
+ int err;
+
+ res_mem = request_mem_region_exclusive(pmem-phys_addr,
pmem-size,
+
On Thu, 2015-03-26 at 17:43 +0100, Christoph Hellwig wrote:
On Thu, Mar 26, 2015 at 05:49:38PM +0200, Boaz Harrosh wrote:
+#define E820_PRAM12
Why the PRAM Name. For one 2/3 of this patch say PMEM the Kconfig
to enable is _PMEM_, the driver stack that gets loaded is pmem,
so
On Thu, 2015-03-26 at 19:02 +0200, Boaz Harrosh wrote:
static void pmem_do_bvec(struct pmem_device *pmem, struct page *page,
unsigned int len, unsigned int off, int rw,
sector_t sector)
{
void *mem = kmap_atomic(page);
+ size_t pmem_off
On Wed, 2015-02-18 at 16:29 -0800, tip-bot for Ross Zwisler wrote:
Commit-ID: 3b68983dc66c61da3ab4191b891084a7ab09e3e1
Gitweb: http://git.kernel.org/tip/3b68983dc66c61da3ab4191b891084a7ab09e3e1
Author: Ross Zwisler ross.zwis...@linux.intel.com
AuthorDate: Tue, 27 Jan 2015 09:53:51
Add kerneldoc comments for pcommit_sfence() describing the purpose of
the pcommit instruction and demonstrating the usage of that instruction.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t
The current algorithm used in clflush_cache_range() can cause the last
cache line of the buffer to be flushed twice. Fix that algorithm so
that each cache line will only be flushed once.
Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Reported-by: H. Peter Anvin h...@zytor.com
Cc: H
On Tue, 2015-04-28 at 16:05 -0700, Andy Lutomirski wrote:
On Tue, Apr 28, 2015 at 3:28 PM, Dan Williams dan.j.willi...@intel.com
wrote:
On Tue, Apr 28, 2015 at 2:06 PM, Andy Lutomirski l...@amacapital.net
wrote:
On Tue, Apr 28, 2015 at 1:59 PM, Dan Williams dan.j.willi...@intel.com
On Thu, 2015-03-26 at 09:06 +0100, Christoph Hellwig wrote:
On Wed, Mar 25, 2015 at 02:21:53PM -0600, Ross Zwisler wrote:
What needed to be fixed with the partition support? I used to have real
numbers for first_minor and passed into alloc_disk(), but simplified it
based
on code found
a contiguous range of reserved
memory as one or more persistent block devices.
Reviewed-by: Ross Zwisler ross.zwis...@linux.intel.com
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-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: Dan Williams dan.j.willi...@intel.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
Cc: linux-nvd...@lists.01.org
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