Hello Steffen & Workqueue People,
As Jason wrote about here a few weeks ago, we've been having issues
with padata. After spending considerable time working to rule out
the possibility that our code was doing something wrong, I've begun
to debug padata and the workqueue subsystems. I've gotten
Hello,
On 09/22/17 19:15, Icenowy Zheng wrote:
Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.
OPPs higher to 816MHz is temporarily dropped, to prevent overheat on
boards with AXP803 support and undervoltage on boards without AXP803
support.
Signed-off-by: Icenowy Zheng
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
drivers/clocksource/Kconfig | 11 ++
drivers/clocksource/arm_arch_timer.c | 39
2 files changed, 50 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
As instability in the architectural timer has been observed on multiple
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
enable the workaround in the SoC's device tree.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dt
obvious problems with this SoC's
architectural timer, and this patch series introduces what I believe is
the simplest workaround. More details are in the commit message for
patch 1. Patch 2 simply enables the workaround in the device tree.
Thanks,
Samuel
Samuel Holland (2):
arm64: arch_timer
the schematic
- Marking the CPU's power supply as such
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
.../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 141 -
1 file changed, 134 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-or
.
Additionally, fix up an incorrect comment, remove an unnecessary header
inclusion, sort existing nodes, and fix some indentation issues.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
.../dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 58 --
1 file changed, 42 inse
On 05/11/18 03:48, Marc Zyngier wrote:
> [+Mark, who co-maintains the arch timer code with me]
>
> Hi Samuel,
>
> On 11/05/18 03:27, Samuel Holland wrote:
>> The Allwinner A64 SoC is known [1] to have an unstable architectural
>> timer, which manifests itself most ob
CPI protocol driver frees its mailbox channel during probing
if the SCP firmware does not respond within a specified timeout. In this
case, if the SCP firmware takes slightly too long to respond,
mbox_chan_received_data races with mbox_free_channel clearing chan->cl.
Signed-off-by: Samuel Hollan
On 01/26/18 09:19, Philipp Rossak wrote:
> This patch adds the thermal zones to the A83T. Sensor 0 is located in the
> cpu cluster 0. Sensor 1 is located in cluster 1 and Sensor 3 is located
> in the gpu.
You mention sensor 3 here, but have sensor 2 in the device tree.
> Signed-off-by: Philipp
On 01/26/18 09:19, Philipp Rossak wrote:
> This patch adds the thermal zones to the H3. We have only one sensor and
> that is placed in the cpu.
>
> Signed-off-by: Philipp Rossak
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
>
reboot.org/pipermail/coreboot/2014-September/078551.html
Samuel Holland (5):
firmware: coreboot: Expose the coreboot table as a bus
firmware: memconsole: Probe via coreboot bus
firmware: vpd: Probe via coreboot bus
firmware: coreboot: Remove unused coreboot_table_find
firmware: coreboot: Ad
Remove the ad-hoc coreboot table search. Now the driver will only be
probed when the necessary coreboot table entry has already been found.
Furthermore, since the coreboot bus takes care of creating the device, a
separate platform device is no longer needed.
Signed-off-by: Samuel Holland <
Remove the ad-hoc coreboot table search. Now the driver will only be
probed when the necessary coreboot table entry has already been found.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
drivers/firmware/google/memconsole-coreboot.c | 49 ++-
1 file chang
Register a simplefb framebuffer when the coreboot table contains a
framebuffer entry.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
drivers/firmware/google/Kconfig| 8 ++
drivers/firmware/google/Makefile | 1 +
drivers/firmware/google/coreboot_t
Now that all users of the coreboot_table_find function have been updated
to hang off the coreboot table bus instead, remove it.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
drivers/firmware/google/coreboot_table.c | 43
drivers/firmware/
This simplifies creating device drivers for hardware or information
described in the coreboot table. It also avoids needing to search
through the table every time a driver is loaded.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
drivers/firmware/google/coreboot_table-acpi.c
On 07/04/18 10:01, Marc Zyngier wrote:
> On Wed, 04 Jul 2018 15:44:36, Andre Przywara wrote:
>> On 04/07/18 15:31, Thomas Gleixner wrote:
>>> On Wed, 4 Jul 2018, Andre Przywara wrote:
On 04/07/18 11:00, Thomas Gleixner wrote:
> On Wed, 4 Jul 2018, Marc Zyngier wrote:
>> On 04/07/18
On 02/28/18 12:14, Jassi Brar wrote:
> On Wed, Feb 28, 2018 at 11:21 PM, Samuel Holland <sam...@sholland.org> wrote:
>> Hi,
>>
>> On 02/28/18 03:16, Jassi Brar wrote:
>>> On Wed, Feb 28, 2018 at 7:57 AM, Samuel Holland <sam...@sholland.org> wrote:
>
On 02/26/18 03:26, Maxime Ripard wrote:
> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote:
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
>>>
>>> Is it needed? The bootloader should fill it with whatever version it
>>> has,
Hi,
On 02/28/18 02:32, Maxime Ripard wrote:
> On Tue, Feb 27, 2018 at 08:27:14PM -0600, Samuel Holland wrote:
>> +/*
>> + * The failure path should not disable the clock or assert the reset,
>> + * because the PSCI implementation in firmware relies on this de
Hi,
On 02/28/18 02:24, Maxime Ripard wrote:
> On Tue, Feb 27, 2018 at 08:27:11PM -0600, Samuel Holland wrote:
>> This series adds support for the "hardware message box" in recent
>> Allwinner sunxi SoCs, used for communication with the ARISC management
>> proce
Hi,
On 02/28/18 02:28, Maxime Ripard wrote:
> On Tue, Feb 27, 2018 at 08:27:12PM -0600, Samuel Holland wrote:
>> This mailbox hardware is present in several Allwinner sun8i and sun50i
>> SoCs. Add a device tree binding for it.
>>
>> Signed-off-by: Samuel H
Hi,
On 02/28/18 03:16, Jassi Brar wrote:
> On Wed, Feb 28, 2018 at 7:57 AM, Samuel Holland <sam...@sholland.org> wrote:
>
>
>> +/*
>> + * The message box hardware provides 8 unidirectional channels. As the
>> mailbox
>> + * framework expects them to
CPI protocol driver frees its mailbox channel during probing
if the SCP firmware does not respond within a specified timeout. In this
case, if the SCP firmware takes slightly too long to respond,
mbox_chan_received_data races with mbox_free_channel clearing chan->cl.
Signed-off-by: Samuel Hollan
contains 8 unidirectional 4-message-deep FIFOs. To fit the
mailbox framework API, this driver combines them into 4 bidirectional
pairs of channels, and only allows one message in each channel to be
queued at a time.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
drivers/mailbox/Kcon
This mailbox hardware is present in several Allwinner sun8i and sun50i
SoCs. Add a device tree binding for it.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
.../devicetree/bindings/mailbox/sunxi-msgbox.txt | 40 ++
1 file changed, 40 insertions(+)
creat
t
included changes to the SoC device trees.
The second patch in the series fixes an issue in the mailbox framework
discovered while writing this driver. It is a re-send of a patch I
originally sent by itself in January.
Samuel Holland (3):
dt-bindings: Add a binding for the sunxi message box
mail
On 10/18/18 10:37, Wenwen Wang wrote:
> In coreboot_table_init(), a for loop is used to copy the entries of the
> coreboot table. For each entry, the header of the entry, which is a
> structure coreboot_table_entry and includes the size of the entry, is
> firstly copied from the IO region
of the cleared area.
Cc: sta...@vger.kernel.org
Fixes: d8ae72427187 ("vt: preserve unicode values corresponding to screen
characters")
Signed-off-by: Samuel Holland
---
drivers/tty/vt/vt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/vt/vt.c b/d
Hi,
On 02/28/18 02:24, Maxime Ripard wrote:
> On Tue, Feb 27, 2018 at 08:27:11PM -0600, Samuel Holland wrote:
>> This series adds support for the "hardware message box" in recent
>> Allwinner sunxi SoCs, used for communication with the ARISC management
>> proce
Hi,
On 02/28/18 02:32, Maxime Ripard wrote:
> On Tue, Feb 27, 2018 at 08:27:14PM -0600, Samuel Holland wrote:
>> +/*
>> + * The failure path should not disable the clock or assert the reset,
>> + * because the PSCI implementation in firmware relies on this de
Hi,
On 02/28/18 02:28, Maxime Ripard wrote:
> On Tue, Feb 27, 2018 at 08:27:12PM -0600, Samuel Holland wrote:
>> This mailbox hardware is present in several Allwinner sun8i and sun50i
>> SoCs. Add a device tree binding for it.
>>
>> Signed-off-by: Samuel Holland
Hi,
On 02/28/18 03:16, Jassi Brar wrote:
> On Wed, Feb 28, 2018 at 7:57 AM, Samuel Holland wrote:
>
>
>> +/*
>> + * The message box hardware provides 8 unidirectional channels. As the
>> mailbox
>> + * framework expects them to be bidirectional
>>
On 02/28/18 12:14, Jassi Brar wrote:
> On Wed, Feb 28, 2018 at 11:21 PM, Samuel Holland wrote:
>> Hi,
>>
>> On 02/28/18 03:16, Jassi Brar wrote:
>>> On Wed, Feb 28, 2018 at 7:57 AM, Samuel Holland wrote:
>>>
>>>
>>>> +/*
>>
Signed-off-by: Samuel Holland
---
drivers/clocksource/Kconfig | 11 ++
drivers/clocksource/arm_arch_timer.c | 39
2 files changed, 50 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8e8a09755d10
As instability in the architectural timer has been observed on multiple
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
enable the workaround in the SoC's device tree.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1
obvious problems with this SoC's
architectural timer, and this patch series introduces what I believe is
the simplest workaround. More details are in the commit message for
patch 1. Patch 2 simply enables the workaround in the device tree.
Thanks,
Samuel
Samuel Holland (2):
arm64: arch_timer
the schematic
- Marking the CPU's power supply as such
Signed-off-by: Samuel Holland
---
.../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 141 -
1 file changed, 134 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
b/arch/arm64
.
Additionally, fix up an incorrect comment, remove an unnecessary header
inclusion, sort existing nodes, and fix some indentation issues.
Signed-off-by: Samuel Holland
---
.../dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 58 --
1 file changed, 42 insertions(+), 16 deletions
On 05/11/18 03:48, Marc Zyngier wrote:
> [+Mark, who co-maintains the arch timer code with me]
>
> Hi Samuel,
>
> On 11/05/18 03:27, Samuel Holland wrote:
>> The Allwinner A64 SoC is known [1] to have an unstable architectural
>> timer, which manifests itself most ob
On 02/26/18 03:26, Maxime Ripard wrote:
> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote:
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
>>>
>>> Is it needed? The bootloader should fill it with whatever version it
>>> has,
CPI protocol driver frees its mailbox channel during probing
if the SCP firmware does not respond within a specified timeout. In this
case, if the SCP firmware takes slightly too long to respond,
mbox_chan_received_data races with mbox_free_channel clearing chan->cl.
Signed-off-by: Samuel H
contains 8 unidirectional 4-message-deep FIFOs. To fit the
mailbox framework API, this driver combines them into 4 bidirectional
pairs of channels, and only allows one message in each channel to be
queued at a time.
Signed-off-by: Samuel Holland
---
drivers/mailbox/Kconfig| 7 +
drivers/mailbo
This mailbox hardware is present in several Allwinner sun8i and sun50i
SoCs. Add a device tree binding for it.
Signed-off-by: Samuel Holland
---
.../devicetree/bindings/mailbox/sunxi-msgbox.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation
t
included changes to the SoC device trees.
The second patch in the series fixes an issue in the mailbox framework
discovered while writing this driver. It is a re-send of a patch I
originally sent by itself in January.
Samuel Holland (3):
dt-bindings: Add a binding for the sunxi message box
mail
On 1/17/21 8:08 PM, Andre Przywara wrote:
> Add simple "allwinner,sun50i-h616-xxx" compatible names to existing
> bindings, and pair them with an existing fallback compatible string,
> as the devices are compatible.
> This covers I2C, infrared, RTC and SPI.
>
> Use enums to group all compatible
On 1/17/21 8:08 PM, Andre Przywara wrote:
> This (relatively) new SoC is similar to the H6, but drops the (broken)
> PCIe support and the USB 3.0 controller. It also gets the management
> controller removed, which in turn removes *some*, but not all of the
> devices formerly dedicated to the ARISC
To save power, gate/reset the hardware block while the system is
asleep or powered off.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index
The binding of R_INTC was updated to allow specifying interrupts other
than the external NMI, since routing those interrupts through the R_INTC
driver allows using them for wakeup.
Update the device trees to use the new binding.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch
multiplexed IRQs to
top-level register bits, it is no longer compatible with the A31 R_INTC.
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Samuel Holland
---
.../allwinner,sun6i-a31-r-intc.yaml | 66 +++
.../allwinner,sun7i-a20-sc-nmi.yaml | 10
-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun6i-a31.dtsi | 4
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4
arch/arm/boot/dts/sun8i-a83t.dtsi| 3 +++
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +++
4 files changed, 14 insertions(+)
diff --git a/arch/arm/boot
On 1/18/21 12:00 AM, Samuel Holland wrote:
> This series cleans up some dead code in the sunxi-cir driver and adds
> system power management hooks.
>
> ---
> Changes from v1:
> - Unregister the RC device first thing in sunxi_ir_remove() [3]
I forgot to add:
Acked-by: Maxim
This series cleans up some dead code in the sunxi-cir driver and adds
system power management hooks.
---
Changes from v1:
- Unregister the RC device first thing in sunxi_ir_remove() [3]
Samuel Holland (4):
media: sunxi-cir: Clean up dead register writes
media: sunxi-cir: Remove unnecessary
On 1/17/21 8:08 PM, Andre Przywara wrote:
> Currently the AXP chip requires to have its IRQ line connected to some
> interrupt controller, and will fail probing when this is not the case.
>
> On a new Allwinner SoC (H616) there is no NMI pin anymore, so the
> interrupt functionality of the AXP
ree binding.
- Update commit messages for accuracy and typos.
Samuel Holland (10):
dt-bindings: irq: sun6i-r: Split the binding from sun7i-nmi
dt-bindings: irq: sun6i-r: Add a compatible for the H3
irqchip/sun6i-r: Use a stacked irqchip driver
irqchip/sun6i-r: Add wakeup support
ARM: dts:
by: Maxime Ripard
Signed-off-by: Samuel Holland
---
drivers/irqchip/irq-sun6i-r.c | 107 --
1 file changed, 101 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c
index 284b56905eb7..4cd3e533740b 100644
---
.
Acked-by: Maxime Ripard
Acked-by: Rob Herring
Signed-off-by: Samuel Holland
---
.../interrupt-controller/allwinner,sun6i-a31-r-intc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml
b
ocumentation.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +-
arch/arm/boo
des a
simple way to add wakeup support to any of its IRQs. That is the next
patch; for now, just the NMI is moved over.
This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
--
-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +++
2 files changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64
The binding of R_INTC was updated to allow specifying interrupts other
than the external NMI, since routing those interrupts through the R_INTC
driver allows using them for wakeup.
Update the device trees to use the new binding.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch
The H3 and H5 SoCs have an additional interrupt controller in the RTC
power domain that can be used to enable wakeup for certain IRQs.
Add a node for it.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions
LIRC_SET_REC_TIMEOUT) while the hardware
is disabled.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 128 ---
1 file changed, 74 insertions(+), 54 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 48be400421cd
Only one register, SUNXI_IR_CIR_REG, is accessed from outside the
interrupt handler, and that register is not accessed from inside it.
As there is no overlap between different contexts, no lock is needed.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 10 --
1 file
The register writes during driver removal occur after the device is
already put back in reset, so they never had any effect.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media
On 1/22/21 4:47 AM, Maxime Ripard wrote:
> On Thu, Jan 21, 2021 at 07:33:54PM -0600, Samuel Holland wrote:
>> On 1/21/21 2:35 PM, Marc Zyngier wrote:
>>> On Sun, 17 Jan 2021 23:50:30 -0600, Samuel Holland wrote:
>>>> Allwinner sun6i/sun8i/sun50i SoCs (A31
On 1/21/21 2:35 PM, Marc Zyngier wrote:
> On Sun, 17 Jan 2021 23:50:30 -0600, Samuel Holland wrote:
>> Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt
>> controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles
>> the external NMI pin,
On 1/6/21 5:38 AM, Chen-Yu Tsai wrote:
> On Wed, Jan 6, 2021 at 7:06 PM Maxime Ripard wrote:
>>
>> On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
>>> On 03/01/2021 10:00, Samuel Holland wrote:
>>>> On boards where the only peripheral connected
Hello,
On 1/14/21 3:06 PM, Marc Zyngier wrote:
> Hi Samuel,
>
> On 2021-01-12 05:59, Samuel Holland wrote:
>
> [...]
>
>> +static void sun6i_r_intc_ack_nmi(void)
>> +{
>> +writel(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
>
> writel_relaxe
On 1/14/21 3:44 PM, Marc Zyngier wrote:
> On Tue, 12 Jan 2021 05:59:44 +,
> Samuel Holland wrote:
>>
>> Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them
>> to the hardware during the syscore phase of suspend and shutdown. Then
>> restore th
ing change
- Only add wakeup capability if "wakeup-source" is present
- Warn but do not error out if setting the wake IRQ fails
- Add "wakeup-source" property to PinePhone device tree
Ondrej Jirman (1):
input: sun4i-lradc-keys - Add wakup support
Samuel Holland (2):
PinePhone volume keys are connected to the LRADC in the A64. Users may
want to use them to wake the device from sleep. Support this by
declaring the LRADC as a wakeup source.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
1 file changed, 1
(sometimes doubling it),
disable the LRADC wakeup source by default.
Signed-off-by: Ondrej Jirman
Signed-off-by: Samuel Holland
---
drivers/input/keyboard/sun4i-lradc-keys.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/input/keyboard/sun4i-lradc
The LRADC provides an interrupt that can be used to wake the system.
Signify this by accepting a "wakeup-source" property in the binding.
Signed-off-by: Samuel Holland
---
.../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml | 2 ++
1 file changed, 2 insertions(+)
The register writes during driver removal occur after the device is
already put back in reset, so they never had any effect.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media
This series cleans up some dead code in the sunxi-cir driver and adds
system power management hooks.
Samuel Holland (4):
media: sunxi-cir: Clean up dead register writes
media: sunxi-cir: Remove unnecessary spinlock
media: sunxi-cir: Factor out hardware initialization
media: sunxi-cir
Only one register, SUNXI_IR_CIR_REG, is accessed from outside the
interrupt handler, and that register is not accessed from inside it.
As there is no overlap between different contexts, no lock is needed.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 10 --
1 file
To save power, gate/reset the hardware block while the system is
asleep or powered off.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index
function: throwing away
the error from clk_prepare_enable and using the wrong type for the
temporary register value.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 128 ---
1 file changed, 74 insertions(+), 54 deletions(-)
diff --git a/drivers/media
If the device suspend process begins before the mmc host's autosuspend
timeout, the host will continue running during system sleep. Avoid
this by forcing runtime suspend during a global suspend transition.
Signed-off-by: Samuel Holland
---
drivers/mmc/host/sunxi-mmc.c | 2 ++
1 file changed, 2
On 9/2/20 10:44 PM, Samuel Holland wrote:
> The controller expects all data it sends/receives to be little-endian.
> Therefore, the packet struct definitions should use the __le16/32/64
> types. Once those are correct, sparse reports several issues with the
> driver code, which ar
Increase #sound-dai-cells on the digital codec to allow using the other
DAIs provided by the codec for AIF2 and AIF3.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts
Increase #sound-dai-cells on the digital codec to allow using the other
DAIs provided by the codec for AIF2 and AIF3.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b
o follow new binding
Arnaud Ferraris (1):
arm64: dts: allwinner: pinephone: Set audio card name
Samuel Holland (6):
ASoC: dt-bindings: sun8i-codec: Increase #sound-dai-cells
ARM: dts: sun8i-a33: Allow using multiple codec DAIs
arm64: dts: allwinner: a64: Allow using multiple codec DAIs
arm64:
ted commit message]
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
index e0db2f1373bc..cf
Now that the sun8i-codec driver supports AIF2 and AIF3, boards can use
them in DAI links. Add the necessary pinmux nodes.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts
Increase sound-dai-cells to 1 to allow using the DAIs in the codec
corresponding to AIF2 and AIF3.
The generic ASoC OF code supports a #sound-dai-cells value of 0 or 1
with no impact to the driver, so this is a backward-compatible change.
Signed-off-by: Samuel Holland
---
.../devicetree
shares clock dividers with AIF3. Using equal clock frequencies
allows the modem and headset to be used at the same time.
Signed-off-by: Samuel Holland
---
.../dts/allwinner/sun50i-a64-pinephone.dtsi | 24 +++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts
simple-audio-card supports either a single DAI link at the top level, or
subnodes with one or more DAI links. To use the secondary AIFs on the
codec, we need to add additional DAI links to the same sound card, so we
need to use the other binding.
Signed-off-by: Samuel Holland
---
arch/arm64
xes: bcfb7ae3f50b ("power: supply: axp20x_usb_power: Only poll while offline")
Signed-off-by: Samuel Holland
---
drivers/power/supply/axp20x_usb_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c
b/drivers/power/supply/axp20
On 10/5/20 6:30 AM, Maxime Ripard wrote:
On Wed, Sep 30, 2020 at 09:11:34PM -0500, Samuel Holland wrote:
When using the I2S, LEFT_J, or RIGHT_J format, the hardware supports
independent BCLK and LRCK inversion control. When using DSP_A or DSP_B,
LRCK inversion is not supported. The register
On 10/5/20 7:01 AM, Maxime Ripard wrote:
> On Wed, Sep 30, 2020 at 09:11:43PM -0500, Samuel Holland wrote:
>> The codec's clock input is shared among all AIFs, and shared with other
>> audio-related hardware in the SoC, including I2S and SPDIF controllers.
>> To ensure
On 10/5/20 8:15 AM, Chen-Yu Tsai wrote:
> On Mon, Oct 5, 2020 at 8:01 PM Maxime Ripard wrote:
>>
>> On Wed, Sep 30, 2020 at 09:11:43PM -0500, Samuel Holland wrote:
>>> The codec's clock input is shared among all AIFs, and shared with other
>>> audio-related h
On 10/5/20 7:04 AM, Maxime Ripard wrote:
> Hi,
>
> On Wed, Sep 30, 2020 at 09:11:46PM -0500, Samuel Holland wrote:
>> The AIF clock control register has the same layout for all three AIFs.
>> The only difference between them is that AIF3 is missing some fields. We
>>
; i2s->slot_width is not actually used in the lrck_period computation.
>>
>> Suggested-by: Samuel Holland
>> Signed-off-by: Clément Péron
>> ---
>> sound/soc/sunxi/sun4i-i2s.c | 36 ++--
>> 1 file changed, 14 insertio
On 8/3/20 9:02 AM, Arnd Bergmann wrote:
> On Mon, Aug 3, 2020 at 5:42 AM Samuel Holland wrote:
>> On 7/31/20 2:29 AM, Arnd Bergmann wrote:
>>> On Fri, Jul 31, 2020 at 12:07 AM Samuel Holland wrote:
>>>>
>>>> The main issue observed was at the call to
On 8/5/20 2:17 AM, Arnd Bergmann wrote:
> On Wed, Aug 5, 2020 at 3:44 AM Samuel Holland wrote:
>> On 8/3/20 9:02 AM, Arnd Bergmann wrote:
>>> On Mon, Aug 3, 2020 at 5:42 AM Samuel Holland wrote:
>>>> All of the command structures are packed, due to the &
In preparation for removing the "#pragma pack(1)" from the driver, fix
all instances where a trailing array member could be replaced by a
flexible array member. Since a flexible array member has zero size, it
introduces no padding, whether or not the struct is packed.
Signed-off-
adjusting the type of one misaligned "reserved" member.
After this change, pahole reports that only one type had its layout
change: the tw_compat_info member of TW_Device_Extension is now
naturally aligned.
Signed-off-by: Samuel Holland
---
drivers/scsi/3w-9xxx.h | 18 ++--
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