with PEX8749-CA RDK.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/pci/pcie/aer/aerdrv_core.c | 56 +-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c
b/drivers/pci/pcie/aer/aerdrv_core.c
he fabric that might be necessary.
+*/
+ if (bus) {
+ struct pci_bus *child;
+
+ list_for_each_entry(child, >children, node)
+ pcie_bus_configure_settings(child);
+ }
+
+ return bus;
}
#endif
--
Sinan Kaya
Qualcomm T
On 11/9/2015 2:09 AM, Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
Current code gives up when 32 bit DMA is not supported.
This problem has been observed on systems without any
memory below 4 gig.
This patch tests 64 bit support before bailing out to find
a working
On 11/9/2015 2:15 AM, Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
The mpt2sas and mpt3sas drivers are spinning forever in
their IRQ handlers if there are a lot of jobs queued up
by the PCIe card. This handler is causing spikes for
the rest of the system and sluggish
On 11/9/2015 3:59 AM, Arnd Bergmann wrote:
On Monday 09 November 2015 08:09:39 Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
Current code gives up when 32 bit DMA is not supported.
This problem has been observed on systems without any
memory below 4 gig.
This patch tests
or PCIe. SBSA requires all inbound PCIe
addresses to be non-translated.
I'll just have to stick with IOMMU for this card.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation
On 11/10/2015 1:27 PM, James Bottomley wrote:
On Tue, 2015-11-10 at 12:19 -0500, Sinan Kaya wrote:
On 11/10/2015 11:47 AM, Arnd Bergmann wrote:
On Tuesday 10 November 2015 11:06:40 Sinan Kaya wrote:
On 11/10/2015 3:38 AM, Arnd Bergmann wrote:
From the email thread, it looks like
On 11/10/2015 11:47 AM, Arnd Bergmann wrote:
On Tuesday 10 November 2015 11:06:40 Sinan Kaya wrote:
On 11/10/2015 3:38 AM, Arnd Bergmann wrote:
> No, as Timur found, the driver is correct and it intentionally
sets the 32-bit mask, and that is guaranteed to work on all sane
hardware. Do
do 64 bit DMA when IOMMU is not
there. I need IOMMU enabled all the time for this card.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
s
parametrising issues with particular hardware. There's no software work
around (except allocating memory with the correct characteristics).
Need confirmation. I'm questioning if we are stuck with this behavior
because of altix or something else. If the latter case, the code could
have used PCI ID
device is in IOMMU translation mode.
Details are in the IORT spec.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
--
To unsubscribe from this list
an upper limit of 1020 as possible interrupt
id. Additional checks have been placed to prevent
out of bounds writes.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/acpi/pci_link.c | 35 ++-
1 file changed, 22 insertions(+), 13 deletions(-)
diff
On 11/9/2015 8:48 AM, Timur Tabi wrote:
Sinan Kaya wrote:
And why kmalloc anyway? Why not leave it on the stack?
char src[] = "hello world";
?
I need to call dma_map_single on this address to convert it to a DMA
address. That's why.
And you can't do that with an obj
On 11/9/2015 4:26 AM, Andy Shevchenko wrote:
On Mon, Nov 9, 2015 at 5:07 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
On 11/8/2015 3:09 PM, Andy Shevchenko wrote:
On Sun, Nov 8, 2015 at 6:52 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
This patch adds supporting utili
On 11/9/2015 10:26 PM, Timur Tabi wrote:
Sinan Kaya wrote:
I created this patch back in March with an older version of the compiler
and older kernel (3.19). I'm no longer able to reproduce this with this
compiler and linux-next.
Thread model: posix
gcc version 4.8.3 20140401 (prerelease
On 11/9/2015 1:25 PM, Rob Herring wrote:
On Sun, Nov 08, 2015 at 09:17:20PM -0500, Sinan Kaya wrote:
On 11/8/2015 12:08 AM, Timur Tabi wrote:
On 11/8/2015 12:08 AM, Timur Tabi wrote:
Sinan Kaya wrote:
+val = val & ~(MAX_BUS_REQ_LEN_MASK << MAX_BUS_WR_REQ_BIT_POS);
+
On 11/9/2015 2:15 AM, Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
The mpt2sas and mpt3sas drivers are spinning forever in
their IRQ handlers if there are a lot of jobs queued up
by the PCIe card. This handler is causing spikes for
the rest of the system and sluggish
On 11/9/2015 8:50 AM, Timur Tabi wrote:
Sinan Kaya wrote:
I'm concerned about this though since you warned. This used to consume
1024 bytes now 4096 bytes.
static int acpi_irq_penalty[ACPI_MAX_IRQS] = {
PIRQ_PENALTY_ISA_ALWAYS,/* IRQ0 timer */
...
}
As long as it's not ever put
esource and devm_ioremap_resource together.
Which one do you want me to remove?
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
--
To unsubscr
return 0;
}
bool hidma_ll_isenabled(struct hidma_lldev *lldev)
Seems rather pointless, what about 'static void ...' and dropping the
return statement?
Daniel K.
Yes, that's what I ended up doing. rc was forgotten there because I had
to restructure code to use the issue_pending API
Current code gives up when 32 bit DMA is not supported.
This problem has been observed on systems without any
memory below 4 gig.
This patch tests 64 bit support before bailing out to find
a working combination.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/m
The MULDIV macro has been designed for small numbers.
Compiler emits an overflow warning on 64 bit systems.
This patch uses 64 bit numbers in order to suppress
warning.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/sg.c | 20 +---
1 file changed, 13 inse
context. This relexes the rest
of the system execution.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/mpt2sas/mpt2sas_base.c | 12
drivers/scsi/mpt3sas/mpt3sas_base.c | 13 +
2 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/driver
On 11/8/2015 12:08 AM, Timur Tabi wrote:
On 11/8/2015 12:08 AM, Timur Tabi wrote:
Sinan Kaya wrote:
+val = val & ~(MAX_BUS_REQ_LEN_MASK << MAX_BUS_WR_REQ_BIT_POS);
+val = val | (mgmtdev->max_write_request << MAX_BUS_WR_REQ_BIT_POS);
+val = val & ~(MAX_BUS_
On 11/8/2015 2:13 PM, kbuild test robot wrote:
Hi Sinan,
[auto build test WARNING on: robh/for-next]
[also build test WARNING on: v4.3 next-20151106]
url:
https://github.com/0day-ci/linux/commits/Sinan-Kaya/ma-add-Qualcomm-Technologies-HIDMA-driver/20151108-125824
base: https
On 11/5/2015 2:56 PM, Andy Shevchenko wrote:
On Thu, Nov 5, 2015 at 9:31 PM, Andy Shevchenko
<andy.shevche...@gmail.com> wrote:
On Thu, Nov 5, 2015 at 8:32 PM, Sinan Kaya <ok...@codeaurora.org> wrote:
On 11/5/2015 1:07 PM, Andy Shevchenko wrote:
Let's try again.
stati
On 11/8/2015 3:09 PM, Andy Shevchenko wrote:
On Sun, Nov 8, 2015 at 6:52 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
This patch adds supporting utility functions
for selftest. The intention is to share the self
test code between different drivers.
Supported test cases incl
On 11/8/2015 12:13 AM, Timur Tabi wrote:
Sinan Kaya wrote:
+static int dma_selftest_sg(struct dma_device *dmadev,
+struct dma_chan *dma_chanptr, u64 size,
+unsigned long flags)
+{
+dma_addr_t src_dma, dest_dma, dest_dma_it;
+u8 *dest_buf;
+u32 i, j = 0
On 11/8/2015 11:11 AM, Timur Tabi wrote:
Sinan Kaya wrote:
-#define ACPI_MAX_IRQS256
+#define ACPI_MAX_IRQS1020
Why 1020? Why not 1024?
1020 is the maximum interrupt ID that can be directed to an ARM SPI
interrupt according to ARM architecture.
--
Sinan Kaya
Qualcomm
On 11/8/2015 3:47 PM, Andy Shevchenko wrote:
On Sun, Nov 8, 2015 at 6:53 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
since you warned. This used to consume
1024 bytes now 4096 bytes.
static int acpi_irq_penalty[ACPI_MAX_IRQS] = {
PIRQ_PENALTY_ISA_ALWAYS,/* IRQ0 timer */
...
}
Sinan
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Ce
an upper limit of 1020 as possible
interrupt id.
1020 is the maximum interrupt ID that can be assigned to
an ARM SPI interrupt according to ARM architecture.
Additional checks have been placed to prevent out of bounds
writes.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
driver
driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 61
drivers/dma/qcom/Kconfig | 11 +
d
This patch adds support for hidma engine. The driver consists
of two logical blocks. The DMA engine interface and the
low-level interface. The hardware only supports memcpy/memset
and this driver only support memcpy interface. HW and driver
doesn't support slave interface.
Signed-off-by: Sinan
This patch adds supporting utility functions for selftest.
The intention is to share the self test code between
different drivers.
Supported test cases include:
1. dma_map_single
2. streaming DMA
3. coherent DMA
4. scatter-gather DMA
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
d
* remove the checks after platform_get_resource.
* reorder the pm calls in failure path.
* simplify bit clear and set operations.
* correct device tree documentation compatible string
* clean unnecessary initializations and use unsigned int for
iterator types
Sinan Kaya (4):
dma: qcom_bam_dma: move
Creating a QCOM directory for all QCOM DMA source
files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
drivers/dma/qcom/Kconfig
an upper limit of 1020 as possible
interrupt id.
1020 is the maximum interrupt ID that can be assigned to
an ARM SPI interrupt according to ARM architecture.
Additional checks have been placed to prevent out of bounds
writes.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
driver
ifferent from PCIe SRIOV passthrough.
Pinning guest removes use cases like ballooning/overcommit but that is a
choice for end user to make: whether he wants additional I/O performance
or wants higher memory utilization at the cost of lower I/O performance.
--
Sinan Kaya
Qualcomm Technologies,
I go and invent my own mechanism, I'd like to have ideas on what
an acceptable solution would look like. Especially, I'm looking for a
generic implementation that could plug into any DMA engine HW.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm
rs are pretty much defined,
isn't it?
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-kern
On 11/12/2015 4:53 AM, Andy Shevchenko wrote:
> On Thu, Nov 12, 2015 at 8:41 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
>> The Qualcomm Technologies HIDMA device has been designed
>> to support virtualization technology. The driver has been
>> divided into two to
driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 61
drivers/dma/qcom/Kconfig | 10 +
d
This patch adds support for hidma engine. The driver consists
of two logical blocks. The DMA engine interface and the
low-level interface. The hardware only supports memcpy/memset
and this driver only support memcpy interface. HW and driver
doesn't support slave interface.
Signed-off-by: Sinan
variable names where possible.
* remove error check after platform_get_resource
* return the error code from device read functions
Changes from V4: (https://lkml.org/lkml/2015/11/12/19)
* remove dev_dbg messages
* seperate selftest code from the series
Sinan Kaya (3):
dma: qcom_bam_dma: move to qcom
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
drivers/dma/qcom/Kconfig
Changes from V4 (https://lkml.org/lkml/2015/11/12/18)
* Seperate the series from HIDMA driver
Sinan Kaya (2):
dmaselftest: add memcpy selftest support functions
dma: qcom_hidma: add self test hooks
drivers/dma/dmaengine.h | 2 +
drivers/dma/dmaselftest.c | 638
Add hooks for the self test code into the probe routine.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile | 2 +-
drivers/dma/qcom/hidma.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/qcom/Makefile b/drivers/dma/qcom/Ma
This patch adds supporting utility functions for selftest.
The intention is to share the self test code between
different drivers.
Supported test cases include:
1. dma_map_single
2. streaming DMA
3. coherent DMA
4. scatter-gather DMA
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
d
On 11/12/2015 4:56 AM, Andy Shevchenko wrote:
> On Thu, Nov 12, 2015 at 8:14 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
>> The ACPI compiler uses the extended format when used
>> interrupt numbers are greater than 256. The PCI link code
>> currently only supports simpl
of the compiler
and older kernel (3.19). I'm no longer able to reproduce this with this
compiler and linux-next.
Thread model: posix
gcc version 4.8.3 20140401 (prerelease) (crosstool-NG
linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04)
I'll drop this patch.
--
Sinan Kaya
Qualcomm Technologies, Inc
On 11/9/2015 1:19 PM, Rob Herring wrote:
On Sat, Nov 07, 2015 at 11:53:00PM -0500, Sinan Kaya wrote:
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
memcpy/memset
On 11/9/2015 9:33 AM, Arnd Bergmann wrote:
On Monday 09 November 2015 09:07:36 Sinan Kaya wrote:
On 11/9/2015 3:59 AM, Arnd Bergmann wrote:
On Monday 09 November 2015 08:09:39 Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
Current code gives up when 32 bit DMA
On 11/8/2015 3:35 PM, Andy Shevchenko wrote:
On Sun, Nov 8, 2015 at 6:07 PM, Sinan Kaya <ok...@codeaurora.org> wrote:
The ACPI compiler uses the extended format when
used interrupt numbers are greater than 256.
The PCI link code currently only supports simple
interrupt format. The IRQ n
driver is exected in the guest OS context.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 42 +
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drive
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. This version of the driver
does not support virtualization on this release and only
memcpy interface support is included.
Signed-off-by: Sinan Kaya <
ith 1.0 BTW.
Since the same IP goes into multiple chips, why would you list the chip
name here and submit patches multiple times for each single chip.
or to follow what Timur did, I can do this.
"qcom,qdf2xxx-hidma-mgmt-1.0"
qdf2xxx would become the chip family.
--
Sinan Kaya
Qualcom
On 11/2/2015 11:33 AM, Arnd Bergmann wrote:
On Sunday 01 November 2015 13:50:53 Sinan Kaya wrote:
The issue is not writel_relaxed vs. writel. After I issue reset, I need
wait for some time to confirm reset was done. I can use readl_polling
instead of mdelay if we don't like mdelay.
I meant
On 11/2/2015 10:57 AM, Rob Herring wrote:
On Mon, Nov 2, 2015 at 12:07 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
The Qualcomm Technologies HIDMA device has been designed
to support virtualization technology. The driver has been
divided into two to follow the hardware design. The mana
doesn't use any of the typical AHB/AXI ARM buses.
I'm familiar with how PCI endpoints works. While the first read in a
typical PCI endpoint ISR flushes all outstanding requests traditionally
to the destination, this concept does not apply here for this HW.
--
Sinan Kaya
Qualcomm Technologies
, please have this info added to the spec. I can work
with the designers for the next chip.
Unaligned access on the current hardware returns incomplete values or
can cause bus faults. The behavior is undefined.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc
On 11/3/2015 2:44 AM, Dan Williams wrote:
On Mon, Nov 2, 2015 at 10:30 PM, Vinod Koul <vinod.k...@intel.com> wrote:
On Mon, Nov 02, 2015 at 11:18:37PM -0500, Sinan Kaya wrote:
On 11/2/2015 11:15 PM, Vinod Koul wrote:
On Mon, Nov 02, 2015 at 01:07:38AM -0500, Sinan Kaya wrote:
This
guess you can remove the entire debugfs
file really ;-)
ok, I need some facility to print out stuff when problems happened.
Would you rather use sysfs?
sysfs would be less appropriate, as that requires providing a stable ABI
for user space. I think ftrace should provide what you need. Let me know
On 11/1/2015 3:21 PM, Timur Tabi wrote:
Sinan Kaya wrote:
However, after issuing the command; I still need to wait some amount of
time until hardware acknowledges the commands like reset/enable/disable.
These are relatively faster operations happening in microseconds. That's
why, I have
QEMU.
I'll put checks that the value needs to come from either
DTS/ACPI/command line.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
On 10/30/2015 10:50 AM, Mark Rutland wrote:
The documentation above didn't state this was an 8-bit quantity, and you
save nothing by doing this (all values in the binary format are padded
to 4-byte alignment).
done.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation
On 10/30/2015 5:34 AM, Arnd Bergmann wrote:
On Thursday 29 October 2015 23:08:12 Sinan Kaya wrote:
diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
new file mode 100644
index 000..81674ab
--- /dev/null
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
memcpy/memset and this driver only support memcpy
interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
to the guest machine for control.
This management driver will be used by the system
admin to monitor/reset the execution state of the DMA
channels. This will be the management interface.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 56 ++
d
This patch adds supporting utility functions
for selftest. The intention is to share the self
test code between different drivers.
Supported test cases include:
1. dma_map_single
2. streaming DMA
3. coherent DMA
4. scatter-gather DMA
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
d
wo for now. One of them is DMA Engine slave drivers,
though I didn't notice if you are using tasklet's here.
Otherwise it's okay.
I'm keeping it as it is for maintenance reasons.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc.
On 11/3/2015 11:46 AM, Timur Tabi wrote:
Sinan Kaya wrote:
1. Bug in ARM64 DMA subsystem.
2. Bug in IOMMU driver.
3. Bug in another newly introduced driver. The new driver would hog the
CPU and won't allow HIDMA interrupts to execute. Therefore, the test
times out.
Which driver?
Some other
On 11/3/2015 11:55 AM, Arnd Bergmann wrote:
On Tuesday 03 November 2015 11:33:18 Sinan Kaya wrote:
On 11/3/2015 10:59 AM, Arnd Bergmann wrote:
On Tuesday 03 November 2015 10:10:21 Sinan Kaya wrote:
I don't see anywhere in the SBSA spec addendum that the PCI
configuration space section
.
This relexes the rest of the system execution.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/mpt2sas/mpt2sas_base.c | 13 +
drivers/scsi/mpt3sas/mpt3sas_base.c | 14 ++
2 files changed, 19 insertions(+), 8 deletions(-)
mode change 100644 =&g
Current code gives up when 32 bit DMA is not supported.
This patch tests 64 bit support before bailing out in
such conditions.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 22 +-
1 file changed, 21 insertions(+), 1 de
015 at 11:18:37PM -0500, Sinan Kaya wrote:
On 11/2/2015 11:15 PM, Vinod Koul wrote:
On Mon, Nov 02, 2015 at 01:07:38AM -0500, Sinan Kaya wrote:
This one; on the other hand, is selftest to verify hardware is
working as expected during power up.
I prefer to have such nice case by run time para
Current code gives up when 32 bit DMA is not supported.
This patch tests 64 bit support before bailing out in
such conditions.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/mpt2sas/mpt2sas_base.c | 21 -
1 file changed, 20 insertions(+), 1 de
The MULDIV macro has been designed for small
numbers. It emits an overflow warning on 64 bit
systems. This patch places type casts in the
parameters to fix the compiler warning.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/sg.c | 5 -
1 file changed, 4 insertions
On 11/5/2015 7:05 AM, Vinod Koul wrote:
On Wed, Nov 04, 2015 at 09:42:46PM -0500, Sinan Kaya wrote:
Here is what I proposed.
- a common file that gets compiled into a module that wants to use
self-test with a public API. It can be called from driver's probe
routine.
- the test is independent
<<= 9;
do_div(nsecs, 125);
...
}
Let's try again.
static inline u64 mult_frac64(u64 x, u32 numer, u32 denom) {
u64 rem = x % denom;
u64 quot = do_div(x, denom);
u64 mul = rem * numer;
return (quot * numer) + do_div(mul, denom);
}
I'll do a s/
On 11/5/2015 2:56 PM, Andy Shevchenko wrote:
One more look to the users of MULDIV.
They all seems 32 bit for x.
It means you don't need two do_div()s at all.
Just do something like:
u64 d = x * numer;
do_div(d, denom);
return d;
OK. I assume you want a change only in this file.
--
Sinan
On 11/5/2015 11:17 AM, Sinan Kaya wrote:
On 11/5/2015 7:05 AM, Vinod Koul wrote:
On Wed, Nov 04, 2015 at 09:42:46PM -0500, Sinan Kaya wrote:
Here is what I proposed.
- a common file that gets compiled into a module that wants to use
self-test with a public API. It can be called from
This patch adds supporting utility functions
for selftest. The intention is to share the self
test code between different drivers.
Supported test cases include:
1. dma_map_single
2. streaming DMA
3. coherent DMA
4. scatter-gather DMA
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
d
.
The management driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 62
drivers/dma/qcom/K
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
memcpy/memset and this driver only support memcpy
interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
Creating a QCOM directory for all QCOM DMA
source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 13 +-
drivers/dma/Makefile |2 +-
drivers/dma/qcom/Kconfig |9 +
drivers/dma/qcom/Makefile |1 +
drivers/dma/qcom/bam_dma.c
not be safe in a PCI
device
- For the ones that would be safe on PCI as weel, use
readl_relaxed()/writel_relaxed() without a comment on each one,
but clarify somewhere that these are all intentional.
Makes sense.
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Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center
On 11/3/2015 5:22 AM, Andy Shevchenko wrote:
On Mon, Nov 2, 2015 at 8:07 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
The Qualcomm Technologies HIDMA device has been designed
to support virtualization technology. The driver has been
divided into two to follow the hardware
On 11/3/2015 5:10 AM, Andy Shevchenko wrote:
On Mon, Nov 2, 2015 at 8:07 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
ata structure between them otherwise virtualization will break.
I consider the management driver a client of the DMA engine API at this
moment.
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Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Fo
evice-tree
naming conventions?
I'm more of an ACPI person than DTS.
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Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
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On 10/30/2015 11:33 PM, Jon Masters wrote:
Hi Andy,
On 10/30/2015 04:15 PM, Andy Shevchenko wrote:
On Fri, Oct 30, 2015 at 10:08 PM, Al Stone <al.st...@linaro.org> wrote:
On 10/30/2015 01:01 PM, Mark Rutland wrote:
On Fri, Oct 30, 2015 at 02:48:06PM -0400, Sinan Kaya wrote:
Th
On 11/2/2015 11:15 PM, Vinod Koul wrote:
On Mon, Nov 02, 2015 at 01:07:38AM -0500, Sinan Kaya wrote:
This patch adds supporting utility functions
for selftest. The intention is to share the self
test code between different drivers.
Supported test cases include:
1. dma_map_single
2. streaming
On 11/2/2015 4:30 PM, Arnd Bergmann wrote:
On Saturday 31 October 2015 02:51:46 Sinan Kaya wrote:
On 10/30/2015 5:34 AM, Arnd Bergmann wrote:
On Thursday 29 October 2015 23:08:12 Sinan Kaya wrote:
diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
b/Documentation
On 11/3/2015 12:43 PM, Sinan Kaya wrote:
In any case, the hardware document says 32 bit configuration space
access to the host bridge only. I'll get more clarification.
I got confirmation this morning that this chip supports 32 bit access to
the root complex configuration space. 8/16/32 bits
On 11/5/2015 3:48 AM, Andy Shevchenko wrote:
On Thu, Nov 5, 2015 at 6:46 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
The MULDIV macro has been designed for small
numbers. It emits an overflow warning on 64 bit
systems. This patch places type casts in the
parameters to fix the co
On 10/30/2015 2:25 PM, Mark Rutland wrote:
It does appear that it's not relevant to this device and driver, given
the lack of clients, unless I've misunderstood?
You are right. Kernel and guest machine kernel are the only user of this
DMA device.
No other HW devices.
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Sinan Kaya
On 10/30/2015 11:00 AM, Mark Rutland wrote:
On Thu, Oct 29, 2015 at 11:08:12PM -0400, Sinan Kaya wrote:
The Qualcomm Technologies HIDMA device has been designed
to support virtualization technology. The driver has been
divided into two to follow the hardware design. The management
driver
thanks for the review. I'll work on these.
On 10/30/2015 6:24 AM, Arnd Bergmann wrote:
On Thursday 29 October 2015 23:08:13 Sinan Kaya wrote:
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. This version
https://wiki.linaro.org/LEG/Engineering/Kernel/ACPI/TablePriorities
It does appear that it's not relevant to this device and driver, given
the lack of clients, unless I've misunderstood?
Yeah, just a side note.
OK.
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Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Cente
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