This adds Qualcomm PRNG driver device tree binding documentation
to use as an example in dts trees.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
Documentation/devicetree/bindings/rng/qcom,prng.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
This patch set adds hardware RNG driver wich is used to control the
Qualcomm's PRNG hardware block.
The first patch document the DT bindings needed to sucessfuly probe
the driver and the second patch adds the driver.
Comments are welecome!
Stanimir Varbanov (2):
ARM: DT: msm: Add Qualcomm's
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/char/hw_random/Kconfig | 12 +++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/msm-rng.c | 211
Hi Ted,
On 10/03/2013 07:51 PM, Theodore Ts'o wrote:
On Thu, Oct 03, 2013 at 05:52:33PM +0300, Stanimir Varbanov wrote:
This patch set adds hardware RNG driver wich is used to control the
Qualcomm's PRNG hardware block.
The first patch document the DT bindings needed to sucessfuly probe
Hi Stephen,
Thanks for the quick review!
On 10/03/2013 10:25 PM, Stephen Boyd wrote:
On 10/03/13 07:52, Stanimir Varbanov wrote:
+#define PRNG_CONFIG_MASK0x0002
+#define PRNG_CONFIG_HW_ENABLE BIT(1)
These two are the same so please drop the PRNG_CONFIG_MASK define and
just
Hi Ivan,
Few comments below.
On 10/07/2013 10:44 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
Hi Ivan,
Minor comments below.
On 10/07/2013 10:44 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of
Hi Georgi,
Thanks for the patch.
I have some commnets below.
On 09/16/2013 05:23 PM, Georgi Djakov wrote:
This platform driver adds the support of Secure Digital Host Controller
Interface compliant controller found in Qualcomm MSM chipsets.
CC: Asutosh Das asuto...@codeaurora.org
CC:
and the second patch adds the driver.
Comments are welecome!
Stanimir Varbanov (2):
ARM: DT: msm: Add Qualcomm's PRNG driver binding document
hwrng: msm: Add PRNG support for MSM SoC's
.../devicetree/bindings/rng/qcom,prng.txt | 17 ++
drivers/char/hw_random/Kconfig
This adds Qualcomm PRNG driver device tree binding documentation
to use as an example in dts trees.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
Documentation/devicetree/bindings/rng/qcom,prng.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/char/hw_random/Kconfig | 12 +++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/msm-rng.c | 195
Hi Stephen,
Thanks for the review.
On 10/11/2013 11:46 PM, Stephen Boyd wrote:
On 10/11, Stanimir Varbanov wrote:
This adds Qualcomm PRNG driver device tree binding documentation
to use as an example in dts trees.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
Documentation
Hi Stephen,
Thanks for the review.
On 10/11/2013 11:37 PM, Stephen Boyd wrote:
On 10/11, Stanimir Varbanov wrote:
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
Just nitpicks.
diff --git
This adds Qualcomm PRNG driver device tree binding documentation
to use as an example in dts trees.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
Documentation/devicetree/bindings/rng/qcom,prng.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
set adds hardware RNG driver wich is used to control the
Qualcomm's PRNG hardware block.
The first patch document the DT bindings needed to sucessfuly probe
the driver and the second patch adds the driver.
Comments are welecome!
Stanimir Varbanov (2):
ARM: DT: msm: Add Qualcomm's PRNG driver
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/char/hw_random/Kconfig | 12 +++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/msm-rng.c | 197
Hi Andy,
Thanks for the patch.
On 02/25/2014 01:11 AM, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a
on Qualcomm MSM SoCs.
IMO, after this change the MSM abbreviation in help clause is
irrelevant, could you remove it?
Reviewed-by: Stanimir Varbanov svarba...@mm-sol.com
regards,
Stan
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Hi, Rohit
Thanks for the patch!
On 05/21/2013 09:32 PM, Rohit Vaswani wrote:
This cleans up the gpio-msm-v2 driver of all the global define usage.
The number of gpios are now defined in the device tree. This enables
adding irqdomain support as well.
Signed-off-by: Rohit Vaswani
Hi Rohit,
Thanks for the new version!
I have few more comments below.
On 05/23/2013 03:29 AM, Rohit Vaswani wrote:
This cleans up the gpio-msm-v2 driver of all the global define usage.
The number of gpios are now defined in the device tree. This enables
adding irqdomain support as well.
On 10/15/2013 05:11 PM, Stanimir Varbanov wrote:
This adds Qualcomm PRNG driver device tree binding documentation
to use as an example in dts trees.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Dear DT binding maintainers,
I'd like to receive some comments or maybe an Ack
On 10/15/2013 05:11 PM, Stanimir Varbanov wrote:
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Hi Matt, Herbert,
Sorry for the noise but this patch staying for a while in mailing list
and I'd like
Hi Herbert,
On 10/23/2013 12:45 PM, Herbert Xu wrote:
On Wed, Oct 23, 2013 at 12:41:10PM +0300, Stanimir Varbanov wrote:
On 10/15/2013 05:11 PM, Stanimir Varbanov wrote:
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov
Hi Stephen,
On 10/04/2013 07:37 PM, Stephen Boyd wrote:
On 10/04/13 09:31, Stanimir Varbanov wrote:
+static int msm_rng_probe(struct platform_device *pdev)
+{
+ struct msm_rng *rng;
+ struct device_node *np;
+ struct resource res;
+ int ret;
+
+ np = of_node_get(pdev-dev.of_node
Hi Ted,
On 10/04/2013 09:10 PM, Theodore Ts'o wrote:
On Fri, Oct 04, 2013 at 07:23:50PM +0300, Stanimir Varbanov wrote:
I guess that it should follow NIST 800-90 recommendation, but I'm not
aware what DRBG mechanism is used.
To be honest I really don't know the hardware implementation
Hi Ted, Peter,
On 10/09/2013 06:07 PM, H. Peter Anvin wrote:
On 10/09/2013 07:46 AM, Stanimir Varbanov wrote:
No, there is no public documentation for the block. Here is the driver
documentation which I used as a base [1].
My guess was that - if it is PRNG (got from hardware description
Hi Suman,
Thanks for the patch.
On 09/03/2013 08:52 PM, Suman Anna wrote:
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This patch adds the
base support for parsing the DT nodes, and removes the code
dealing with the traditional platform
long
- move blocksize boundary check on function begging and
clear BYTECOUNT registers on first processing block
This driver is based on Codeaurora's driver found at [1]
[1]
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/crypto/msm?h=msm-3.10
Stanimir Varbanov (3
Modify crypto Kconfig and Makefile in order to build the qce
driver and adds qce Makefile as well.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/Kconfig | 15 +++
drivers/crypto/Makefile |1 +
drivers/crypto/qce/Makefile |6 ++
3
Here is Qualcomm crypto driver device tree binding documentation
to used as a reference example.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/crypto/qcom-qce.txt| 25
1 files changed, 25 insertions(+), 0 deletions(-)
create
Hi Joe,
On 06/09/2014 07:46 PM, Joe Perches wrote:
On Mon, 2014-06-09 at 15:08 +0300, Stanimir Varbanov wrote:
The driver is separated by functional parts. The core part
implements a platform driver probe and remove callbaks.
The probe enables clocks, checks crypto version, initialize
Hi Kumar,
+
+static struct platform_driver qcom_ahci_driver = {
+ .probe = qcom_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = qcom_ahci_qcom,
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ahci_of_match,
+
Hi Bjorn,
Thanks for the patches.
snip
Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p
patches for mainline.
It could be argued that smd is a bus and should go in drivers/bus, but
for the rest I fear that we just created drivers/soc/qcom as another
dumping ground for
Thanks for the review!
On 04/28/2014 11:00 AM, Herbert Xu wrote:
On Mon, Apr 14, 2014 at 03:48:40PM +0300, Stanimir Varbanov wrote:
+if (IS_AES(flags)) {
+switch (keylen) {
+case AES_KEYSIZE_128:
+case AES_KEYSIZE_256:
+break
Thanks for the review!
On 04/28/2014 11:18 AM, Herbert Xu wrote:
On Mon, Apr 14, 2014 at 03:48:40PM +0300, Stanimir Varbanov wrote:
+} else if (IS_DES(flags)) {
+u32 tmp[DES_EXPKEY_WORDS];
+
+if (keylen != QCE_DES_KEY_SIZE)
+goto badkey
Thanks for the review!
On 04/28/2014 11:50 AM, Herbert Xu wrote:
On Mon, Apr 14, 2014 at 03:48:37PM +0300, Stanimir Varbanov wrote:
+if (backlog)
+backlog-complete(backlog, -EINPROGRESS);
The completion function needs to be called with BH disabled.
Cheers,
This is new
Hi Herbert,
On 04/28/2014 11:59 AM, Herbert Xu wrote:
On Mon, Apr 14, 2014 at 03:48:37PM +0300, Stanimir Varbanov wrote:
+#define QCE_MAJOR_VERSION5 0x05
+#define QCE_QUEUE_LENGTH50
What is the purpose of this software queue? Why can't you directly
feed the requests to the hardware
and
easier for review, hope I done well. I'll appreciate any review
comments which will help me to make this code clear and ready
for mainline kernel.
regards,
Stan
Stanimir Varbanov (9):
crypto: qce: Add core driver implementation
crypto: qce: Add register defines
crypto: qce: Add dma and sg
-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/core.c | 333 ++
drivers/crypto/qce/core.h | 69 ++
2 files changed, 402 insertions(+)
create mode 100644 drivers/crypto/qce/core.c
create mode 100644 drivers/crypto/qce/core.h
This adds dmaengine and sg-list helper functions used by
other parts of the crypto driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/dma.c | 201 +++
drivers/crypto/qce/dma.h | 57 ++
2 files changed, 258
Here are all register addresses and bit/masks used by the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/regs-v5.h | 327 +++
1 file changed, 327 insertions(+)
create mode 100644 drivers/crypto/qce/regs-v5.h
diff
Here is the implementation of AES, DES and 3DES crypto API
callbacks, the crypto register alg function, the async request
handler and its dma done callback function.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/ablkcipher.c | 397
Here is the implementation and registration of ahash crypto type.
It includes sha1, sha256, hmac(sha1) and hmac(sha256).
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/sha.c | 595 +++
drivers/crypto/qce/sha.h | 74
Adds Makefile needed to build the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/Makefile | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 drivers/crypto/qce/Makefile
diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile
new
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/common.c | 424
drivers/crypto/qce/common.h | 111
2 files changed, 535 insertions(+)
create mode 100644 drivers/crypto/qce/common.c
create mode 100644 drivers/crypto
Modify crypto Kconfig and Makefile in order to build the qce
driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/Kconfig | 10 ++
drivers/crypto/Makefile | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
Here is Qualcomm crypto driver device tree binding documentation
to used as a reference example.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/crypto/qcom-qce.txt| 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Hi,
On 04/03/2014 07:24 PM, Kumar Gala wrote:
On Apr 3, 2014, at 11:17 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Here are all register addresses and bit/masks used by the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/regs-v5.h | 327
tested this driver during wake up of the crypto driver. With your
additions to bam_start_dma() in regards to EOT interrupts I successfully
passed the crypto framework test vectors for the implemented algorithms.
Tested-by: Stanimir Varbanov svarba...@mm-sol.com
regards,
Stan
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To unsubscribe from
On 04/03/2014 09:25 PM, Josh Cartwright wrote:
Nitworthy comments :).
On Thu, Apr 03, 2014 at 07:18:00PM +0300, Stanimir Varbanov wrote:
[..]
+++ b/drivers/crypto/qce/dma.c
[..]
+int qce_dma_request(struct device *dev, struct qce_dma_data *dma)
+{
+unsigned int memsize;
+void
Hi Courtney,
Thanks for the comments!
On 04/04/2014 02:15 AM, Courtney Cavin wrote:
On Thu, Apr 03, 2014 at 06:18:00PM +0200, Stanimir Varbanov wrote:
This adds dmaengine and sg-list helper functions used by
other parts of the crypto driver.
Signed-off-by: Stanimir Varbanov svarba...@mm
Hi Josh,
Thanks for the comments!
On 04/03/2014 09:19 PM, Josh Cartwright wrote:
Hey Stanimir-
Just a few comments/questions from a quick scan of your patchset:
On Thu, Apr 03, 2014 at 07:17:58PM +0300, Stanimir Varbanov wrote:
[..]
+++ b/drivers/crypto/qce/core.c
[..]
+
+static
Hi
On 04/08/2014 01:42 AM, Courtney Cavin wrote:
On Fri, Apr 04, 2014 at 03:07:13PM +0200, Stanimir Varbanov wrote:
diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h
new file mode 100644
index ..932b02fd8f25
--- /dev/null
+++ b/drivers/crypto/qce/dma.h
@@ -0,0
Hi Courtney,
Thanks for the review!
On 04/04/2014 02:38 AM, Courtney Cavin wrote:
On Thu, Apr 03, 2014 at 06:17:58PM +0200, Stanimir Varbanov wrote:
This adds core driver files. The core part is implementing a
platform driver probe and remove callbaks, the probe enables
clocks, checks crypto
/2014 03:48 PM, Stanimir Varbanov wrote:
Hi,
Here is the second version of the patch set. This time tagged
as an RFC to avoid confusions. The driver is splitted by files
and is buildable at the last patch. When the review has finished
1/9 to 7/9 could be squashed in one patch.
Any comments
Hi Stephen,
thanks for the comments.
On 04/09/2014 03:09 AM, Stephen Boyd wrote:
On 04/03, Stanimir Varbanov wrote:
+static void qce_ahash_dma_done(void *data)
+{
+struct crypto_async_request *async_req = data;
+struct ahash_request *req = ahash_request_cast(async_req);
+struct
Hi Courtney,
On 04/09/2014 01:00 AM, Courtney Cavin wrote:
On Tue, Apr 08, 2014 at 06:26:44PM +0200, Stanimir Varbanov wrote:
On 04/04/2014 02:38 AM, Courtney Cavin wrote:
On Thu, Apr 03, 2014 at 06:17:58PM +0200, Stanimir Varbanov wrote:
This adds core driver files. The core part
Hi Stephen,
On 04/11/2014 11:12 PM, Stephen Boyd wrote:
On 04/10, Stanimir Varbanov wrote:
On 04/09/2014 03:09 AM, Stephen Boyd wrote:
On 04/03, Stanimir Varbanov wrote:
+
+ return 0;
+}
+
+static int qce_ahash_import(struct ahash_request *req, const void *in)
+{
+ struct
readable and
easier for review, hope I done well. I'll appreciate any review
comments which will help me to make this code clear and ready
for mainline kernel.
Stanimir Varbanov (9):
crypto: qce: Add core driver implementation
crypto: qce: Add register defines
crypto: qce: Add dma and sg helpers
-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/core.c | 295 ++
drivers/crypto/qce/core.h | 73
2 files changed, 368 insertions(+)
create mode 100644 drivers/crypto/qce/core.c
create mode 100644 drivers/crypto/qce/core.h
This adds dmaengine and sg-list helper functions used by
other parts of the crypto driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/dma.c | 188 +++
drivers/crypto/qce/dma.h | 58 +++
2 files changed
Here are all register addresses and bit/masks used by the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/regs-v5.h | 331 +++
1 file changed, 331 insertions(+)
create mode 100644 drivers/crypto/qce/regs-v5.h
diff
Here is the implementation of AES, DES and 3DES crypto API
callbacks, the crypto register alg function, the async request
handler and its dma done callback function.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/ablkcipher.c | 403
Here is the implementation and registration of ahash crypto type.
It includes sha1, sha256, hmac(sha1) and hmac(sha256).
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/sha.c | 591 +++
drivers/crypto/qce/sha.h | 81
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/common.c | 438
drivers/crypto/qce/common.h | 104 +++
2 files changed, 542 insertions(+)
create mode 100644 drivers/crypto/qce/common.c
create mode 100644 drivers/crypto
Adds Makefile needed to build the driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/Makefile | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 drivers/crypto/qce/Makefile
diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile
new
Modify crypto Kconfig and Makefile in order to build the qce
driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/Kconfig | 10 ++
drivers/crypto/Makefile | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
Here is Qualcomm crypto driver device tree binding documentation
to be used as a reference example.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/crypto/qcom-qce.txt| 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Hi Lee,
Thanks for the comments.
On 07/09/2014 05:34 PM, Lee Jones wrote:
On Thu, 03 Jul 2014, Stanimir Varbanov wrote:
From: Josh Cartwright jo...@codeaurora.org
The Qualcomm QPNP PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
largely
On 07/09/2014 05:10 PM, Lee Jones wrote:
On Thu, 03 Jul 2014, Stanimir Varbanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
The qpnp-spmi device nodes are childrens of spmi pmic arbiter.
msm8974 SoC using two pmic chips pm8941 and pm8841. Every chip
has two spmi-qpnp bus id's.
Signed
Hi Stephen,
On 07/09/2014 09:07 PM, Stephen Boyd wrote:
On 07/03/14 06:14, Stanimir Varbanov wrote:
A 32bits RTC is housed inside PMIC. The RTC driver uses QPNP
SPMI interface to communicate with the PMIC RTC module.
The RTC device is divided into two sub-peripherals:
- RTC read-write
tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/mfd/Kconfig | 15 ++
drivers/mfd/Makefile|1 +
drivers/mfd/qpnp-spmi.c | 129
+++
3 files changed, 145
On 07/10/2014 04:08 PM, Bjorn Andersson wrote:
On Thu, Jul 3, 2014 at 6:14 AM, Stanimir Varbanov svarba...@mm-sol.com
wrote:
[...]
+static const struct of_device_id qpnp_rtc_table[] = {
+ { .compatible = qcom,qpnp-rtc, },
+ {}
+};
+MODULE_DEVICE_TABLE(of, rtc_qpnp_table
This driver is based on Codeaurora's driver found at [1]
[1]
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/crypto/msm?h=msm-3.10
Stanimir Varbanov (3):
crypto: qce: Qualcomm crypto engine driver
crypto: qce: Build Qualcomm crypto driver
ARM: DT: qcom: Add Qualcomm
Modify crypto Kconfig and Makefile in order to build the qce
driver and adds qce Makefile as well.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/Kconfig | 15 +++
drivers/crypto/Makefile |1 +
drivers/crypto/qce/Makefile |6 ++
3
Here is Qualcomm crypto driver device tree binding documentation
to used as a reference example.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/crypto/qcom-qce.txt| 25
1 files changed, 25 insertions(+), 0 deletions(-)
create
On 07/22/2014 02:03 PM, Lee Jones wrote:
On Thu, 17 Jul 2014, Stanimir Varbanov wrote:
From: Josh Cartwright jo...@codeaurora.org
The Qualcomm SPMI PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
largely as a glue mfd component, it exists
On 07/22/2014 01:32 PM, Lee Jones wrote:
On Thu, 17 Jul 2014, Stanimir Varbanov wrote:
The pm8921-core driver presently supports pm8921 and pm8058
Qualcomm PMICs. To avoid confusion with new generation PMICs
(like pm8941) rename the pm8921-core driver to more
appropriate name pm8xxx-ssbi
Hello to all,
Here is patch set which adds Qualcomm QPNP PMIC's support.
I've removed RFC tag and sending as regular set hoping that
this time more comments will come out. The link to the RFCv2
at [1].
The first patch in the set implements an *of* based parsing of
PMIC peripheral resources and
-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile|1 +
drivers/mfd/qpnp-spmi.c | 145 +++
3 files changed, 161 insertions(+), 0 deletions(-)
create mode 100644 drivers/mfd/qpnp-spmi.c
diff --git
From: Ivan T. Ivanov iiva...@mm-sol.com
The qpnp-spmi device nodes are childrens of spmi pmic arbiter.
msm8974 SoC using two pmic chips pm8941 and pm8841. Every chip
has two spmi-qpnp bus id's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 45
From: Ivan T. Ivanov iiva...@mm-sol.com
Document DT bindings used to describe the Qualcomm QPNP PMICs.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/qpnp/qcom,qpnp-spmi.txt| 53
1
Hi Lee,
On 07/11/2014 12:07 PM, Lee Jones wrote:
On Thu, 10 Jul 2014, Stanimir Varbanov wrote:
The Qualcomm QPNP PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
largely as a glue mfd component, it exists to be an owner
of an SPMI regmap
On 07/14/2014 05:03 PM, Lee Jones wrote:
On Mon, 14 Jul 2014, Stanimir Varbanov wrote:
On 07/11/2014 12:07 PM, Lee Jones wrote:
On Thu, 10 Jul 2014, Stanimir Varbanov wrote:
The Qualcomm QPNP PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
Hi Bjorn,
On 07/10/2014 06:43 PM, Stanimir Varbanov wrote:
On 07/10/2014 04:08 PM, Bjorn Andersson wrote:
On Thu, Jul 3, 2014 at 6:14 AM, Stanimir Varbanov svarba...@mm-sol.com
wrote:
[...]
+static const struct of_device_id qpnp_rtc_table[] = {
+ { .compatible = qcom,qpnp-rtc
Stanimir Varbanov (3):
rtc: add qpnp rtc driver
dt: msm8974: add qpnp rtc device node
dt: rtc: add binding document for qpnp rtc
.../devicetree/bindings/rtc/qcom,rtc-qpnp.txt | 24 +
arch/arm/boot/dts/qcom-msm8974.dtsi| 53 +++
drivers/mfd/Kconfig
-by: Josh Cartwright jo...@codeaurora.org
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/mfd/Kconfig | 15 ++
drivers/mfd/Makefile|1 +
drivers/mfd/qpnp-spmi.c | 129 +++
3 files changed, 145 insertions(+), 0 deletions
From: Ivan T. Ivanov iiva...@mm-sol.com
The qpnp-spmi device nodes are childrens of spmi pmic arbiter.
msm8974 SoC using two pmic chips pm8941 and pm8841. Every chip
has two spmi-qpnp bus id's.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 45
are childrens of QPNP SPMI bus. They
use regmap to read/write to its registers into PMIC.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/rtc/Kconfig|8 +
drivers/rtc/Makefile |1 +
drivers/rtc/rtc-qpnp.c | 489
3 files
Add QPNP RTC device tree node. The RTC device resides into pm8941
and is attached on usid0.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
arch/arm/boot/dts/qcom-msm8974.dtsi |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974
Add devicetree binding document which describes the qpnp-rtc.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/rtc/qcom,rtc-qpnp.txt | 24
1 files changed, 24 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree
Hi Herbert,
Here are sparse fixes for Qualcomm crypto driver reported here [1].
The patches are based on cryptodev-2.6 tree.
regards,
Stan
[1] https://lists.01.org/pipermail/kbuild-all/2014-July/005429.html
Stanimir Varbanov (2):
crypto: qce: fix sparse warnings
crypto: qce: add dependancy
Make qce crypto driver depend on ARCH_QCOM and make
possible to test driver compilation.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/Kconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index
Fix few sparse warnings of type:
- sparse: incorrect type in argument
- sparse: incorrect type in initializer
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
drivers/crypto/qce/common.c | 15 +--
drivers/crypto/qce/common.h |2 +-
drivers/crypto/qce/sha.c| 20
Hi all,
On 07/24/2014 03:45 PM, Stanimir Varbanov wrote:
Hello all,
Changes since v2:
- 1/4 - added new line, signed-off-by / acked-by and module_authors.
- 3/4 - the subject has been changed.
The previous v2 can be found at [1].
I'm still waiting Acks for:
- 4/4 from Qualcomm
Hi,
While looking in MFD drivers I saw that few of them (88pm860x-core,
max8925-core and wm831x-core) allow use of IORESOURCE_REG as resource
type when calling platform_get_resource() by their child drivers. The
resources for these child devices are filled by core MFD driver manually
and then
Arnd, thanks for the comments.
On 07/29/2014 03:00 PM, Arnd Bergmann wrote:
On Tuesday 29 July 2014 14:42:31 Stanimir Varbanov wrote:
taddr = of_translate_address(dev, addrp);
- if (taddr == OF_BAD_ADDR)
- return -EINVAL;
+ /*
+* if the address
Hi,
snip
Signed-off-by: Pramod Gurav pramod.gurav@gmail.com
CC: Josh Cartwright jo...@codeaurora.org
CC: Mark Brown broo...@linaro.org
---
This was found when I enabled support for Qualcomm QPNP PMICs and was
compiling it. It selects REGMAP_SPMI and hence the crash.
snip
config REGMAP_SPMI
+ select SPMI
NO, IMO the CONFIG_SPMI should be enabled by qcom_defconfig and
multi_v7_defconfig. See CONFIG_I2C and REGMAP_I2C for example.
I am using multi_v7_defconfig but its not enabling it. I ran qcom_defconfig
which does.
yes, it seems reasonable to
snip
Thanks.
I misunderstood the Kconfig documentation which says, Reverse dependencies
can only be used with boolean or tristate symbols. In the note following
this statement doc says, In general use select only for non-visible symbols.
The CONFIG_SPMI option is visible in menuconfig
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