On 10/29/2012 12:32 PM, Mike Turquette wrote:
Quoting Stephen Warren (2012-10-23 14:45:56)
What do people think of this? Does it sound like a good idea to go ahead
with a reset subsystem? Should we simply add a new API to the common clock
subsystem instead (and assume that reset and clock
type checked before making allocations.
Reviewed-by: Stephen Warren swar...@nvidia.com
I believe this looks OK. However, I would like Laxman to also ack/review
this since he wrote the driver.
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On 10/30/2012 01:04 AM, Laxman Dewangan wrote:
Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
Reviewed-by: Stephen Warren swar...@nvidia.com
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On 10/30/2012 08:23 AM, Dmitry Osipenko wrote:
This prevents playing sound with wrong speed.
Reviewed-by: Stephen Warren swar...@nvidia.com
I guess this is fine, although as you say it makes little practical
difference in the mainline kernel; I'm sure there is much other work to
be done
On 10/30/2012 01:05 AM, Laxman Dewangan wrote:
This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
enable slink controller defconfig.
This series only instantiates the SPI controller, and not any SPI
devices. I tried
On 10/30/2012 04:07 AM, Pritesh Raithatha wrote:
...
(a commit description wouuld have been nice; I'll add one)
Applied to Tegra's for-3.7/fixes-for-rc4 branch.
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More
On 10/31/2012 03:04 AM, Alex Courbot wrote:
Hi,
Would anyone be opposed to having a gpio_get() function that works similarly
to e.g. regulator_get() and clk_get()?
One major stumbling block is that with device tree, each individual
binding gets to decide on the specific naming of the
On 10/31/2012 02:51 AM, Laxman Dewangan wrote:
On Wednesday 31 October 2012 01:59 AM, Stephen Warren wrote:
On 10/30/2012 01:05 AM, Laxman Dewangan wrote:
This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
enable
On 10/31/2012 03:02 AM, Laxman Dewangan wrote:
This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
enable slink controller defconfig.
I don't appear to have received patch 1/4 this time around. I'll assume
it's
On 10/31/2012 03:02 AM, Laxman Dewangan wrote:
Enable SLINK4 and connected device in Tegra30 based
platform Cardhu.
Setting maximum spi frequency to 25MHz.
Spi serial flash is connected on CS1 of SLINK4 on
cardhu platform.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
On 10/31/2012 11:31 AM, Laxman Dewangan wrote:
On Wednesday 31 October 2012 09:59 PM, Stephen Warren wrote:
On 10/31/2012 03:02 AM, Laxman Dewangan wrote:
This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
enable
From: Stephen Warren swar...@nvidia.com
Modify cmd_dtc to run the C pre-processor on the input .dts file before
passing it to dtc for final compilation. This allows the use of #define
and #include within the .dts file.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v5:
* Update
From: Stephen Warren swar...@nvidia.com
All architectures that use cmd_dtc do so in the same way. Move the build
rule to a central location to avoid duplication.
Update Documentation/kbuild to remove the explicit call to cmd_dtc from
the example, now that the rule exists in a centralized
On 10/31/2012 04:32 AM, Mike Turquette wrote:
Quoting Stephen Warren (2012-10-30 11:02:05)
On 10/29/2012 12:32 PM, Mike Turquette wrote:
Quoting Stephen Warren (2012-10-23 14:45:56)
What do people think of this? Does it sound like a good idea to go ahead
with a reset subsystem? Should we
On 11/01/2012 09:53 AM, Dmitry Osipenko wrote:
Added suspend/resume pm ops. We need to store current regs vals on suspend and
restore them on resume.
Interesting. Just literally a couple days ago, I was reviewing a patch
to our internal kernel tree that implemented the same thing for the
On 11/01/2012 08:16 AM, Axel Lin wrote:
The of_device_id table is supposed to be zero-terminated.
Thanks. How embarrassing! I forwarded this to arm-soc for inclusion into
3.7.
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On 11/02/2012 04:23 AM, Ralf Baechle wrote:
On Fri, Nov 02, 2012 at 10:58:01AM +0100, Ralf Baechle wrote:
Can you fold these MIPS bits into your patch?
I missed Lantiq.
Thanks, I've squashed that in, and with a quick grep noticed that
arch/{arm64,microblaze} also need updating.
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On 11/02/2012 10:21 AM, Murali Karicheri wrote:
This is a platform driver for asynchronous external memory interface
available on TI SoCs. This driver was previously located inside the
mach-davinci folder. As this DaVinci IP is re-used across multiple
family of devices such as c6x, keystone
On 09/22/2012 09:56 AM, Mark Brown wrote:
On Thu, Sep 20, 2012 at 04:04:57PM -0600, Stephen Warren wrote:
Mark, if this gets into 3.7, I can fix up all the Tegra .dts files during
3.8.
I don't know which branch you generated this against but it doesn't
apply to any of the obvious
On 09/24/2012 10:07 AM, Stephen Rothwell wrote:
Hi Randy,
On Mon, 24 Sep 2012 08:39:05 -0700 Randy Dunlap
rdun...@xenotime.net wrote:
On 09/24/2012 07:53 AM, Stephen Rothwell wrote:
Today was a train wreck, with lots of new conflicts across
several trees and a few build failures as
Commit 89214f0 ARM: bcm2835: add interrupt controller driver added an
empty drivers/irqchip/Kconfig. Empty files apparently don't work well
with git (sometimes, with some versions?) so add some dummy content to
resolve this issue.
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
drivers
On 09/24/2012 12:18 AM, Venu Byravarasu wrote:
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Friday, September 21, 2012 9:21 PM
To: Venu Byravarasu
Cc: a...@linux-foundation.org; a.zu...@towertech.it; linux-
ker...@vger.kernel.org; rtc-li
On 09/21/2012 01:05 PM, Arend van Spriel wrote:
On 09/21/2012 06:19 PM, Stephen Warren wrote:
On 09/21/2012 08:39 AM, Arend van Spriel wrote:
On 09/21/2012 10:55 AM, Wei Ni wrote:
New options enabled:
* CFG80211_WEXT: (dependency)
* BRCMFMAC: wlan driver, enable as module.
Signed-off
From: Stephen Warren swar...@nvidia.com
Commit regulator: deprecate regulator-compatible DT property deprecated
the use of the regulator-compatible DT property. Update the DT example in
the TPS6586x binding documentation to reflect this.
Signed-off-by: Stephen Warren swar...@nvidia.com
From: Stephen Warren swar...@nvidia.com
As explained in patch 1, this series deprecates the regulator-compatible
DT property, and updates various binding documentation and examples for
this change.
I expect patches 1-3 to go into various regulator topic trees, and patch
4 to go into the MFD tree
From: Stephen Warren swar...@nvidia.com
Commit regulator: deprecate regulator-compatible DT property deprecated
the use of the regulator-compatible DT property. Update the DT example in
the TPS65217 binding documentation to reflect this.
Signed-off-by: Stephen Warren swar...@nvidia.com
From: Stephen Warren swar...@nvidia.com
Commit regulator: deprecate regulator-compatible DT property deprecated
the use of the regulator-compatible DT property. Update the DT example in
the MAX8907 binding documentation to reflect this.
Signed-off-by: Stephen Warren swar...@nvidia.com
From: Stephen Warren swar...@nvidia.com
When the bindings for the TPS6586x regulator were being proposed, I
asserted that DT node naming rules for bus child nodes should also be
applied to nodes inside the TPS6586x regulator node itself. In other
words, that each node providing regulator init
On 09/24/2012 10:29 PM, Philip, Avinash wrote:
On Fri, Sep 21, 2012 at 23:13:39, Stephen Warren wrote:
On 09/21/2012 12:03 AM, Philip, Avinash wrote:
Hi Stephen,
On Fri, Sep 21, 2012 at 10:46:45, Stephen Warren wrote:
On 09/20/2012 10:51 PM, Philip, Avinash wrote:
Some backlights perform
On 09/24/2012 11:29 PM, Venu Byravarasu wrote:
As RTC driver needs only irq number from platform data,
using platform_get_irq(), instead of generic dev_get_platdata().
This seems fine to me now.
However, it'd be useful to post all the patches related to this issue at
one time, so we can get a
On 09/14/2012 04:23 PM, Markus Mayer wrote:
Prior to this change, an empty input file would cause a segfault, because
yylloc had never been initialized. There was never any characters for the
lexer to match, so YY_USER_ACTION was never executed before the parse error
was detected.
When the
On 09/25/2012 10:35 PM, Philip, Avinash wrote:
On Tue, Sep 25, 2012 at 11:49:14, Stephen Warren wrote:
On 09/24/2012 10:29 PM, Philip, Avinash wrote:
On Fri, Sep 21, 2012 at 23:13:39, Stephen Warren wrote:
On 09/21/2012 12:03 AM, Philip, Avinash wrote:
Hi Stephen,
On Fri, Sep 21, 2012 at 10
On 09/26/2012 07:01 AM, Linus Walleij wrote:
From: Linus Walleij linus.wall...@linaro.org
This pure documentation fix tries to align the idle and
sleep pin states to the idle and suspend states from
runtime PM.
Seems reasonable,
Acked-by: Stephen Warren swar...@nvidia.com
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On 09/26/2012 11:18 AM, Linus Walleij wrote:
From: Linus Walleij linus.wall...@linaro.org
This allocates the IRQ descriptors for the Nomadik pin controller
dynamically so that we don't have to rely on some other mechanism
doing it, and moving a step closer to a linear IRQ domain.
Cc: Rob
On 10/03/2012 02:24 AM, Alex Courbot wrote:
On 09/14/2012 12:24 AM, Stephen Warren wrote:
On 09/13/2012 01:29 AM, Mark Brown wrote:
On Thu, Sep 13, 2012 at 04:26:34PM +0900, Alex Courbot wrote:
On Thursday 13 September 2012 15:19:30 Mark Brown wrote:
On Thursday 13 September 2012 14:25:53
.
Allocate the pointer as part of dma channel and pass
this pointer as the devname for irq registration to
avoid change of name.
(Dropping stable Cc; Olof/Arnd or Vinod, is it possible you could add
that into the patch description when applying this?)
Reported-by: Stephen Warren swar...@nvidia.com
Acked
On 11/04/2012 11:04 AM, Linus Walleij wrote:
On Wed, Oct 31, 2012 at 10:04 AM, Alex Courbot acour...@nvidia.com wrote:
Would anyone be opposed to having a gpio_get() function that works similarly
to e.g. regulator_get() and clk_get()?
I understand the concept and why you want to do this.
On 11/05/2012 07:55 PM, Omar Ramirez Luna wrote:
Actually moving it from plat-omap, as this framework/driver code is
supposed to be under drivers/ folder. The framework should work with
the current supported OMAP processors (OMAP1+) that have mailbox and
can be used as a method of
*of_pinctrl_add_gpio_range(struct
device_node *np,
if (!pctldev)
return NULL;
- pinctrl_add_gpio_range(pctldev, range);
return pctldev;
}
I think that collapses to just:
return pctldev;
Aside from that, the series,
Reviewed-by: Stephen Warren swar
On 11/06/2012 09:21 AM, Linus Walleij wrote:
From: Linus Walleij linus.wall...@linaro.org
The */gpio.h includes are updated again: now we need to account
for the problem introduced by commit:
595679a8038584df7b9398bf34f61db3c038bfea
gpiolib: fix up function prototypes etc
Actually we
On 11/06/2012 12:41 PM, Pantelis Antoniou wrote:
Hi Russ,
On Nov 6, 2012, at 8:29 PM, Russ Dill wrote:
On Tue, Nov 6, 2012 at 10:35 AM, Tony Lindgren t...@atomide.com wrote:
* Grant Likely grant.lik...@secretlab.ca [121106 03:16]:
On Tue, Nov 6, 2012 at 10:30 AM, Pantelis Antoniou
On 11/05/2012 01:40 PM, Grant Likely wrote:
Hey folks,
As promised, here is my early draft to try and capture what device
tree overlays need to do and how to get there. Comments and
suggestions greatly appreciated.
Interesting. This just came up internally at NVIDIA within the last
couple
On 11/07/2012 08:01 AM, Laxman Dewangan wrote:
The gpio interrupts get mapped linearly and hence the mapping
of irq need to be created by irq_create_mapping().
The function gpio_to_irq() returns the irq by irq_find_mapping()
and so returns 0 as there is no mapping created. Fix the function
CONFIG_PM_SLEEP and CONFIG_PM_RUNTIME.
This means if CONFIG_PM is used to protect system sleep callbacks
then it may end up unreferenced if only runtime PM is enabled.
- Fix the suspend/resume APIs declaration as per callback prototype.
Seems plausible, so this patch,
Acked-by: Stephen Warren
On 11/07/2012 01:47 AM, Pantelis Antoniou wrote:
Hi Stephen,
On Nov 6, 2012, at 11:37 PM, Stephen Warren wrote:
On 11/05/2012 01:40 PM, Grant Likely wrote:
Hey folks,
As promised, here is my early draft to try and capture what device
tree overlays need to do and how to get
On 11/07/2012 03:19 AM, Benoit Cousson wrote:
Hi Panto,
On 11/07/2012 09:13 AM, Pantelis Antoniou wrote:
Hi Grant
On Nov 6, 2012, at 9:45 PM, Grant Likely wrote:
On Tue, Nov 6, 2012 at 7:34 PM, Pantelis Antoniou
pa...@antoniou-consulting.com wrote:
[ snip ]
g.
Since we've started
On 11/06/2012 02:47 PM, Murali Karicheri wrote:
This is a platform driver for asynchronous external memory interface
available on TI SoCs. This driver was previously located inside the
mach-davinci folder. As this DaVinci IP is re-used across multiple
family of devices such as c6x, keystone
On 11/06/2012 02:47 PM, Murali Karicheri wrote:
DaVinci NAND driver is a controller driver based on the AEMIF hardware
IP found on TI SoCs. It is also used on SoCs that are not DaVinci based. This
patch removes the driver dependency on DaVinci architecture so that it
can be used on other
On 11/07/2012 01:55 PM, Marek Belisko wrote:
diff --git a/Documentation/devicetree/bindings/leds/tca6507.txt
b/Documentation/devicetree/bindings/leds/tca6507.txt
+LEDs conected to tca6507
+
+Required properties:
+- compatible : should be : leds-tca6507.
ti,tca6507 would be more typical.
On 11/07/2012 07:45 PM, Axel Lin wrote:
Both tegra_gpio_request() and tegra_gpio_free() are not referenced outside of
this file, make them static.
Both patches,
Acked-by: Stephen Warren swar...@nvidia.com
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On 11/07/2012 11:27 PM, Laxman Dewangan wrote:
Read the output value when gpio is set for the output mode for
gpio_get_value(). Reading input value in direction out does not
give correct value.
That's an unfortunate HW design, but oh well. Do you have any idea why
reading the input register
On 11/08/2012 04:55 AM, Linus Walleij wrote:
From: Jonas Aaberg jonas.ab...@stericsson.com
Currently there are some unnecessary criss-cross
dependencies between the PRCMU driver in MFD and a lot of
other drivers, mainly because other drivers need to poke
around in the PRCM register range.
On 11/08/2012 08:57 AM, Murali Karicheri wrote:
On 11/07/2012 03:08 PM, Stephen Warren wrote:
On 11/06/2012 02:47 PM, Murali Karicheri wrote:
DaVinci NAND driver is a controller driver based on the AEMIF hardware
IP found on TI SoCs. It is also used on SoCs that are not DaVinci
based
From: Stephen Warren swar...@nvidia.com
Currently, whenever CONFIG_ARCH_USES_GETTIMEOFFSET is enabled, each
arch core provides a single implementation of arch_gettimeoffset(). In
many cases, different sub-architectures, different machines, or
different timer providers exist, and so the arch ends
From: Stephen Warren swar...@nvidia.com
remove m68k's mach_gettimeoffset function pointer, and instead directly
set the arch_gettimeoffset function pointer. This requires multiplying
all function results by 1000, since the removed m68k_gettimeoffset() did
this. Also, s/unsigned long/u32/ just
From: Stephen Warren swar...@nvidia.com
Move PXA's timer suspend/resume functions from struct sys_timer
pxa_timer into struct clock_event_device ckevt_pxa_osmr0. This
will allow the sys_timer suspend/resume fields to be removed, and
eventually lead to a complete removal of struct sys_timer.
Cc
From: Stephen Warren swar...@nvidia.com
Move ux500's timer suspend/resume functions from struct sys_timer
ux500_timer into struct clock_event_device nmdk_clkevt. This
will allow the sys_timer suspend/resume fields to be removed, and
eventually lead to a complete removal of struct sys_timer.
Cc
From: Stephen Warren swar...@nvidia.com
Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.
This will enable moving timer drivers into drivers/clocksource without
having to place
From: Stephen Warren swar...@nvidia.com
These fields duplicate e.g. struct clock_event_device's suspend and
resume fields, so remove them now that nothing is using them. The aim
is to remove all fields from struct sys_timer except .init, then replace
the ARM machine descriptor's .timer field
From: Stephen Warren swar...@nvidia.com
Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.
This will enable moving timer drivers into drivers/clocksource without
having to place
From: Stephen Warren swar...@nvidia.com
The overall aim of this series is to allow ARM (or indeed any) timer
drivers to be moved into drivers/clocksource without requiring a
struct or function prototype for each individual driver in include/linux.
The intent is eventually to create a single e.g
From: Stephen Warren swar...@nvidia.com
Instead of using struct sys_timer's resume function, register syscore_ops
directly in s3c2410_timer_init(). This will allow the sys_timer suspend/
resume fields to be removed, and eventually lead to a complete removal of
struct sys_timer.
Cc: Ben Dooks ben
From: Stephen Warren swar...@nvidia.com
Move sa1100's timer suspend/resume functions from struct sys_timer
sa1100_timer into struct clock_event_device ckevt_sa1100_osmr0. This
will allow the sys_timer suspend/resume fields to be removed, and
eventually lead to a complete removal of struct
From: Stephen Warren swar...@nvidia.com
Move at91's timer suspend/resume functions from struct sys_timer
at91sam926x_timer into struct clock_event_device pit_clkevt. This
will allow the sys_timer suspend/resume fields to be removed, and
eventually lead to a complete removal of struct sys_timer
On 11/08/2012 02:01 PM, Stephen Warren wrote:
Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.
Oops. This one patch is a duplicate of 11/11 in the series I just sent.
Sorry
From: Stephen Warren swar...@nvidia.com
remove ARM's struct sys_timer .offset function pointer, and instead
directly set the arch_gettimeoffset function pointer when the timer
driver is initialized. This requires multiplying all function results
by 1000, since the removed arm_gettimeoffset() did
From: Stephen Warren swar...@nvidia.com
Move usec to nsec conversion from arch_gettimeoffset() to
do_slow_gettimeoffset(); in a future patch, do_slow_gettimeoffset()
will be used directly as the implementation of arch_gettimeoffset(),
so needs to perform all required calculations.
Cc: Mikael
On 10/18/2012 11:58 PM, Mark Zhang wrote:
Define pinmux for DDC. The DDC pinmux in Ventana is 2 pins in I2C2.
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
- ddc {
- nvidia,pins = ddc, owc, spdi, spdo,
- uac;
On 10/19/2012 03:10 AM, Laxman Dewangan wrote:
On Friday 19 October 2012 04:11 AM, Stephen Warren wrote:
On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
Add slink controller details in the dts file of
Tegra20 and Tegra30.
diff --git a/arch/arm/boot/dts/tegra20.dtsi
b/arch/arm/boot/dts/tegra20
On 10/19/2012 03:13 AM, Laxman Dewangan wrote:
On Friday 19 October 2012 04:13 AM, Stephen Warren wrote:
+OF_DEV_AUXDATA(nvidia,tegra20-slink, TEGRA_SLINK1_BASE,
spi-tegra-slink.0, NULL),
Here, can't we just use the existing device names in the clock files...
So we can completely drop
On 10/19/2012 03:20 AM, Tony Prisk wrote:
On Fri, 2012-10-19 at 18:06 +0900, Alexandre Courbot wrote:
Make use of the power sequences specified in the device tree or platform
data to control how the backlight is powered on and off.
Tony, please do cut down the amount of the patch that you
.
For this to work: use irq_create_mapping() in the IRQ iterator
so that the descriptors get allocated here.
Tested-by: Stephen Warren swar...@nvidia.com
Acked-by: Stephen Warren swar...@nvidia.com
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though it currently doesn't have to do anything, it
provides documentation for where any required cleanup would be placed if
needed in the future.
If you still want to remove the function, pinconf_free_setting() should
also be removed, since that's empty right now.
Irrespective,
Acked-by: Stephen
On 10/19/2012 09:09 AM, Linus Walleij wrote:
From: Linus Walleij linus.wall...@linaro.org
Since in the DT case, the linear domain path will not allocate
descriptors for the IRQs, we need to use irq_create_mapping()
for mapping hwirqs to Linux IRQs, so these descriptors get
created
On 10/19/2012 09:35 AM, Felipe Balbi wrote:
Hi,
On Fri, Oct 19, 2012 at 04:08:05PM +0530, Venu Byravarasu wrote:
NVIDIA produces several Tegra SoCs viz Tegra20, Tegra30 etc. In
order to support USB PHY drivers on these SoCs, existing PHY
driver is split into SoC agnostic common USB PHY
On 10/22/2012 07:02 AM, Mark Brown wrote:
Rather than requiring platforms to select the generic clock API to make
it available make the API available as a user selectable option unless the
user either selects HAVE_CUSTOM_CLK (if they have their own implementation)
or selects COMMON_CLK (if
On 10/22/2012 01:29 AM, Mark Zhang wrote:
On 10/19/2012 11:48 PM, Stephen Warren wrote:
On 10/18/2012 11:58 PM, Mark Zhang wrote:
Define pinmux for DDC. The DDC pinmux in Ventana is 2 pins in I2C2.
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
-ddc {
-nvidia,pins
On 10/18/2012 04:47 AM, Laxman Dewangan wrote:
Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
+static inline void tegra_slink_writel(struct
On 10/22/2012 02:14 AM, Linus Walleij wrote:
On Fri, Oct 19, 2012 at 6:22 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 10/19/2012 09:09 AM, Linus Walleij wrote:
From: Linus Walleij linus.wall...@linaro.org
@@ -931,7 +931,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq,
struct
On 10/22/2012 02:15 AM, Linus Walleij wrote:
This switches the way that pins are reserved for multiplexing:
We used to do this when the map was parsed, at the creation of
the settings inside the pinctrl handle, in pinmux_map_to_setting().
However this does not work for us, because we want
On 10/22/2012 02:21 AM, Linus Walleij wrote:
On Fri, Oct 19, 2012 at 8:10 PM, Tony Lindgren t...@atomide.com wrote:
[Me]
Instead: let use reserve the pins when the state is activated
and drop them when the state is disabled, i.e. when we move to
another state. This way different
on-the-fly in this case.
ChangeLog v1-v2:
- Just use irq_create_mapping() in the .to_irq function since
this is called before unmasking or enabling any interrupt
lines, so irq_find_mapping() should be sufficient for the
IRQ handler function.
Reviewed-by: Stephen Warren swar...@nvidia.com
On 10/23/2012 01:18 AM, Pavan Kunapuli wrote:
Adding vmmc and vmmcq supplies for sdhci nodes
in tegra dt files.
As I already mentioned downstream, this patch is invalid because it will
cause runtime failures if applied before the second patch in this
series. Please see the more detailed
On 10/23/2012 01:18 AM, Pavan Kunapuli wrote:
vmmc and vqmmc regulators control the voltage to
the host and device. Defer the probe if either of
them is not registered.
Signed-off-by: Pavan Kunapuli pkunap...@nvidia.com
---
drivers/mmc/host/sdhci.c | 25 ++---
1
On 10/23/2012 01:57 AM, Lucas Stach wrote:
Am Dienstag, den 23.10.2012, 12:49 +0530 schrieb Pavan Kunapuli:
vmmc and vqmmc regulators control the voltage to
the host and device. Defer the probe if either of
them is not registered.
Does this work with boards where we don't have any MMC
On 10/23/2012 12:07 PM, Marc Dietrich wrote:
Pavan,
On Tuesday 23 October 2012 12:48:59 Pavan Kunapuli wrote:
Adding vmmc and vmmcq supplies for sdhci nodes
in tegra dt files.
...
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
b/arch/arm/boot/dts/tegra20-paz00.dts index
From: Stephen Warren swar...@nvidia.com
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
Such a binding would allow the creation of a reset subsystem, which
could replace APIs such as the following Tegra-specific API:
void
.
Acked-by: Stephen Warren swar...@nvidia.com
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
@@ -633,6 +633,8 @@ config ARCH_TEGRA
select GENERIC_GPIO
select HAVE_CLK
select HAVE_SMP
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if LOCAL_TIMERS
select
On 10/07/2012 07:28 AM, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Remove duplicated include.
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Linus, I assume this will go through the pinctrl tree?
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To unsubscribe from this
On 10/07/2012 08:01 AM, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
In case of error, the function pinctrl_register() returns
NULL not ERR_PTR(). The PTR_ERR() in the return value
should be replaced with error no.
dpatch engine is used to auto generate this patch.
to auto generate this patch.
(https://github.com/weiyj/dpatch)
Acked-by: Stephen Warren swar...@wwwdotorg.org
Mike, this driver was added through arm-soc; I assume it's simplest to
take this fixup through there too for 3.7-rc*? If so, Wei, could you
resend this patch with my ack to a...@kernel.org
On 10/09/2012 04:33 AM, Venu Byravarasu wrote:
Laxman Dewangan wrote at Tuesday, October 09, 2012 3:19 PM:
The TPS65090's DCDC output can also be enable/disable through the
external digital input signal. Add support for enable/disable
either through register access via I2C or through external
On 10/01/2012 12:39 PM, Jon Loeliger wrote:
What more do you think needs discussion re: dtc+cpp?
How not to abuse the ever-loving shit out of it? :-)
Perhaps we can just handle this through the regular patch review
process; I think it may be difficult to define and agree upon exactly
what
On 10/09/2012 06:04 PM, Scott Wood wrote:
On 10/09/2012 06:20:53 PM, Mitch Bradley wrote:
On 10/9/2012 11:16 AM, Stephen Warren wrote:
On 10/01/2012 12:39 PM, Jon Loeliger wrote:
What more do you think needs discussion re: dtc+cpp?
How not to abuse the ever-loving shit out
On 10/10/2012 01:24 AM, David Gibson wrote:
On Tue, Oct 09, 2012 at 10:43:50PM -0600, Warner Losh wrote:
On Oct 9, 2012, at 6:04 PM, Scott Wood wrote:
On 10/09/2012 06:20:53 PM, Mitch Bradley wrote:
On 10/9/2012 11:16 AM, Stephen Warren wrote:
On 10/01/2012 12:39 PM, Jon Loeliger wrote
On 10/10/2012 09:33 AM, Rob Herring wrote:
On 10/10/2012 10:16 AM, Stephen Warren wrote:
On 10/10/2012 01:24 AM, David Gibson wrote:
On Tue, Oct 09, 2012 at 10:43:50PM -0600, Warner Losh wrote:
On Oct 9, 2012, at 6:04 PM, Scott Wood wrote:
On 10/09/2012 06:20:53 PM, Mitch Bradley wrote
On 10/10/2012 10:09 AM, Scott Wood wrote:
On 10/10/2012 10:15:17 AM, Stephen Warren wrote:
On 10/09/2012 06:04 PM, Scott Wood wrote:
On 10/09/2012 06:20:53 PM, Mitch Bradley wrote:
On 10/9/2012 11:16 AM, Stephen Warren wrote:
On 10/01/2012 12:39 PM, Jon Loeliger wrote:
What more do
On 10/10/2012 11:09 AM, Rob Herring wrote:
On 10/09/2012 04:16 PM, Stephen Warren wrote:
On 10/01/2012 12:39 PM, Jon Loeliger wrote:
What more do you think needs discussion re: dtc+cpp?
How not to abuse the ever-loving shit out of it? :-)
Perhaps we can just handle this through the regular
On 10/10/2012 11:18 AM, Rob Herring wrote:
On 10/10/2012 11:19 AM, Stephen Warren wrote:
On 10/10/2012 09:33 AM, Rob Herring wrote:
On 10/10/2012 10:16 AM, Stephen Warren wrote:
On 10/10/2012 01:24 AM, David Gibson wrote:
On Tue, Oct 09, 2012 at 10:43:50PM -0600, Warner Losh wrote:
On Oct 9
On 10/10/2012 12:23 PM, Mitch Bradley wrote:
On 10/10/2012 7:09 AM, Rob Herring wrote:
On 10/09/2012 04:16 PM, Stephen Warren wrote:
On 10/01/2012 12:39 PM, Jon Loeliger wrote:
What more do you think needs discussion re: dtc+cpp?
How not to abuse the ever-loving shit out
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