...@arm.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/base/cacheinfo.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 6e64563361f0..7015bf05c828 100644
--- a/drivers/base/cacheinfo.c
Hi Venkappa,
First of all, please make sure the relevant mailing list(ALKML in this case)
and maintainers (MarcZ and Catalin as you are addressing him) are cc-ed,
else there's every chance that the mail gets lost.
On Thu, Feb 19, 2015 at 1:03 PM, Venkappa Mala venkapp...@samsung.com wrote:
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Tony Luck
the AMD L3 cache specific attributes.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 709
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Benjamin
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Martin
On Thursday 08 January 2015 01:44 PM, Heiko Carstens wrote:
On Thu, Jan 08, 2015 at 07:41:52AM +, Sudeep Holla wrote:
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base
...@arm.com
Acked-by: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/base/cacheinfo.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
Hi Greg,
Can you please pick this up as a bug fix ?
Without this there's possibility
On 16/03/15 19:17, Fabian Frederick wrote:
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Not sure if you really need acks for simple change like this, anyways
for vexpress parts in patch 06, 26 and 32
Acked-by: Sudeep Holla sudeep.ho
Hi Huang,
On 19/03/15 02:28, Huang Ying wrote:
FYI, we noticed the below changes on
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
commit 0d55ba46bfbee64fd2b492b87bfe2ec172e7b056 (x86/cacheinfo: Move cacheinfo
sysfs code to generic infrastructure)
[...]
[
Cc: Felipe Balbi ba...@ti.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/usb/isp1760/isp1760-udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Laurent, Felipe,
I am extremely sorry for missing this in my original patch.
Thanks to Dan Carpenter for reporting
Hi Laurent,
On 20/03/15 14:20, Laurent Pinchart wrote:
Hi Sudeep,
Thank you for the patch.
On Friday 20 March 2015 11:42:17 Sudeep Holla wrote:
Commit a124820de5fd (usb: isp1760: fix possible deadlock in
isp1760_udc_irq) replaced spin_{un,}lock with
spin_{un,}lock_irq{save,restore}. However
On 19/03/15 17:32, Mark Rutland wrote:
One more thing:
@@ -883,7 +894,11 @@ static inline const struct cci_pmu_model
*get_cci_model(struct platform_device *
pdev-dev.of_node);
if (!match)
return NULL;
+ if
Hi Steven,
On 20/03/15 17:32, Steven Rostedt wrote:
I decided to run my tracing tests on linux-next and they failed with
the following warning:
[drm] Initialized i915 1.6.0 20150130 for :00:02.0 on minor 0
[ cut here ]
WARNING: CPU: 0 PID: 1 at
Hi Filipe,
On 09/03/15 15:49, Felipe Balbi wrote:
On Wed, Mar 04, 2015 at 03:56:12PM +, Sudeep Holla wrote:
On 26/02/15 18:53, Laurent Pinchart wrote:
Hi Sudeep,
Thank you for the patch.
On Thursday 26 February 2015 11:47:57 Sudeep Holla wrote:
As per the SAF1761 data sheet[0
Hi Boris,
On 11/03/15 13:36, Borislav Petkov wrote:
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
My initial assumption was that it will be NULL for Intel processors
and hence I assigned cacheinfo-priv to nb pointer unconditionally. So
I don't have any strong opinion here
Hi Greg,
On 23/02/15 16:32, Sudeep Holla wrote:
On architectures that depend on DT for obtaining cache hierarcy, we need
to validate the device node for all the cache indices, failing to do so
might result in wrong information being exposed to the userspace.
This is quite possible on initial
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
No, not seen this before. I will test tip/master on my Intel i7 box
again and get back to you.
Regards,
Sudeep
--
To
On Tue, Mar 10, 2015 at 11:53:35AM +, Sudeep Holla wrote:
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
No, not seen this before. I will test tip/master on my Intel
On 10/03/15 14:26, Borislav Petkov wrote:
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote:
I was able to reproduce this and now I realise I had CONFIG_AMD_NB
disabled in my config earlier which hid this issue previously, sorry
for that.
The below patch fixed the issue on my
-secure)TC2 and A53x2.
For the series,
Tested-by: Sudeep Holla sudeep.ho...@arm.com
(Tested on secure TC2 using MCPM)
Regards,
Sudeep
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versions(e.g, CCI-500).
Changes since V2:
- Make ARM_CCI400_PMU default y (Suggested-by: Sudeep Holla)
Changes since V1 (Suggestions-by: Nicolas Pitre):
- Renames
CONFIG_ARM_CCI400_MCPM = CONFIG_ARM_CCI400_PORT_CTRL
CCI400_MCPM_PORTS_DATA = CCI400_PORTS_DATA
- Select
On 01/04/15 05:40, Michael Ellerman wrote:
On Tue, 2015-03-31 at 18:14 +0100, Sudeep Holla wrote:
On 31/03/15 11:56, Michael Ellerman wrote:
On Mon, 2015-23-02 at 18:18:20 UTC, Sudeep Holla wrote:
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic
On 31/03/15 11:56, Michael Ellerman wrote:
On Mon, 2015-23-02 at 18:18:20 UTC, Sudeep Holla wrote:
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache
On 02/03/15 11:29, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
No functional changes, only code re-arrangements for easier split of the
PMU code vs low level driver code. Extracts the port handling code
to cci_probe_ports().
Signed-off-by: Suzuki K. Poulose
On 02/03/15 11:29, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Avoid secure transactions while probing the CCI PMU. The
existing code makes use of the Peripheral ID2 (PID2) register
to determine the revision of the CCI400, which requires a
secure transaction. This
On 03/03/15 15:30, Viresh Kumar wrote:
On 3 March 2015 at 20:56, Sudeep Holla sudeep.ho...@arm.com wrote:
You can use any_online_cpu(..) instead of cpumask_any IMO
What about policy-cpu ? :)
We can, was not sure if they have access to policy in their thermal
driver. Just the first
On 02/03/15 11:29, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch separates the PMU driver code from the low level
CCI driver code.
Introduces config options for both.
ARM_CCI400_PORT_CTRL - controls the low level driver code for
On Tue, Mar 3, 2015 at 3:09 PM, Kapileshwar Singh
kapileshwar.si...@arm.com wrote:
On 03/03/15 13:07, Viresh Kumar wrote:
[...]
Please goto the depth of this thing, as I don't think it should happen.
Over that I was asking you if you have tested the solution Javi gave,
because OPPs
-secure)TC2 and Juno.
For the series:
Tested-by: Sudeep Holla sudeep.ho...@arm.com (on secure/MCPM TC2)
Regards,
Sudeep
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Hi Andre,
On 01/03/15 22:39, Andre Przywara wrote:
On Tue, 24 Feb 2015 18:57:49 +0100, Borislav Petkov wrote:
On Mon, Feb 23, 2015 at 06:14:25PM +, Sudeep Holla wrote:
- Rebased on v4.0-rc1
- Fixed lockdep warning reported by Borislav
You probably have fixed the lockdep splat
On 26/02/15 18:53, Laurent Pinchart wrote:
Hi Sudeep,
Thank you for the patch.
On Thursday 26 February 2015 11:47:57 Sudeep Holla wrote:
As per the SAF1761 data sheet[0], the DcChipID register represents
the hardware version number (0001h) and the chip ID (1582h) for the
Peripheral
: (f-f_pos_lock){+.+.+.}, at: [c010a101] __fdget_pos+0x31/0x34
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Laurent Pinchart laurent.pinch...@ideasonboard.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: Felipe Balbi ba...@ti.com
---
drivers/usb/isp1760/isp1760-udc.c | 10
On 04/03/15 16:11, Laurent Pinchart wrote:
Hi Sudeep,
On Wednesday 04 March 2015 15:56:12 Sudeep Holla wrote:
[...]
Also I don't see any message on the host side. Let me know if there's
something wrong in my config or test commands.
Looks like a driver bug to me, .udc_start
On 03/03/15 18:45, Borislav Petkov wrote:
[...]
Now, previously the code did
- if (!per_cpu(ici_cpuid4_info, i))
- continue;
and __cache_cpumap_setup() already does:
if (i == cpu || !sib_cpu_ci-info_list)
On 04/03/15 11:27, Borislav Petkov wrote:
On Wed, Mar 04, 2015 at 11:15:49AM +, Sudeep Holla wrote:
I can do that, but wouldn't that add confusion as this commit is not
changing that behaviour. It's already changed in v4.0-rc1
Nah, this would add a reference to the fact that the cpumask
similar to any
other device.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: Borislav Petkov b...@suse.de
Cc: Andre Przywara andre.przyw...@arm.com
Cc: x...@kernel.org
---
arch/x86/kernel
Hi Boris,
On 03/03/15 18:57, Borislav Petkov wrote:
On Tue, Mar 03, 2015 at 01:53:02PM -0500, Tejun Heo wrote:
We were alternating between the two forms depending on
CONFIG_CPUMASK_OFFSTACK before. Now we're always sticking to the
shorter format. Please see 513e3d2d11c9 (cpumask: always use
Hi Boris,
On 05/03/15 08:16, Borislav Petkov wrote:
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git
On 05/03/15 10:49, Laurent Pinchart wrote:
Hi Sudeep,
Thank you for the patch.
On Wednesday 04 March 2015 17:07:57 Sudeep Holla wrote:
Use spin_{un,}lock_irq{save,restore} in isp1760_udc_{start,stop} to
prevent following potentially deadlock scenario between
isp1760_udc_{start,stop
On 23/02/15 15:14, Mark Rutland wrote:
On Mon, Feb 16, 2015 at 02:10:16PM +, Sudeep Holla wrote:
On architectures that depend on DT for obtaining cache hierarcy, we need
to validate the device node for all the cache indices, failing to do so
might result in wrong information being exposed
...@arm.com
Acked-by: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/base/cacheinfo.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
v1-v2:
- Updated log information as suggested by Mark
- Added Mark's ACK
Hi Greg,
Can you
Hi Boris,
On 23/01/15 18:15, Borislav Petkov wrote:
On Fri, Jan 23, 2015 at 02:55:03PM +0100, Thomas Gleixner wrote:
Cc: Boris
On Thu, 8 Jan 2015, Sudeep Holla wrote:
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Tony Luck
the AMD L3 cache specific attributes.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: Borislav Petkov b...@suse.de
Cc: x...@kernel.org
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 711
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Benjamin
On 24/02/15 07:58, Ingo Molnar wrote:
* Sudeep Holla sudeep.ho...@arm.com wrote:
This patch removes the redundant sysfs cacheinfo code by
reusing the newly introduced generic cacheinfo
infrastructure through the commit 246246cbde5e (drivers:
base: support cpu cache information interface
...@ideasonboard.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/usb/isp1760/isp1760-udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Laurent,
I found that the chip ID is wrong when I tried testing OTG on vexpress
platforms. As per Section 10.8.2 DcChipID register in [1
Hi Boris,
On 24/02/15 17:57, Borislav Petkov wrote:
On Mon, Feb 23, 2015 at 06:14:25PM +, Sudeep Holla wrote:
- Rebased on v4.0-rc1
- Fixed lockdep warning reported by Borislav
You probably have fixed the lockdep splat but not the NULL pointer
dereference which was there in the first
Hi Laurent,
On 25/02/15 22:27, Laurent Pinchart wrote:
Hi Sudeep,
Thank you for the patch.
On Tuesday 24 February 2015 17:53:42 Sudeep Holla wrote:
As per the ISP1761 data sheet, the DcChipID register represents
the hardware version number (0015h) and the chip ID (8210h) for the
Peripheral
-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/usb/isp1760/isp1760-udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Changes v1-v2:
- Updated to support both chip IDs: 0x00011582 and 0x00158210 instead of
just 0x00158210 as suggested by Laurent
diff --git a/drivers/usb/isp1760
Hi Thomas/Rafael,
With latest mainline(commit 27cf3a16b2535a490f8cf1d29a6634f1c70f7831),
and lockdep enabled I see the following inconsistent lock state log.
I am not sure if it's related to recent changes in tick-broadcast or I
might be missing any config ?
=
[
On Thu, Apr 23, 2015 at 6:07 PM, Josh Boyer jwbo...@fedoraproject.org wrote:
Hi All,
We've had a user report the following backtrace from the bridge module
with a recent Linus' tree. Has anything like this been reported yet?
If you have any questions on setup, the user is CC'd.
I too
Hi Rafael,
On 28/04/15 13:19, Rafael J. Wysocki wrote:
On Tue, Apr 28, 2015 at 12:42 PM, Sudeep Holla sudeep.ho...@arm.com wrote:
[...]
At-least I observed issue only when I am using hardware broadcast timer.
It doesn't hang when I am using hrtimer as broadcast timer in which case
one
On 28/04/15 15:14, Rafael J. Wysocki wrote:
On Tuesday, April 28, 2015 03:37:44 PM Rafael J. Wysocki wrote:
On Tuesday, April 28, 2015 03:31:54 PM Rafael J. Wysocki wrote:
On Tuesday, April 28, 2015 02:37:10 PM Linus Walleij wrote:
On Tue, Apr 28, 2015 at 2:19 PM, Rafael J. Wysocki
On 27/04/15 19:11, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
Hi,
This patch series adds support for:
1. SCPI(System Control and Power Interface) mailbox protocol
driver.
Is there a public document with the final protocol
On 28/04/15 14:54, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
This patch adds support for System Control and Power Interface (SCPI)
Message Protocol used between the Application Cores(AP) and the System
Control Processor(SCP). The MHU peripheral provides
clock event
device cannot go away from under code executed with interrupts disabled
on the local CPU), the simplified one below should be sufficient.
Tested-by: Sudeep Holla sudeep.ho...@arm.com
Regards,
Sudeep
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the body
Hi Viresh,
Thanks for the review.
On 29/04/15 06:44, Viresh Kumar wrote:
On 27 April 2015 at 17:10, Sudeep Holla sudeep.ho...@arm.com wrote:
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 4f3dbc8cf729..9e678bf1687c 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b
-foundation.org
Cc: Tejun Heo t...@kernel.org
Cc: Peter Zijlstra (Intel) pet...@infradead.org
Suggested-by: Pawel Moll pawel.m...@arm.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
lib/bitmap.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
v1-v2:
- Updated the doxygen
On 29/04/15 13:25, Jon Medhurst (Tixy) wrote:
On Wed, 2015-04-29 at 12:43 +0100, Jon Medhurst (Tixy) wrote:
On Wed, 2015-04-29 at 11:53 +0100, Sudeep Holla wrote:
On 28/04/15 14:54, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
[...]
+ int ret
Hi Tixy,
On 29/04/15 12:43, Jon Medhurst (Tixy) wrote:
On Wed, 2015-04-29 at 11:53 +0100, Sudeep Holla wrote:
On 28/04/15 14:54, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
[...]
+ int ret;
+ u8 token, chan;
+ struct scpi_xfer *msg
On 29/04/15 23:48, Andrew Morton wrote:
On Tue, 28 Apr 2015 16:36:41 +0100 Sudeep Holla sudeep.ho...@arm.com wrote:
bitmap_print_to_pagebuf uses scnprintf to copy the cpumask/list to page
buffer. It handles the newline and trailing null character explicitly.
bitmap_print_to_pagebuf
and also the
inclusion of asm/hardware/arm_timer.h header.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
---
arch/arm/mach-integrator
Since there are ARM64 platforms(e.g. Juno) with SP804 timers, we need
to move the driver out of arch/arm so that the code can be shared.
Regards,
Sudeep
Sudeep Holla (2):
ARM: simplify timer initialisation and remove arm_timer.h inclusion
ARM: move Dual-Timer SP804 driver to drivers
The ARM Dual-Timer SP804 module is peripheral found not only on ARM32
platforms but also on ARM64 platforms.
This patch moves the driver out of arch/arm to driver/clocksource
so that it can be used on ARM64 platforms also.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Russell King li
On 30/04/15 15:09, Rob Herring wrote:
On Thu, Apr 30, 2015 at 5:44 AM, Sudeep Holla sudeep.ho...@arm.com wrote:
The header asm/hardware/arm_timer.h is included in various machine
specific files to access TIMER_CTRL and initialise to a known state.
However that's not required as the clock
to scnprintf. This patch does that simplification.
Cc: Andrew Morton a...@linux-foundation.org
Cc: Tejun Heo t...@kernel.org
Cc: Peter Zijlstra (Intel) pet...@infradead.org
Suggested-by: Pawel Moll pawel.m...@arm.com
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
lib/bitmap.c | 11 ---
1
robh...@kernel.org
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Jassi Brar jaswinder.si...@linaro.org
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
.../devicetree/bindings/mailbox/arm-mhu.txt| 29 ++
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git
gets the frequency)
This patch adds check to see if the frequency is set correctly or if
they were any hardware failures and sends the appropriate errors to the
cpufreq core.
Cc: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Michael Turquette mike.turque...@linaro.org
Signed-off-by: Sudeep
in the consumer.
This patch removes the unused clock string from the driver.
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/cpufreq/arm_big_little.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/cpufreq
.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Rob Herring robh...@kernel.org
Cc: Mark Rutland mark.rutl...@arm.com
CC: Jassi Brar jassisinghb...@gmail.com
Cc: Liviu Dudau liviu.du...@arm.com
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Jon Medhurst (Tixy) t...@linaro.org
Cc: devicet
-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Stephen Boyd sb...@codeaurora.org
Cc: Liviu Dudau liviu.du...@arm.com
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Jon Medhurst (Tixy) t...@linaro.org
Cc: linux-...@vger.kernel.org
---
drivers/clk/clk-scpi.c | 13
support for the clocks provided by SCP using SCPI
protocol.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Stephen Boyd sb...@codeaurora.org
Cc: Liviu Dudau liviu.du...@arm.com
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Jon Medhurst (Tixy) t
for clocks provided by SCP firmware through
the SCPI interface
3. Using the existing arm_big_little cpufreq driver and the
newly added SCPI clock driver, it also adds support for DVFS
on ARM64 JUNO development platforms.
Regards,
Sudeep
Sudeep Holla (4):
mailbox: add
the arm_big_little cpufreq driver for such systems.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Viresh Kumar viresh.ku...@linaro.org
Cc: Rafael J. Wysocki r...@rjwysocki.net
Cc: linux...@vger.kernel.org
---
drivers/cpufreq/Kconfig.arm| 9
drivers/cpufreq/Makefile | 1
Hi Tejun,
On 27/04/15 17:30, Tejun Heo wrote:
Hello, Sudeep.
On Mon, Apr 27, 2015 at 05:26:16PM +0100, Sudeep Holla wrote:
Completely agree and in-fact we did discuss that internally too.
But since this function deals only with page size buffers, we thought
it's highly unlikely to hit
On 27/04/15 17:14, Tejun Heo wrote:
Hello, Sudeep.
On Mon, Apr 27, 2015 at 10:46:58AM +0100, Sudeep Holla wrote:
int bitmap_print_to_pagebuf(bool list, char *buf, const unsigned long *maskp,
int nmaskbits)
{
- ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE
On 28/04/15 08:36, Paul Bolle wrote:
Just one nit: a license mismatch.
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
--- /dev/null
+++ b/drivers/mailbox/scpi_protocol.c
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions
Hi Tixy,
On 27/04/15 19:11, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
Hi,
This patch series adds support for:
1. SCPI(System Control and Power Interface) mailbox protocol
driver.
Is there a public document with the final protocol
On 01/05/15 18:10, Jon Medhurst (Tixy) wrote:
On Fri, 2015-05-01 at 15:15 +0100, Sudeep Holla wrote:
No issues, it's better to have remainders like this :). I plan to post
something in the next version.
Will that also include the other piece of the puzzle to get the
big.LITTLE cpufreq
On 01/05/15 15:12, Jon Medhurst (Tixy) wrote:
On Fri, 2015-05-01 at 14:32 +0100, Sudeep Holla wrote:
On 01/05/15 14:19, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP
On 28/04/15 11:11, Linus Walleij wrote:
On Thu, Apr 2, 2015 at 12:22 AM, Rafael J. Wysocki r...@rjwysocki.net wrote:
From: Thomas Gleixner t...@linutronix.de
Replace the clockevents_notify() call with an explicit function call.
Signed-off-by: Thomas Gleixner t...@linutronix.de
On 28/04/15 11:34, Daniel Lezcano wrote:
On 04/28/2015 12:11 PM, Linus Walleij wrote:
On Thu, Apr 2, 2015 at 12:22 AM, Rafael J. Wysocki
r...@rjwysocki.net wrote:
From: Thomas Gleixner t...@linutronix.de
Replace the clockevents_notify() call with an explicit function
call.
Signed-off-by:
On 01/05/15 14:19, Jon Medhurst (Tixy) wrote:
On Mon, 2015-04-27 at 12:40 +0100, Sudeep Holla wrote:
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control including CPU DVFS. SCPI Message Protocol is used
, which represents a generic container device.
This patch enables the support for these ACPI processor containers.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
Documentation/memory-hotplug.txt | 2 +-
drivers/acpi/container.c | 1 +
2 files changed, 2 insertions(+), 1 deletion
also help in enabling ACPI_PROCESSOR on ARM64 which is currently
disabled and few others are just to be consistent.
Regards,
Sudeep
Sudeep Holla (5):
ACPI / containers : add support for ACPI0010 processor container
ACPI / processor: always compile perflib if CONFIG_ACPI_PROCESSOR
ACPI
the processor_idle module to support
LPI.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
arch/ia64/Kconfig | 1 +
arch/x86/Kconfig | 1 +
arch/x86/include/asm/acpi.h | 2 --
drivers/acpi/Kconfig | 3 +++
drivers/acpi/processor_idle.c | 57
Like few of the other ACPI modules, replace PREFIX with pr_fmt and
change all the printk call sites to use pr_* companion functions
in processor_idle.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/acpi/processor_idle.c | 25 +++--
1 file changed, 11 insertions
configuration.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/acpi/Makefile| 2 +-
include/acpi/processor.h | 29 -
include/linux/cpufreq.h | 4
3 files changed, 5 insertions(+), 30 deletions(-)
diff --git a/drivers/acpi/Makefile b/drivers
it depend on CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT so that
it's not compiled on architecture like ARM64 where S-states are not
yet defined in ACPI.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/acpi/processor_idle.c | 37 -
drivers/acpi/sleep.c
Hi Preeti,
On 07/05/15 06:26, Preeti U Murthy wrote:
When a CPU has to enter an idle state where tick stops, it makes a call
to tick_broadcast_enter(). The call will fail if this CPU is the
broadcast CPU. Today, under such a circumstance, the arch cpuidle code
handles this CPU. This is not
On 08/05/15 09:52, Hanjun Guo wrote:
On 2015年05月07日 02:36, Ashwin Chaugule wrote:
Hello,
On 6 May 2015 at 10:31, Sudeep Holla sudeep.ho...@arm.com wrote:
Similar to the idle, thermal and throttling libraries, always compile
the perflib if CONFIG_ACPI_PROCESSOR is enabled. This not only
On 08/05/15 15:06, Rafael J. Wysocki wrote:
On Friday, May 08, 2015 04:50:10 PM Hanjun Guo wrote:
Hi Sudeep,
On 2015年05月06日 22:31, Sudeep Holla wrote:
ACPI 6.0 adds support for optional processor container device which may
contain child objects that are either processor devices or other
to have fixed only them. I need to fix my habit of eating away
the characters ;)
Acked-by: Sudeep Holla sudeep.ho...@arm.com
Regards,
Sudeep
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to remove BL_SWITCHER dependency in the driver.
Cc: Viresh Kumar viresh.ku...@linaro.org
Cc: Rafael J. Wysocki r...@rjwysocki.net
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
---
drivers/cpufreq/Kconfig.arm | 2 +-
drivers/cpufreq/arm_big_little.c | 27 ++-
2 files
.
Tested on ARM Vexpress platforms with one of the CPU in broadcast mode
and also with broadcast timer. So, you can add:
Tested-by: Sudeep Holla sudeep.ho...@arm.com
Regards,
Sudeep
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On 05/05/15 03:46, Hanjun Guo wrote:
Just use pr-id instead of cpu_index to simplify the code.
IIRC pr-id is u32, has it changed in any other patches that's not in
mainline ? Otherwise, comparing it with -1 makes no sense here.
Regards,
Sudeep
Signed-off-by: Hanjun Guo
On 05/05/15 03:46, Hanjun Guo wrote:
In ACPI processor drivers, we use direct comparisons of cpu logical
id with -1 which are error prone in case logical cpuid is accidentally
assinged an error code and prevents us from returning an error-encoding
cpuid directly in some cases.
So introduce
On 05/05/15 03:46, Hanjun Guo wrote:
Introduce invalid_phys_cpuid() to identify cpu with invalid
physical ID, then used it as replacement of the direct comparisons
with PHYS_CPUID_INVALID.
Signed-off-by: Hanjun Guo hanjun@linaro.org
---
drivers/acpi/acpi_processor.c | 4 ++--
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