,
+ },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR(Xing Zheng zhengx...@rock-chips.com);
+MODULE_DESCRIPTION(Rockchip general machine ASoC driver);
+MODULE_LICENSE(GPL v2);
+MODULE_ALIAS(platform: DRV_NAME);
+MODULE_DEVICE_TABLE(of, rockchip_machine_of_match);
diff --git a/sound/soc/rockchip
,rockchip-audio-max98090);
+
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+MODULE_AUTHOR(jianqun jay...@rock-chips.com);
+MODULE_AUTHOR(Xing Zheng zhengx...@rock-chips.com);
+MODULE_DESCRIPTION(Rockchip max98090 machine ASoC driver);
+MODULE_LICENSE(GPL v2);
--
1.7.9.5
From: zhengxing zhengx...@rock-chips.com
Hi,
These patches to add machine driver for rockchip platform.
We intended to use simple-card on the project, but it seem like that have
some issues(jack detection). We need the following features on the project,
but simple-card is temporarily unable to
)) {
+ /* pre-init snd card info. */
+ soc_card-card = snd_soc_card_rk;
+ strcpy(soc_card-compatible,
+ rockchip,rockchip-audio-rt5645);
+
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+MODULE_AUTHOR(Xing Zheng zhengx...@rock
From: zhengxing zhengx...@rock-chips.com
Add documentation to the machine driver of the device-tree
bindings for the soundcard of the Rockchip board.
Signed-off-by: zhengxing zhengx...@rock-chips.com
---
.../sound/rockchip,rockchip-audio-machine.txt | 38
1 file
From: zhengxing zhengx...@rock-chips.com
The driver is used for rockchip board using a max98090.
Reviewed-by: Dylan Reid dgr...@chromium.org
Signed-off-by: zhengxing zhengx...@rock-chips.com
---
sound/soc/rockchip/Kconfig | 10 ++
sound/soc/rockchip/Makefile|4 +
,
+ .owner = THIS_MODULE,
+ .pm = snd_soc_pm_ops,
+ .of_match_table = rockchip_rt5645_of_match,
+ },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR(Xing Zheng zhengx...@rock-chips.com);
+MODULE_DESCRIPTION(Rockchip rt5645 machine ASoC
From: zhengxing zhengx...@rock-chips.com
Hi,
The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.
From: zhengxing zhengx...@rock-chips.com
The driver is used for rockchip board using a max98090.
Reviewed-by: Dylan Reid dgr...@chromium.org
Signed-off-by: zhengxing zhengx...@rock-chips.com
---
Changes in v2: None
.../bindings/sound/rockchip-max98090.txt | 19 ++
,
+ .of_match_table = rockchip_rt5645_of_match,
+ },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR(Xing Zheng zhengx...@rock-chips.com);
+MODULE_DESCRIPTION(Rockchip rt5645 machine ASoC driver);
+MODULE_LICENSE(GPL v2);
+MODULE_ALIAS(platform: DRV_NAME
From: zhengxing zhengx...@rock-chips.com
Hi,
The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.
On 2015年07月18日 17:16, Mark Brown wrote:
On Sat, Jul 18, 2015 at 01:08:43PM +0800, Xing Zheng wrote:
+ ret = devm_snd_soc_register_card(pdev-dev, card);
+ if (ret) {
+ dev_err(pdev-dev,
+ Soc register card failed %d\n, ret);
+ return
From: zhengxing zhengx...@rock-chips.com
Hi,
The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.
,
+ .pm = snd_soc_pm_ops,
+ .of_match_table = rockchip_rt5645_of_match,
+ },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR(Xing Zheng zhengx...@rock-chips.com);
+MODULE_DESCRIPTION(Rockchip rt5645 machine ASoC driver);
+MODULE_LICENSE(GPL v2);
+MODULE_ALIAS
From: zhengxing zhengx...@rock-chips.com
The driver is used for rockchip board using a max98090.
Reviewed-by: Dylan Reid dgr...@chromium.org
Signed-off-by: zhengxing zhengx...@rock-chips.com
---
Changes in v3: None
.../bindings/sound/rockchip-max98090.txt | 19 ++
From: zhengxing zhengx...@rock-chips.com
The driver is used for rockchip board using a max98090.
Reviewed-by: Dylan Reid dgr...@chromium.org
Signed-off-by: zhengxing zhengx...@rock-chips.com
---
Changes in v3: None
.../bindings/sound/rockchip-max98090.txt | 19 ++
,
+ .pm = snd_soc_pm_ops,
+ .of_match_table = rockchip_rt5645_of_match,
+ },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR(Xing Zheng zhengx...@rock-chips.com);
+MODULE_DESCRIPTION(Rockchip rt5645 machine ASoC driver);
+MODULE_LICENSE(GPL v2);
+MODULE_ALIAS
From: zhengxing zhengx...@rock-chips.com
Hi,
The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v5: None
.../bindings/clock/rockchip,rk
tion of rk3036 clock controller
Changes in v5:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Heiko Stuebner (1):
ARM: rockchip: add support smp for rk3036
Xing Zheng (7):
dt-bindings: add documentation of rk3036 clock controller
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v5: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v5: None
include/dt-bindings/clock/rk3036-
d-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Xing Zheng <zhengx...@rock-chips.com>
Signed-off-by:
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v5: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v5:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
arch/arm/mach-rockchip/rockc
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v5: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/
d-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Xing Zheng <zhengx...@rock-chips.com>
Signed-off-by:
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v4: None
include/dt-bindings/clock/rk3036-
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v4: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v4: None
.../bindings/clock/rockchip,rk
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v4: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v4: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v4:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
arch/arm/mach-rockchip/rockc
) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add new pll-type for rk3036 and similar socs
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v4:
Signed-off-by
On 2015年11月05日 07:39, Heiko Stuebner wrote:
Hi,
Am Mittwoch, 4. November 2015, 20:18:16 schrieb Xing Zheng:
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>
Reviewed-by:
On 2015年11月05日 07:33, Heiko Stuebner wrote:
Am Mittwoch, 4. November 2015, 20:25:16 schrieb Xing Zheng:
From: Heiko Stuebner<he...@sntech.de>
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of t
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v7: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/
Enable smp for rk3036, and add the smp sram name for adapting.
---
Changes in v7:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v7: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v7: N
for rk3036
3) clk: rockchip: add new pll-type for rk3036 and similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v7:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he.
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v7: None
include/dt-bindings/clock/
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v6: None
include/dt-bindings/clock/rk3036-
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v6: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v6: None
.../bindings/clock/rockchip,rk
similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v6:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Heiko Stuebner (1):
ARM: rockchip: add support smp
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v6: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v6: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/
d-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Xing Zheng <zhengx...@rock-chips.com>
Signed-off-by:
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v6:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
arch/arm/mach-rockchip/rockc
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v2:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Reviewed-by: Dylan Reid dgr...@chromium.org
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion
Hi,
We need to support rk3036 soc platform via upstream, there are
3 parts for the initial release of minimum system: dts, pinctrl,
and clock tree for rk3036, startup and run to init processs.
Thanks.
Changes in v1:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Xing Zheng (3):
ARM: dts
Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume should be done
in clk-rk3036.c
---
Changes in v1:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Many parts of pinctrl rk3036 are similar to rk2928's.
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
---
Changes in v1: None
drivers/pinctrl/pinctrl-rockchip.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
---
Changes in v1: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-sdk.dts | 362 ++
2 files changed, 363 insertions
HI Heiko,
Thank you for your reply. I will improve them as quickly as possible.
Thanks. :)
On 2015年08月28日 17:59, Heiko Stuebner wrote:
Hi,
Am Freitag, 28. August 2015, 13:46:45 schrieb Xing Zheng:
We need to support rk3036 soc platform via upstream, there are
3 parts for the initial release
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v1:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Reviewed-by: Dylan Reid dgr...@chromium.org
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion
Hi,
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
Thanks.
Changes in v1:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Reviewed-by: Dylan Reid dgr...@chromium.org
Xing Zheng (1):
ASoC: rockchip: fix a misjudgement by return
sound
Hi,
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
Thanks.
Changes in v1:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Reviewed-by: Dylan Reid dgr...@chromium.org
Xing Zheng (1):
ASoC: rockchip: fix a misjudgement by return
sound
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v1:
Signed-off-by: Xing Zheng zhengx...@rock-chips.com
Reviewed-by: Dylan Reid dgr...@chromium.org
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
.../bindings/clock/rockchip,rk3036-cru.txt | 60
1 file chang
Add new type for rk3036 and many parts of pinctrl rk3036 are similar
with rk2928's.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
.../bindings/pinctrl/rockchip,pinctrl.txt |1 +
drivers/pinctrl/pinctrl-rockchip.c
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
arch/arm/mach-rockchip/rockchip.c | 22 ++
1 file chang
The rk3036 is dual-core soc, we can use this patch to enable cpu1
enter boot secondary, and hotplug(online/offline).
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
arch/arm/mach-rockchip/platsmp.c | 121 ++
1 file change
(946684920)
---
Changes in v2:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
drivers/rtc/rtc-hym8563.c | 93 +
1 file changed, 93 insertions(+)
diff --git a/drivers/rtc/rtc-hym8563.c b/drivers/rtc/rtc-hym8563.c
index 097325d..ea37fdf
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c | 504 +
drivers/clk/rockchip
On 2015年08月28日 17:54, Heiko Stuebner wrote:
Hi,
Am Freitag, 28. August 2015, 13:46:48 schrieb Xing Zheng:
Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume
On 2015年08月28日 16:59, Heiko Stuebner wrote:
Hi,
Am Freitag, 28. August 2015, 13:46:46 schrieb Xing Zheng:
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>
---
Changes in v1: None
arch/arm/boot/dts/Makefile
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-sdk.dts | 62 +++
arch/arm/boot/dts/rk3036.dtsi
controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) ARM: dts: rockchip: add core rk3036 dts
Changes in v2:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Xing Zheng (9):
ARM: dts: rockchip: add core rk3036 dts
clk: rockchip: add dt-binding header for rk3036
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
include/dt-bindings/clock/rk3036-cru.h | 198
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
C
On 2015年09月17日 20:31, Alexandre Belloni wrote:
Hi,
On 17/09/2015 at 14:07:47 +0200, Heiko Stübner wrote :
Am Donnerstag, 17. September 2015, 18:39:28 schrieb Xing Zheng:
The rtc hym8563 maybe failed to register if first startup or rtc
powerdown:
[0.988540 ] rtc-hym8563 1-0051: no valid
On 2015年09月18日 04:15, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 18:38:06 schrieb Xing Zheng:
The rk3036 is dual-core soc, we can use this patch to enable cpu1
enter boot secondary, and hotplug(online/offline).
Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>
---
Changes
On 2015年09月17日 23:05, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 18:37:24 schrieb Xing Zheng:
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
please kindly ask the people doing uboot development
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +++
a
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c
The rk3036 is dual-core soc, we can use this patch to enable cpu1
enter boot secondary, and hotplug(online/offline).
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
arch/arm/mach-rockchip/plat
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
include/dt-bindings/clock/rk3036-
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
.../bindings/clock/rockchip,rk
tion of rk3036 clock controller
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) ARM: dts: rockchip: add core rk3036 dts
Changes in v3:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
On 2015年09月28日 20:44, Heiko Stübner wrote:
Hi,
Am Montag, 28. September 2015, 20:25:07 schrieb Xing Zheng:
On 2015年09月17日 23:05, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 18:37:24 schrieb Xing Zheng:
The timer5 supplies the architected timer and thus as has to run when
Enable the rk3036's cpu1 and smp.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
arch/arm/boot/dts/rk3036.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v3:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
arch/arm/mach-rockchip/rockc
On 2015年09月24日 11:04, Xing Zheng wrote:
#define RK3066_PLL_RATE(_rate, _nr, _nf, _no)\
@@ -95,12 +106,31 @@ enum rockchip_pll_type {
.nb = _nb,\
}
+#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,\
+_postdiv2, _dsmpd, _frac
On 2015年09月17日 23:09, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 18:32:49 schrieb Xing Zheng:
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>
---
Changes
On 2015年09月17日 17:18, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng:
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>
---
Changes in v2: None
arch/arm/boot/dts/Makefile
On 2015年09月17日 17:25, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 16:28:53 schrieb Xing Zheng:
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng<zhengx...@rock-chips.
On 2015年09月17日 17:47, Heiko Stübner wrote:
Hi,
Am Donnerstag, 17. September 2015, 16:28:54 schrieb Xing Zheng:
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>
missing a dt-bindings document in a separate patch. See "dt-bi
Hi Heiko,
Thank you for your patch, I will apply and test it later.
Thanks.
> 在 2016年1月2日，06:10，Heiko Stübner <he...@sntech.de> 写道：
>
> Hi Xing,
>
> Am Dienstag, 29. Dezember 2015, 10:34:09 schrieb Xing Zheng:
>> On 2015年12月29日 09:59, Yakir Yang wrote:
>&g
OK, I think I will use named structures.
Thanks.
> 在 2016年1月1日，20:55，Arnd Bergmann <a...@arndb.de> 写道：
>
>> On Tuesday 29 December 2015 14:59:59 Florian Fainelli wrote:
>>> On December 27, 2015 11:22:20 PM PST, Xing Zheng <zhengx...@rock-chips.com>
>&g
Hi Heiko,
On 2016年01月02日 10:34, Xing Zheng wrote:
> Hi Heiko,
> Thank you for your patch, I will apply and test it later.
>
> Thanks.
>
>> 在 2016年1月2日，06:10，Heiko Stübner <he...@sntech.de> 写道：
>>
>> Hi Xing,
>>
>> Am Dienstag, 29. Dezember 20
Due to reference to old version TRM, there are incorrect emac clock node.
The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the
child div.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c |4 ++--
1 file changed, 2 insertions
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags
of COMPOSITE_NODIV type should be MFLAGS.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drive
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, we should to fix it.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk
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