Re: [PATCH v1 3/3] ipc: Add support for default interrupt mode

Can you document this in the help text? It's unclear whether people should enable this option or not. Thanks for the review. I will update the help content in my next patchset. -- Matthew Garrett matthew.garr...@nebula.com -- Sathyanarayanan Kuppuswamy -- To unsubscribe from this list: send

Re: [PATCH v2.2] ipc: Added support for IPC interrupt mode

On 11/20/2013 05:47 PM, Matthew Garrett wrote: On Wed, 2013-11-20 at 17:45 -0800, Kuppuswamy Sathyanarayanan wrote: - Changed INIT_COMPLETION to reinit_completion. Thanks, I've already folded that fix into the patch and re-pushed. Thanks. -- Sathyanarayanan Kuppuswamy Android kernel

[PATCH v1 01/13] mrst: Fixed printk/pr_* related issues

Fixed printk and pr_* related issues in mrst related files. Change-Id: I7dafe04f1cd6a0ee2c97672b98441ade5b2000a7 Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/pci/mrst.c|2 +- arch/x86/platform/mrst/early_printk_mrst.c

[PATCH v1 07/13] intel_mid: Added custom device_handler support

This patch provides a means to add custom handler for SFI devices. If you set device_handler as NULL in device_id table standard SFI device handler will be used. If its not NULL custom handler will be called. Change-Id: I294371004b2c4b6bb0713fd6f5ea94ab0fc2df52 Signed-off-by: Sathyanarayanan

[PATCH v1 11/13] sfi: fix compiler warnings

From: Andy Shevchenko andriy.shevche...@linux.intel.com drivers/sfi/sfi_core.c:164:26: warning: no previous prototype for ‘sfi_map_table’ [-Wmissing-prototypes] drivers/sfi/sfi_core.c:192:6: warning: no previous prototype for ‘sfi_unmap_table’ [-Wmissing-prototypes] Change-Id:

[PATCH v1 13/13] x86: mrst: move to generic SFI GPIO API

Let's use the common SFI helpers for GPIO API. Change-Id: I7aba6e61af7df3e34ffc4dfe161ab6ea2d723691 Signed-off-by: Andy Shevchenko andriy.shevche...@linux.intel.com Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/include/asm/intel-mid.h

[PATCH v1 06/13] intel_mid: Refactored sfi_parse_devs() function

handlers. Change-Id: I995bcf6ab872272d4a08a900231ddc5f3110c8a6 Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/platform/intel-mid/intel-mid.c | 141 --- 1 file changed, 71 insertions(+), 70 deletions(-) diff --git a/arch/x86

[PATCH v1 12/13] gpiolib: append SFI helpers for GPIO API

From: Andy Shevchenko andriy.shevche...@linux.intel.com To support some (legacy) firmwares and platforms let's make life easier for their customers. Change-Id: I39a0e3e0ed4e04a0d733801f59d46d76189195e8 Signed-off-by: Andy Shevchenko andriy.shevche...@linux.intel.com --- drivers/gpio/Kconfig

[PATCH v1 10/13] intel_mid: Moved SFI related code to intel_mid_sfi.c

Moved SFI specific parsing/handling code to intel_mid_sfi.c. This will enable us to reuse our intel-mid code for platforms that supports firmware interfaces other than SFI (like ACPI). Change-Id: I95f6c233914c949fda8a7d14715a7e954fe7512e Signed-off-by: Sathyanarayanan Kuppuswamy

[PATCH v1 05/13] intel_mid: Renamed *mrst* to *intel_mid*

changes, I have compared the objdump of related files before and after rename and found the only difference is symbol and name changes. Change-Id: I86729b45c653def052d8275edd50cdae76edb18d Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- Documentation/kernel

[PATCH v1 04/13] intel_mid: Renamed *mrst* to *intel_mid*

-Id: I33f23d7d662eda6e33ecead26fb3fe453ab66345 Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/include/asm/{mrst.h = intel-mid.h} |8 .../include/asm/{mrst-vrtc.h = intel_mid_vrtc.h} |4 ++-- arch/x86/kernel/apb_timer.c

[PATCH v1 03/13] mrst: Fixed checkpatch warnings

Fixed checkpatch warnings in mrst related files. Change-Id: I4aa558a1b1c261444ae6b63b0da6273923d0afaa Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/pci/mrst.c |2 +- arch/x86/platform/mrst/mrst.c |2 +- arch/x86/platform/mrst/vrtc.c

[PATCH v1 08/13] intel_mid: Added custom handler for ipc devices

Added a custom handler for medfield based ipc devices and moved devs_id structure defintion to header file. Change-Id: Ib34d12e0f70da9b0890972d286072369bebf349d Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/include/asm/intel-mid.h| 15

[PATCH v1 02/13] mrst: Fixed indentation issues

Fixed indentation issues reported by checkpatch script in mrst related files. Change-Id: I4deceed3ff2fc92bdb8118300f18eed963b9b988 Signed-off-by: Sathyanarayanan Kuppuswamy sathyanarayanan.kuppusw...@intel.com --- arch/x86/pci/mrst.c|4 ++-- arch/x86/platform/mrst

[PATCH v1 00/13] mrst refactoring patches

. Patch 6 - 13 refactors mrst code. Andy Shevchenko (2): sfi: fix compiler warnings gpiolib: append SFI helpers for GPIO API Sathyanarayanan Kuppuswamy (11): mrst: Fixed printk/pr_* related issues mrst: Fixed indentation issues mrst: Fixed checkpatch warnings intel_mid: Renamed *mrst

Re: [PATCH v2 09/10] intel_mid: Moved board related code to a new file

On Wed, Oct 09, 2013 at 11:00:06PM -0700, David Cohen wrote: From: Kuppuswamy Sathyanarayanan sathyanarayanan.kuppusw...@linux.intel.com +# I2C Devices +obj-$(subst m,y,$(CONFIG_SENSORS_EMC1403)) += platform_emc1403.o +obj-$(subst m,y,$(CONFIG_SENSORS_LIS3LV02D)) += platform_lis331.o I am

Re: [PATCH v1 02/10] x86, intel-mid: Remove weak from function declarations

*get_penwell_ops(void); +extern void *get_cloverview_ops(void); +extern void *get_tangier_ops(void); -- Sathyanarayanan Kuppuswamy Android kernel developer -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info

Re: [PATCH] IIO: Adds ACPI support for ST gyroscopes

) +{ + return -ENXIO; +} #endif /* Device properties */ -- To unsubscribe from this list: send the line unsubscribe linux-iio in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Sathyanarayanan Kuppuswamy

Re: [PATCH 0/2] ACPI: Translate Linux IRQ number directly from GpioInt

On 04/29/2015 02:26 AM, Mika Westerberg wrote: On Tue, Apr 28, 2015 at 10:36:48AM -0700, sathyanarayanan kuppuswamy wrote: This requires that the boot firmware (BIOS/coreboot) configures these pins correctly (input, etc) before handing over to OS. I've tested this on Intel Baytrail, Braswell

Re: [RFC PATCH 3/3] iio: derive the mounting matrix from ACPI _PLD objects

...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Sathyanarayanan Kuppuswamy Android kernel developer -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http

Re: [RFC PATCH 3/3] iio: derive the mounting matrix from ACPI _PLD objects

Hi Octavian, On 04/27/2015 07:23 PM, Octavian Purdila wrote: On Tue, Apr 28, 2015 at 12:57 AM, sathyanarayanan kuppuswamy sathyanarayanan.kuppusw...@linux.intel.com wrote: Hi On 04/27/2015 08:54 AM, Octavian Purdila wrote: On Mon, Apr 27, 2015 at 6:42 PM, Kuppuswamy Sathyanarayanan

Re: [PATCH 0/2] ACPI: Translate Linux IRQ number directly from GpioInt

| 29 + drivers/i2c/i2c-core.c | 9 +++-- include/linux/acpi.h| 7 +++ 3 files changed, 43 insertions(+), 2 deletions(-) -- Sathyanarayanan Kuppuswamy Android kernel developer -- To unsubscribe from this list: send the line unsubscribe linux

Re: [PATCH v1 1/1] iio: ltr501: Add light channel support

in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Sathyanarayanan Kuppuswamy Android kernel developer -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord

Re: [PATCH] iio: light: jsa1212: remove unneeded i2c check functionality test

(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) - return -EOPNOTSUPP; - indio_dev = devm_iio_device_alloc(>dev, sizeof(*data)); if (!indio_dev) return -ENOMEM; -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH 1/1] intel-mid: Fix sfi get_platform_data() return value issues

intel_scu_i2c_device_register(pentry->host_num, _info); @@ -424,8 +431,10 @@ static void __init sfi_handle_sd_dev(struct sfi_device_table_entry *pentry, sd_info.max_clk, sd_info.addr); pdata = intel_mid_sfi_get_pdata(dev, _info); - if (IS_ERR(pdat

Re: [PATCH v2 1/1] intel-mid: Fix sfi get_platform_data() return value issues

gpio_base = get_gpio_by_name(base_pin_name); intr = get_gpio_by_name(intr_pin_name); - if (gpio_base < 0) + if (gpio_base < 0) { + pr_err("%s: Unknown GPIO base number, falling back to dynamic" + "allocation\n", __func__); Ditto. -- Sathyanarayanan Kuppuswamy Android kernel developer

[PATCH v1 1/1] mfd: bxtwc: remove unnecessary i2c_addr checks in ipc calls

From: Kuppuswamy Sathyanarayanan In the following code block, BXTWC_DEVICE1_ADDR value is already fixed and hence there no need to check for if (!i2c_addr) in every ipc read/write calls. Even if this check is required it can be moved to probe function.

Re: [PATCH v3 4/5] platform/x86: intel_pmc_ipc: Fix iTCO GCS memory mapping failure

->start + PLAT_RESOURCE_GCR_OFFSET; ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; dev_info(>dev, "ipc res: %pR\n", res); -- 2.7.4 -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v2 1/4] platform/x86: intel_pmc_ipc: fix gcr offset

0x1000 -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 #define PLAT_RESOURCE_GCR_SIZE0x1000 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 #define PLAT_RESOURCE_BIOS_IFACE_INDEX2 -- 2.7.4 -- Sathyanarayanan Kuppuswamy An

Re: [PATCH v2 3/4] watchdog: iTCO_wdt: Fix PMC GCR memory mapping failure

tested this on APL and i see iTCO_WDT driver loads fine. Since it impacts core WDT functionality, need to be thoroughly tested on various platforms. I have tested it in Joule and it works fine. it would be nice if some one can verify it in non-atom platforms. -- 2.7.4 -- Sathyanarayanan

Re: [PATCH v2 2/4] platform/x86: intel_pmc_ipc: Add pmc gcr read/write api's

CR_OFFSET; + ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; dev_info(>dev, "ipc res: %pR\n", res); -- 2.7.4 -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v2 3/4] watchdog: iTCO_wdt: Fix PMC GCR memory mapping failure

C if its version iTCO_version >= 2. Guenter -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v2 3/4] watchdog: iTCO_wdt: Fix PMC GCR memory mapping failure

Hi Andy, On 03/17/2017 11:38 AM, Andy Shevchenko wrote: On Fri, Mar 17, 2017 at 7:37 PM, sathyanarayanan kuppuswamy <sathyanarayanan.kuppusw...@linux.intel.com> wrote: On 03/17/2017 07:25 AM, Andy Shevchenko wrote: On Fri, Mar 17, 2017 at 3:40 PM, Guenter Roeck <li...@roeck-us.n

Re: [PATCH v2 3/4] watchdog: iTCO_wdt: Fix PMC GCR memory mapping failure

702.3/01408.html -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v2 3/4] watchdog: iTCO_wdt: Fix PMC GCR memory mapping failure

On 03/17/2017 10:50 AM, Guenter Roeck wrote: On Fri, Mar 17, 2017 at 10:24:35AM -0700, sathyanarayanan kuppuswamy wrote: On 03/17/2017 06:40 AM, Guenter Roeck wrote: On 03/17/2017 04:43 AM, Rajneesh Bhardwaj wrote: On Thu, Mar 16, 2017 at 05:41:35PM -0700, Kuppuswamy Sathyanarayanan wrote

Re: [PATCH v1 1/1] platform/x86: intel_pmc_ipc: fix io mem mapping size

0ix_size); release_mem_region(res->start, - PLAT_RESOURCE_IPC_SIZE + - PLAT_RESOURCE_GCR_SIZE); + PLAT_RESOURCE_IPC_SIZE); } ipcdev.dev = NULL; return 0; -- 2.7.4 -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v1 1/1] platform/x86: intel_pmc_ipc: fix io mem mapping size

iTCO_WDT device. -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v1 1/1] platform/x86: intel_pmc_ipc: fix io mem mapping size

On 03/16/2017 12:20 PM, Rajneesh Bhardwaj wrote: On Thu, Mar 16, 2017 at 11:50:16AM -0700, sathyanarayanan kuppuswamy wrote: Hi, On 03/16/2017 07:52 AM, Rajneesh Bhardwaj wrote: On Wed, Mar 15, 2017 at 08:32:53PM -0700, Kuppuswamy Sathyanarayanan wrote: Mapping entire GCR mem region

Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset

On 04/04/2017 06:25 AM, Andy Shevchenko wrote: Please, STOP top-posting. On Mon, Apr 3, 2017 at 4:51 AM, Sathyanarayanan Kuppuswamy Natarajan <sathyao...@gmail.com> wrote: Yes, just applying this patch will fix the existing offset issue. Then the question how it was tested in both

Re: [PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's

ock' is missed in the label name. "goto" to this label is only used when there is an error in update operation. Do you think we should still rename it to gcr_ipc_unlock ? + mutex_unlock(); + return ret; +} +EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's

Hi Andy, On 04/04/2017 06:23 AM, Andy Shevchenko wrote: On Mon, Apr 3, 2017 at 4:51 AM, Sathyanarayanan Kuppuswamy Natarajan <sathyao...@gmail.com> wrote: +static inline int is_gcr_valid(u32 offset) Pointer to ipcdev should be a parameter to this function. But ipcdev is a static va

Re: [PATCH v5 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read

_REG); + shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG); *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); -- 2.7.4 -- Sathyanarayanan Kuppuswamy Android kernel developer

[PATCH v1 6/7] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

From: Kuppuswamy Sathyanarayanan Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to

[PATCH v1 5/7] gpio: gpio-wcove: use first level PMIC GPIO irq

From: Kuppuswamy Sathyanarayanan PMIC mfd driver only exports first level irq for GPIO device. But currently we are reading the irqs from the second level irq chip, So this patch fixes this issue by adding support to use first level PMIC GPIO irq.

[PATCH v1 4/7] mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device

From: Kuppuswamy Sathyanarayanan Currently all PMIC GPIO domain irqs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO irq(BXTWC_GPIO_LVL1_IRQ) as an

[PATCH v1 2/7] mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs

From: Kuppuswamy Sathyanarayanan Since all second level thermal irqs are consumed by the same device(bxt_wcove_thermal), there is no need to expose them as separate interrupts. We can just export only the first level irqs for thermal and let the

[PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index

From: Kuppuswamy Sathyanarayanan TMU interrupts are registered as a separate interrupt chip, and hence it should start its interrupt index(BXTWC_TMU_IRQ) number from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum bxtwc_irqs_level2 and its

[PATCH v1 7/7] platform: x86: intel_bxtwc_tmu: remove first level irq unmask

From: Kuppuswamy Sathyanarayanan Currently in WCOVE PMIC mfd driver, all second level irq chips are chained to the respective first level irqs. So there is no need for explicitly unmasking the first level irq in this driver. This patches removes this

[PATCH v1 3/7] thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq

From: Kuppuswamy Sathyanarayanan PMIC mfd driver only exports first level irq for thermal device. But currently we are reading the irqs from the second level irq chip, So this patch fixes this issue by adding support to use first level PMIC thermal

[PATCH v2 3/8] thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq

From: Kuppuswamy Sathyanarayanan PMIC mfd driver only exports first level irq for thermal device. But currently we are reading the irqs from the second level irq chip, So this patch fixes this issue by adding support to use first level PMIC thermal

[PATCH v2 2/8] mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs

From: Kuppuswamy Sathyanarayanan Since all second level thermal irqs are consumed by the same device(bxt_wcove_thermal), there is no need to expose them as separate interrupts. We can just export only the first level irqs for thermal and let the

[PATCH v2 1/8] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index

From: Kuppuswamy Sathyanarayanan TMU interrupts are registered as a separate interrupt chip, and hence it should start its interrupt index(BXTWC_TMU_IRQ) number from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum bxtwc_irqs_level2 and its

[PATCH v2 4/8] mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device

From: Kuppuswamy Sathyanarayanan Currently all PMIC GPIO domain irqs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO irq(BXTWC_GPIO_LVL1_IRQ) as an

[PATCH v2 8/8] platform: x86: intel_bxtwc_tmu: remove first level irq unmask

From: Kuppuswamy Sathyanarayanan Currently in WCOVE PMIC mfd driver, all second level irq chips are chained to the respective first level irqs. So there is no need for explicitly unmasking the first level irq in this driver. This patches removes this

[PATCH v2 5/8] gpio: gpio-wcove: use first level PMIC GPIO irq

From: Kuppuswamy Sathyanarayanan PMIC mfd driver only exports first level irq for GPIO device. But currently we are reading the irqs from the second level irq chip, So this patch fixes this issue by adding support to use first level PMIC GPIO irq.

[PATCH v2 7/8] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

From: Kuppuswamy Sathyanarayanan Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to

[PATCH v2 6/8] mfd: intel_soc_pmic_bxtwc: utilize devm_* functions in driver probe

From: Kuppuswamy Sathyanarayanan Cleanup the resource allocation/free code in probe function by using devm_* calls. Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/mfd/intel_soc_pmic_bxtwc.c | 54

Re: [PATCH v1 1/2] gpio: gpio-wcove: fix GPIO irq status mask

SK) << 7); I would leave this on one line despite 80 characters limit (actually how long is it?). It comes to 84 characters. Should I leave it as it is ? -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v1 6/7] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

map_irq_chip_data *irq_chip_data; struct regmap_irq_chip_data *irq_chip_data_level2; struct regmap_irq_chip_data *irq_chip_data_tmu; + struct regmap_irq_chip_data *irq_chip_data_bcu; + struct regmap_irq_chip_data *irq_chip_data_adc; + struct regmap_irq_chip_data *irq_chip_data_chgr; + struct regmap_irq_chip_data *irq_chip_data_crit; struct device *dev; }; -- Sathyanarayanan Kuppuswamy Android kernel developer

[PATCH v1 1/2] gpio: gpio-wcove: fix GPIO irq status mask

From: Kuppuswamy Sathyanarayanan According to Whiskey cove PMIC spec, bit 7 of GPIOIRQ0_REG belongs to battery IO. So we should skip this bit when checking for GPIO irq pending status. Otherwise, wcove_gpio_irq_handler() might go into the infinite loop

[PATCH v1 2/2] gpio: gpio-wcove: fix irq pending status bit width

From: Kuppuswamy Sathyanarayanan Whiskey cove PMIC has three GPIO banks with total number of 13 GPIO pins. But when checking for the pending status, for_each_set_bit() uses bit width of 7 and hence it only checks the status for first 7 GPIO pins

Re: [RFC v1 3/6] platform/x86: intel_pmc_ipc: Use MFD framework to create dependent devices

ev_err(>dev, "Failed to create sysfs group %d\n", ret); - goto unregister_devices; + return ret; } ipcdev.has_gcr_regs = true; return 0; - -unregister_devices: - platform_device_unregister(ipcdev.tco_dev); - platform_device_unregister(ipcdev.punit_dev); - platform_device_unregister(ipcdev.telemetry_dev); - - return ret; } static int ipc_plat_remove(struct platform_device *pdev) { sysfs_remove_group(>dev.kobj, _ipc_group); - platform_device_unregister(ipcdev.tco_dev); - platform_device_unregister(ipcdev.punit_dev); - platform_device_unregister(ipcdev.telemetry_dev); ipcdev.dev = NULL; + return 0; } -- 2.7.4 -- Sathyanarayanan Kuppuswamy Linux kernel developer

Re: [PATCH v1 1/1] watchdog: iTCO_wdt: Move update_no_reboot_bit() out of atomic context

nsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Sathyanarayanan Kuppuswamy Linux kernel developer

[PATCH v3 1/1] mux: consumer: Add dummy functions for !CONFIG_MULTIPLEXER case

From: Kuppuswamy Sathyanarayanan Add dummy functions to avoid compile time issues when CONFIG_MULTIPLEXER is not enabled. Signed-off-by: Kuppuswamy Sathyanarayanan --- include/linux/mux/consumer.h | 42

[PATCH v1 1/1] mux: consumer: Add dummy functions for !CONFIG_MULTIPLEXER case

From: Kuppuswamy Sathyanarayanan Add dummy functions to avoid compile time issues when CONFIG_MULTIPLEXER is not enabled. Signed-off-by: Kuppuswamy Sathyanarayanan --- include/linux/mux/consumer.h | 38

[PATCH v2 1/1] mux: mux-core: Add NULL check for dev->of_node

From: Kuppuswamy Sathyanarayanan If dev->of_node is NULL, then calling mux_control_get() function can lead to NULL pointer exception. So adding a NULL check for dev->of_node. Signed-off-by: Kuppuswamy Sathyanarayanan

[PATCH v1 1/1] mux: mux-core: Add NULL check for dev->of_node

From: Kuppuswamy Sathyanarayanan If dev->of_node is NULL, then calling mux_control_get() function can lead to NULL pointer exception. So adding a NULL check for dev->of_node. Signed-off-by: Kuppuswamy Sathyanarayanan

Re: [PATCH v1 1/1] gpio: gpio-crystalcove: Skip IRQ CTRL register update for virtual GPIOs

Hi Hans, Do you have any comments on this patch ? It kind of fixes your patch, so would prefer to get your comments. On 06/15/2017 02:45 PM, sathyanarayanan kuppuswamy wrote: Hi Andy, On 06/15/2017 02:19 AM, Andy Shevchenko wrote: On Thu, Jun 15, 2017 at 2:21 AM, <sathyanarayanan.kupp

Re: [PATCH v1 1/1] mux: Add new API to get mux_control ref by device name.

to what the mux core should do. Or something like that. Let me go through it and get back to you. Cheers, peda -- Sathyanarayanan Kuppuswamy Linux kernel developer

Re: [PATCH v2 1/1] mux: mux-core: Add NULL check for dev->of_node

t; + if (!np) + return ERR_PTR(-ENODEV); + if (mux_name) { index = of_property_match_string(np, "mux-control-names", mux_name); -- Sathyanarayanan Kuppuswamy Linux kernel developer

[PATCH v1 1/1] mux: mux-core: Unregister mux_class in mux_exit()

From: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/mux/mux-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mux/mux-core.c

[PATCH v1 1/1] mux: Add new API to get mux_control ref by device name.

From: Kuppuswamy Sathyanarayanan Currently this driver only provides a single API, mux_control_get() to get mux_control reference based on mux_name, and also this API has tight dependency on device tree node. For devices, that does not use device tree,

[PATCH v2 1/1] mux: consumer: Add dummy functions for !CONFIG_MULTIPLEXER case

From: Kuppuswamy Sathyanarayanan Add dummy functions to avoid compile time issues when CONFIG_MULTIPLEXER is not enabled. Signed-off-by: Kuppuswamy Sathyanarayanan --- include/linux/mux/consumer.h | 38

[PATCH v1 1/1] watchdog: iTCO_wdt: Move update_no_reboot_bit() out of atomic context

From: Kuppuswamy Sathyanarayanan In iTCO_wdt_start() and iTCO_wdt_stop() functions, update_no_reboot_bit() call has been made within io_lock spin lock context. But if the update_no_reboot_bit() function is implemented by chipset/PMC driver then we

Re: [PATCH v2 1/1] gpio: gpio-wcove: Fix GPIO control register offset calculation

ve sent, I have tested it in Apollo lake reference board and also sent this patch to testing team for verification. Only after confirming that it works, I sent this patch to upstream for review. Hans, do you have anything to add / comment on this? -- Sathyanarayanan Kuppuswamy Linux kernel developer

Re: [PATCH v2 1/1] gpio: gpio-wcove: Fix GPIO control register offset calculation

e mentioned violation of ACPI which is not your fault. Thanks. I have also tested it and it seem to run fine. Without this fix, I am getting Interrupt storms in USB Type-C device. Would you mind signing yourself up as maintainer in the MAINTAINERS file for this driver? I don't mind. I can sign-up for it. Yours, Linus Walleij -- Sathyanarayanan Kuppuswamy Linux kernel developer

Re: [PATCH v2 1/1] gpio: gpio-wcove: Fix GPIO control register offset calculation

le should really be renamed to drivers/gpio/gpio-bxt-wcove.c I also agree with this point. If Linus is also fine with rename, I can submit a patch for it. And future patches should also use gpio-bxt-wcove in their subject. With that said, the patch looks good to me. Regards, Hans -- Sathyanarayanan Kuppuswamy Linux kernel developer

[PATCH 1/1] MAINTAINERS: Add entry for Whiskey Cove PMIC GPIO driver

From: Kuppuswamy Sathyanarayanan Added maintainer info for Whiskey Cove PMIC GPIO driver. Signed-off-by: Kuppuswamy Sathyanarayanan --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git

Re: [PATCH 1/1] MAINTAINERS: Add entry for Whiskey Cove PMIC GPIO driver

and create a new one for CHT (if required). Let me know your comments. -- Sathyanarayanan Kuppuswamy Linux kernel developer

Re: [PATCH v2 8/8] platform: x86: intel_bxtwc_tmu: remove first level irq unmask

don't make a mess for Linus. Given the interdependencies, I'd recommend someone pull the series in as a whole - maybe into MFD? Lee, do you have a preference? -- Sathyanarayanan Kuppuswamy Android kernel developer

Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset

00 #define PLAT_RESOURCE_GCR_SIZE 0x1000 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 -- 2.7.4 -- Sathyanarayanan Kuppuswamy Android kernel developer

[PATCH v2 1/1] gpio: gpio-wcove: fix GPIO IRQ status mask

From: Kuppuswamy Sathyanarayanan According to Whiskey Cove PMIC spec, bit 7 of GPIOIRQ0_REG belongs to battery IO. So we should skip this bit when checking for GPIO IRQ pending status. Otherwise, wcove_gpio_irq_handler() might go into the infinite loop

[RFC v1 2/6] platform/x86: intel_pmc_ipc: Use devm_* calls in driver probe

From: Kuppuswamy Sathyanarayanan This patch cleans up unnecessary free/alloc calls in this driver by using devm_* calls. Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/platform/x86/intel_pmc_ipc.c

[RFC v1 1/6] platform/x86: intel_pmc_ipc: Fix error handling in ipc_pci_probe()

From: Kuppuswamy Sathyanarayanan This patch adds proper error handling for failure cases in ipc_pci_probe() function. Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/platform/x86/intel_pmc_ipc.c |

[RFC v1 0/6] PMC/PUNIT IPC driver cleanup

From: Kuppuswamy Sathyanarayanan Hi All, Currently intel_pmc_ipc.c, intel_punit_ipc.c, intel_scu_ipc.c drivers implements the same IPC features. This code duplication could be avoided if we implement the IPC driver as a single library and let custom

[RFC v1 6/6] platform/x86: intel_pmc_ipc: Use generic Intel IPC device calls

From: Kuppuswamy Sathyanarayanan Removed redundant IPC helper functions and refactored the intel_pmc_ipc_simple_command() and intel_pmc_ipc_command() functions to use generic IPC device driver APIs. Signed-off-by: Kuppuswamy Sathyanarayanan

[RFC v1 4/6] platform: x86: Add generic Intel IPC driver

From: Kuppuswamy Sathyanarayanan Currently intel_scu_ipc.c, intel_pmc_ipc.c and intel_punit_ipc.c redundantly implements the same IPC features and has lot of code duplication between them. This driver addresses this issue by grouping the common IPC

[RFC v1 5/6] platform/x86: intel_punit_ipc: Use generic intel ipc device calls

From: Kuppuswamy Sathyanarayanan Removed redundant IPC helper functions and refactored the intel_punit_ipc_simple_command() and intel_punit_ipc_command() functions to use eneric IPC device driver APIs. Signed-off-by: Kuppuswamy Sathyanarayanan

[RFC v1 3/6] platform/x86: intel_pmc_ipc: Use MFD framework to create dependent devices

From: Kuppuswamy Sathyanarayanan Currently, we have lot of repetitive code in dependent device resource allocation and device creation handling code. This logic can be improved if we use MFD framework for dependent device creation. This patch adds this

[PATCH v2 1/1] gpio: gpio-wcove: Fix GPIO control register offset calculation

From: Kuppuswamy Sathyanarayanan According to Whiskey Cove PMIC GPIO controller specification, for GPIO pins 0-12, GPIO input and output register control address range from, 0x4e44-0x4e50 for GPIO outputs control register 0x4e51-0x4e5d for GPIO input

Re: [PATCH v2 3/8] thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq

q_chip_data_level2; + regmap_irq_chip = pmic->irq_chip_data; pmic_irq_count = 0; while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) { -- Sathyanarayanan Kuppuswamy Linux kernel developer

[PATCH v3 5/8] gpio: gpio-wcove: use first level PMIC GPIO irq

From: Kuppuswamy Sathyanarayanan PMIC mfd driver only exports first level irq for GPIO device. But currently we are reading the irqs from the second level irq chip, So this patch fixes this issue by adding support to use first level PMIC GPIO irq.

[PATCH v3 7/8] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

From: Kuppuswamy Sathyanarayanan Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to

[PATCH v3 1/8] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index

From: Kuppuswamy Sathyanarayanan TMU interrupts are registered as a separate interrupt chip, and hence it should start its interrupt index(BXTWC_TMU_IRQ) number from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum bxtwc_irqs_level2 and its

[PATCH v3 2/8] mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs

From: Kuppuswamy Sathyanarayanan Since all second level thermal irqs are consumed by the same device(bxt_wcove_thermal), there is no need to expose them as separate interrupts. We can just export only the first level irqs for thermal and let the

[PATCH v3 8/8] platform: x86: intel_bxtwc_tmu: remove first level irq unmask

From: Kuppuswamy Sathyanarayanan Currently in WCOVE PMIC mfd driver, all second level irq chips are chained to the respective first level irqs. So there is no need for explicitly unmasking the first level irq in this driver. This patches removes this

[PATCH v3 4/8] mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device

From: Kuppuswamy Sathyanarayanan Currently all PMIC GPIO domain irqs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO irq(BXTWC_GPIO_LVL1_IRQ) as an

[PATCH v3 3/8] thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq

From: Kuppuswamy Sathyanarayanan PMIC mfd driver only exports first level irq for thermal device. But currently we are reading the irqs from the second level irq chip, So this patch fixes this issue by adding support to use first level PMIC thermal

[PATCH v3 6/8] mfd: intel_soc_pmic_bxtwc: utilize devm_* functions in driver probe

From: Kuppuswamy Sathyanarayanan Cleanup the resource allocation/free code in probe function by using devm_* calls. Signed-off-by: Kuppuswamy Sathyanarayanan Acked-for-MFD-by: Lee Jones

[PATCH v1 1/1] mux: mux-intel-usb: Add Intel USB Multiplexer driver

From: Kuppuswamy Sathyanarayanan In some Intel SOCs, a single USB port is shared between USB device and host controller and an internal mux is used to control the selection of port by host/device controllers. This driver adds support for the USB

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