In case of xspi work in busy condition, may send bytes failed.
Add one bytes delay
Signed-off-by: sxauwsk <sxau...@163.com>
Signed-off-by: guojian <guoj...@innoinstrument.net>
Signed-off-by: wangshikai <wangshi...@inno-instrument.cn>
---
drivers/spi/spi-cadence.c |6 ++
In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more
My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;
Signed-off-by: sxauwsk <sxau...@163.com>
-by: sxauwsk <sxau...@163.com>
---
drivers/spi/spi-cadence.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 5c9516a..9694042 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -313,6 +313,14 @@
In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more
My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;
Signed-off-by: sxauwsk <sxau...@163.
In case of xspi work in busy condition, may send bytes failed.
Add one bytes delay
Signed-off-by: sxauwsk
Signed-off-by: guojian
Signed-off-by: wangshikai
---
drivers/spi/spi-cadence.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi
In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more
My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;
Signed-off-by: sxauwsk
Signed-off-by: guojian
-by: sxauwsk
---
drivers/spi/spi-cadence.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 5c9516a..9694042 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -313,6 +313,14 @@ static void
In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more
My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;
Signed-off-by: sxauwsk
---
drivers/spi/spi
-by: sxauwsk
---
drivers/i2c/busses/i2c-cadence.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index b13605718291..e10048d7524a 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c
-by: sxauwsk
Signed-off-by: Shubhrajyoti Datta
---
drivers/i2c/busses/i2c-cadence.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index b13605718291..595b0d56ff1a 100644
--- a/drivers/i2c/busses
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