[GIT PULL] clk: changes for 3.20
The following changes since commit e36f014edff70fc02b3d3d79cead1d58f289332e:
Linux 3.19-rc7 (2015-02-01 20:07:21 -0800)
are available in the git repository at:
https://git.linaro.org/people/mike.turquette/linux.git tags/clk-for-linus-3.20
for you to fetch changes up to ec02ace8ca0a50eef430d3676de5c5fa978b0e29:
clk: Only recalculate the rate if needed (2015-02-19 19:29:19 -0800)
The clock framework changes for 3.20 contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
Andrew Bresticker (1):
clk: tegra: SDMMC controllers are on APB
Arnd Bergmann (1):
clk: omap: compile legacy omap3 clocks conditionally
Chanwoo Choi (4):
clk: samsung: Change the return value of samsung_cmu_register_one()
clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos4: Add divider clock id for memory bus frequency
Chen-Yu Tsai (10):
clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
ARM: dts: sun6i: Unify ahb1 clock nodes
ARM: dts: sun8i: Unify ahb1 clock nodes
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
clk: sunxi: Fix factor clocks usage for sun9i core clocks
clk: sunxi: Propagate rate changes to parent for mux clocks
clk: sunxi: Add a common setup function for mmc module clocks
clk: sunxi: Add mod0 and mmc module clock support for A80
clk: sunxi: Add driver for A80 MMC config clocks/resets
Doug Anderson (2):
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
Emil Medve (9):
clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT
clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY
clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT
clk: qoriq: Fix checkpatch type OOM_MESSAGE
clk: qoriq: Make local symbol 'static'
clk: qoriq: Replace kzalloc() with kmalloc()
clk: qoriq: Use pr_fmt()
powerpc/corenet: Enable CLK_QORIQ
clk: qoriq: Add support for the platform PLL
Geert Uytterhoeven (2):
clk: shmobile: div6: Avoid changing divisor in .disable()
clk: shmobile: div6: Avoid division by zero in .round_rate()
Hans de Goede (4):
clk: sunxi: Give sunxi_factors_register a registers parameter
clk: sunxi: Make the mod0 clk driver also a platform driver
clk: sunxi: rewrite sun9i_a80_get_pll4_factors()
sunxi: clk: Set sun6i-pll1 n_start = 1
Heiko Stuebner (3):
clk: rockchip: add id for watchdog pclk on rk3288
Merge branch 'v3.20-clk/new-ids' into v3.20-clk/next
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
Hisashi Nakamura (1):
clk: shmobile: Add r8a7793 support
Huang Lin (1):
clk: rockchip: add clock IDs for the PVTM clocks
Javier Martinez Canillas (3):
clk: Don't dereference parent clock if is NULL
clk: Add __clk_hw_set_clk helper function
clk: Replace explicit clk assignment with __clk_hw_set_clk
Josh Cartwright (1):
clk: qcom: Add support for regmap divider clocks
Kever Yang (2):
clk: rockchip: add clock ID for usbphy480m_src
clk: rockchip: use the clock ID for usbphy480m_src
Kevin Hao (2):
powerpc: call of_clk_init() from time_init()
clk: ppc-corenet: fix section mismatch warning
Krzysztof Kozlowski (2):
clk: Add clk_unregister_{divider, gate, mux} to close memory leak
clk: exynos-audss: Fix memory leak on driver unbind or probe failure
Mark Zhang (1):
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
Max Filippov (1):
clk: TI CDCE706 clock synthesizer driver
Maxime Ripard (5):
clk: sunxi: Rework MMC phase clocks
ARM: sunxi: dt: Add sample and output mmc clocks
mmc: sunxi: Convert MMC driver to the standard clock phase API
clk: sunxi: Remove custom phase function
clk: Export phase functions
[GIT PULL] clk: changes for 3.20
The following changes since commit e36f014edff70fc02b3d3d79cead1d58f289332e:
Linux 3.19-rc7 (2015-02-01 20:07:21 -0800)
are available in the git repository at:
https://git.linaro.org/people/mike.turquette/linux.git tags/clk-for-linus-3.20
for you to fetch changes up to ec02ace8ca0a50eef430d3676de5c5fa978b0e29:
clk: Only recalculate the rate if needed (2015-02-19 19:29:19 -0800)
The clock framework changes for 3.20 contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
Andrew Bresticker (1):
clk: tegra: SDMMC controllers are on APB
Arnd Bergmann (1):
clk: omap: compile legacy omap3 clocks conditionally
Chanwoo Choi (4):
clk: samsung: Change the return value of samsung_cmu_register_one()
clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos4: Add divider clock id for memory bus frequency
Chen-Yu Tsai (10):
clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
ARM: dts: sun6i: Unify ahb1 clock nodes
ARM: dts: sun8i: Unify ahb1 clock nodes
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
clk: sunxi: Fix factor clocks usage for sun9i core clocks
clk: sunxi: Propagate rate changes to parent for mux clocks
clk: sunxi: Add a common setup function for mmc module clocks
clk: sunxi: Add mod0 and mmc module clock support for A80
clk: sunxi: Add driver for A80 MMC config clocks/resets
Doug Anderson (2):
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
Emil Medve (9):
clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT
clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY
clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT
clk: qoriq: Fix checkpatch type OOM_MESSAGE
clk: qoriq: Make local symbol 'static'
clk: qoriq: Replace kzalloc() with kmalloc()
clk: qoriq: Use pr_fmt()
powerpc/corenet: Enable CLK_QORIQ
clk: qoriq: Add support for the platform PLL
Geert Uytterhoeven (2):
clk: shmobile: div6: Avoid changing divisor in .disable()
clk: shmobile: div6: Avoid division by zero in .round_rate()
Hans de Goede (4):
clk: sunxi: Give sunxi_factors_register a registers parameter
clk: sunxi: Make the mod0 clk driver also a platform driver
clk: sunxi: rewrite sun9i_a80_get_pll4_factors()
sunxi: clk: Set sun6i-pll1 n_start = 1
Heiko Stuebner (3):
clk: rockchip: add id for watchdog pclk on rk3288
Merge branch 'v3.20-clk/new-ids' into v3.20-clk/next
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
Hisashi Nakamura (1):
clk: shmobile: Add r8a7793 support
Huang Lin (1):
clk: rockchip: add clock IDs for the PVTM clocks
Javier Martinez Canillas (3):
clk: Don't dereference parent clock if is NULL
clk: Add __clk_hw_set_clk helper function
clk: Replace explicit clk assignment with __clk_hw_set_clk
Josh Cartwright (1):
clk: qcom: Add support for regmap divider clocks
Kever Yang (2):
clk: rockchip: add clock ID for usbphy480m_src
clk: rockchip: use the clock ID for usbphy480m_src
Kevin Hao (2):
powerpc: call of_clk_init() from time_init()
clk: ppc-corenet: fix section mismatch warning
Krzysztof Kozlowski (2):
clk: Add clk_unregister_{divider, gate, mux} to close memory leak
clk: exynos-audss: Fix memory leak on driver unbind or probe failure
Mark Zhang (1):
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
Max Filippov (1):
clk: TI CDCE706 clock synthesizer driver
Maxime Ripard (5):
clk: sunxi: Rework MMC phase clocks
ARM: sunxi: dt: Add sample and output mmc clocks
mmc: sunxi: Convert MMC driver to the standard clock phase API
clk: sunxi: Remove custom phase function
clk: Export phase functions
