subject:"\[PATCH\] arm64\: dts\: add zx296718's topcrm node"

Re: [PATCH] arm64: dts: add zx296718's topcrm node

2016-11-30 Thread Jun Nie

2016-11-30 15:33 GMT+08:00 Baoyou Xie :
> Enable topcrm clock node for zx296718, which is used for
> CPU's frequency change.

Please follow general rule, such as
arm64: dts: zx: brief title of your changes

>
> Furthermore, this patch adds the CPU clock phandle in CPU's node
> and uses operating-points-v2 to register operating points.
>
> So it can be used by cpufreq-dt driver.

Suggest to split clock nodes and cpu-freq nodes changes into different patches.

>
> Signed-off-by: Baoyou Xie 
> ---
>  arch/arm64/boot/dts/zte/zx296718.dtsi | 48 
> +++
>  1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi 
> b/arch/arm64/boot/dts/zte/zx296718.dtsi
> index 6b239a3..f9eb37d 100644
> --- a/arch/arm64/boot/dts/zte/zx296718.dtsi
> +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
> @@ -44,6 +44,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  / {
> compatible = "zte,zx296718";
> @@ -81,6 +82,8 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x0>;
> enable-method = "psci";
> +   clocks = < A53_GATE>;
> +   operating-points-v2 = <_opp>;
> };
>
> cpu1: cpu@1 {
> @@ -88,6 +91,7 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x1>;
> enable-method = "psci";
> +   operating-points-v2 = <_opp>;
> };
>
> cpu2: cpu@2 {
> @@ -95,6 +99,7 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x2>;
> enable-method = "psci";
> +   operating-points-v2 = <_opp>;
> };
>
> cpu3: cpu@3 {
> @@ -102,6 +107,43 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x3>;
> enable-method = "psci";
> +   operating-points-v2 = <_opp>;
> +   };
> +   };
> +
> +   cluster0_opp: opp_table0 {
> +   compatible = "operating-points-v2";
> +   opp-shared;
> +
> +   opp@10 {
> +   opp-hz = /bits/ 64 <5>;

Why frequency in opp name differ with opp-hz value?

> +   opp-microvolt = <857000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@11 {
> +   opp-hz = /bits/ 64 <64800>;
> +   opp-microvolt = <857000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@12 {
> +   opp-hz = /bits/ 64 <8>;
> +   opp-microvolt = <882000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@13 {
> +   opp-hz = /bits/ 64 <10>;
> +   opp-microvolt = <892000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@14 {
> +   opp-hz = /bits/ 64 <118800>;
> +   opp-microvolt = <1009000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@15 {
> +   opp-hz = /bits/ 64 <131200>;
> +   opp-microvolt = <1052000>;
> +   clock-latency-ns = <50>;
> };

I did not see frequency 15 or 131200 in clock drivers for
A53. Please confirm whether clock driver need update or your need
revise your patch.

> };
>
> @@ -279,6 +321,12 @@
> dma-requests = <32>;
> };
>
> +   topcrm: clock-controller@01461000 {

Removing heading 0 in address of name.

> +   compatible = "zte,zx296718-topcrm";
> +   reg = <0x01461000 0x1000>;
> +   #clock-cells = <1>;
> +   };
> +
> sysctrl: sysctrl@1463000 {
> compatible = "zte,zx296718-sysctrl", "syscon";
> reg = <0x1463000 0x1000>;
> --
> 2.7.4
>

Re: [PATCH] arm64: dts: add zx296718's topcrm node

2016-11-30 Thread Jun Nie

2016-11-30 15:33 GMT+08:00 Baoyou Xie :
> Enable topcrm clock node for zx296718, which is used for
> CPU's frequency change.

Please follow general rule, such as
arm64: dts: zx: brief title of your changes

>
> Furthermore, this patch adds the CPU clock phandle in CPU's node
> and uses operating-points-v2 to register operating points.
>
> So it can be used by cpufreq-dt driver.

Suggest to split clock nodes and cpu-freq nodes changes into different patches.

>
> Signed-off-by: Baoyou Xie 
> ---
>  arch/arm64/boot/dts/zte/zx296718.dtsi | 48 
> +++
>  1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi 
> b/arch/arm64/boot/dts/zte/zx296718.dtsi
> index 6b239a3..f9eb37d 100644
> --- a/arch/arm64/boot/dts/zte/zx296718.dtsi
> +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
> @@ -44,6 +44,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  / {
> compatible = "zte,zx296718";
> @@ -81,6 +82,8 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x0>;
> enable-method = "psci";
> +   clocks = < A53_GATE>;
> +   operating-points-v2 = <_opp>;
> };
>
> cpu1: cpu@1 {
> @@ -88,6 +91,7 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x1>;
> enable-method = "psci";
> +   operating-points-v2 = <_opp>;
> };
>
> cpu2: cpu@2 {
> @@ -95,6 +99,7 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x2>;
> enable-method = "psci";
> +   operating-points-v2 = <_opp>;
> };
>
> cpu3: cpu@3 {
> @@ -102,6 +107,43 @@
> compatible = "arm,cortex-a53","arm,armv8";
> reg = <0x0 0x3>;
> enable-method = "psci";
> +   operating-points-v2 = <_opp>;
> +   };
> +   };
> +
> +   cluster0_opp: opp_table0 {
> +   compatible = "operating-points-v2";
> +   opp-shared;
> +
> +   opp@10 {
> +   opp-hz = /bits/ 64 <5>;

Why frequency in opp name differ with opp-hz value?

> +   opp-microvolt = <857000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@11 {
> +   opp-hz = /bits/ 64 <64800>;
> +   opp-microvolt = <857000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@12 {
> +   opp-hz = /bits/ 64 <8>;
> +   opp-microvolt = <882000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@13 {
> +   opp-hz = /bits/ 64 <10>;
> +   opp-microvolt = <892000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@14 {
> +   opp-hz = /bits/ 64 <118800>;
> +   opp-microvolt = <1009000>;
> +   clock-latency-ns = <50>;
> +   };
> +   opp@15 {
> +   opp-hz = /bits/ 64 <131200>;
> +   opp-microvolt = <1052000>;
> +   clock-latency-ns = <50>;
> };

I did not see frequency 15 or 131200 in clock drivers for
A53. Please confirm whether clock driver need update or your need
revise your patch.

> };
>
> @@ -279,6 +321,12 @@
> dma-requests = <32>;
> };
>
> +   topcrm: clock-controller@01461000 {

Removing heading 0 in address of name.

> +   compatible = "zte,zx296718-topcrm";
> +   reg = <0x01461000 0x1000>;
> +   #clock-cells = <1>;
> +   };
> +
> sysctrl: sysctrl@1463000 {
> compatible = "zte,zx296718-sysctrl", "syscon";
> reg = <0x1463000 0x1000>;
> --
> 2.7.4
>

[PATCH] arm64: dts: add zx296718's topcrm node

2016-11-29 Thread Baoyou Xie

Enable topcrm clock node for zx296718, which is used for
CPU's frequency change.

Furthermore, this patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Signed-off-by: Baoyou Xie 
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 48 +++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi 
b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 6b239a3..f9eb37d 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -44,6 +44,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "zte,zx296718";
@@ -81,6 +82,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+   clocks = < A53_GATE>;
+   operating-points-v2 = <_opp>;
};
 
cpu1: cpu@1 {
@@ -88,6 +91,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu2: cpu@2 {
@@ -95,6 +99,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu3: cpu@3 {
@@ -102,6 +107,43 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
+   };
+   };
+
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@10 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@11 {
+   opp-hz = /bits/ 64 <64800>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@12 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <882000>;
+   clock-latency-ns = <50>;
+   };
+   opp@13 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <892000>;
+   clock-latency-ns = <50>;
+   };
+   opp@14 {
+   opp-hz = /bits/ 64 <118800>;
+   opp-microvolt = <1009000>;
+   clock-latency-ns = <50>;
+   };
+   opp@15 {
+   opp-hz = /bits/ 64 <131200>;
+   opp-microvolt = <1052000>;
+   clock-latency-ns = <50>;
};
};
 
@@ -279,6 +321,12 @@
dma-requests = <32>;
};
 
+   topcrm: clock-controller@01461000 {
+   compatible = "zte,zx296718-topcrm";
+   reg = <0x01461000 0x1000>;
+   #clock-cells = <1>;
+   };
+
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
-- 
2.7.4

[PATCH] arm64: dts: add zx296718's topcrm node

2016-11-29 Thread Baoyou Xie

Enable topcrm clock node for zx296718, which is used for
CPU's frequency change.

Furthermore, this patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Signed-off-by: Baoyou Xie 
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 48 +++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi 
b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 6b239a3..f9eb37d 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -44,6 +44,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "zte,zx296718";
@@ -81,6 +82,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+   clocks = < A53_GATE>;
+   operating-points-v2 = <_opp>;
};
 
cpu1: cpu@1 {
@@ -88,6 +91,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu2: cpu@2 {
@@ -95,6 +99,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu3: cpu@3 {
@@ -102,6 +107,43 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
+   };
+   };
+
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@10 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@11 {
+   opp-hz = /bits/ 64 <64800>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@12 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <882000>;
+   clock-latency-ns = <50>;
+   };
+   opp@13 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <892000>;
+   clock-latency-ns = <50>;
+   };
+   opp@14 {
+   opp-hz = /bits/ 64 <118800>;
+   opp-microvolt = <1009000>;
+   clock-latency-ns = <50>;
+   };
+   opp@15 {
+   opp-hz = /bits/ 64 <131200>;
+   opp-microvolt = <1052000>;
+   clock-latency-ns = <50>;
};
};
 
@@ -279,6 +321,12 @@
dma-requests = <32>;
};
 
+   topcrm: clock-controller@01461000 {
+   compatible = "zte,zx296718-topcrm";
+   reg = <0x01461000 0x1000>;
+   #clock-cells = <1>;
+   };
+
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
-- 
2.7.4

Re: [PATCH] arm64: dts: add zx296718's topcrm node

Re: [PATCH] arm64: dts: add zx296718's topcrm node

[PATCH] arm64: dts: add zx296718's topcrm node

[PATCH] arm64: dts: add zx296718's topcrm node

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