subject:"\[PATCH\] clk\: Add driver for the si544 clock generator chip"

Re: [PATCH] clk: Add driver for the si544 clock generator chip

2018-03-16 Thread Stephen Boyd

Quoting Mike Looijmans (2018-03-13 01:43:59)
> diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt 
> b/Documentation/devicetree/bindings/clock/silabs,si544.txt
> new file mode 100644
> index 000..eec1787
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/silabs,si544.txt
> @@ -0,0 +1,25 @@
> +Binding for Silicon Labs 544 programmable I2C clock generator.
> +
> +Reference
> +This binding uses the common clock binding[1]. Details about the device can 
> be
> +found in the datasheet[2].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Si544 datasheet
> +https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf

Can this reference stuff go to the bottom of this document?

> +
> +Required properties:
> + - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" 
> according
> +   to the speed grade of the chip.
> + - reg: I2C device address.
> + - #clock-cells: From common clock bindings: Shall be 0.
> +
> +Optional properties:
> + - clock-output-names: From common clock bindings. Recommended to be "si544".
> +
> +Example:
> +   si544: clock-generator@55 {

I'm not sure clock-generator is in the list of node names, but we have
some of these already so alright.

> +   reg = <0x55>;
> +   #clock-cells = <0>;
> +   compatible = "silabs,si544b";
> +   };
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 98ce9fc..5c7dc8e 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -91,6 +91,16 @@ config COMMON_CLK_SI514
>   This driver supports the Silicon Labs 514 programmable clock
>   generator.
>  
> +config COMMON_CLK_SI544
> +   tristate "Clock driver for SiLabs 544 devices"
> +   depends on I2C
> +   depends on OF

Does it depend on anything in OF to build?

> +   select REGMAP_I2C
> +   help
> +   ---help---
> + This driver supports the Silicon Labs 544 programmable clock
> + generator.
> +
>  config COMMON_CLK_SI570
> tristate "Clock driver for SiLabs 570 and compatible devices"
> depends on I2C
> diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
> new file mode 100644
> index 000..1947e48
> --- /dev/null
> +++ b/drivers/clk/clk-si544.c
> @@ -0,0 +1,421 @@
> +/*
> + * Driver for Silicon Labs Si544 Programmable Oscillator
> + *
> + * Copyright (C) 2018 Topic Embedded Products
> + *
> + * Author: Mike Looijmans 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.

Can we have SPDX style license here?

> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* I2C registers (decimal as in datasheet) */

Heh.

> +#define SI544_REG_CONTROL  7
> +#define SI544_REG_OE_STATE 17
> +#define SI544_REG_HS_DIV   23
> +#define SI544_REG_LS_HS_DIV24
> +#define SI544_REG_FBDIV0   26
> +#define SI544_REG_FBDIV8   27
> +#define SI544_REG_FBDIV16  28
> +#define SI544_REG_FBDIV24  29
> +#define SI544_REG_FBDIV32  30
> +#define SI544_REG_FBDIV40  31
> +#define SI544_REG_FCAL_OVR 69
> +#define SI544_REG_ADPLL_DELTA_M0   231
> +#define SI544_REG_ADPLL_DELTA_M8   232
> +#define SI544_REG_ADPLL_DELTA_M16  233
> +#define SI544_REG_PAGE_SELECT  255
> +
> +/* Register values */
> +#define SI544_CONTROL_RESETBIT(7)
> +#define SI544_CONTROL_MS_ICAL2 BIT(3)
> +
> +#define SI544_OE_STATE_ODC_OE  BIT(0)
> +
> +/* Max freq depends on speed grade */
> +#define SI544_MIN_FREQ 20U
> +
> +/* Si544 Internal oscilator runs at 55.05 MHz */
> +#define FXO  5505U
> +
> +/* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
> +#define FVCO_MIN   108ULL
> +
> +#define HS_DIV_MAX 2046
> +#define HS_DIV_MAX_ODD 33
> +
> +enum si544_speed_grade {
> +   si544a,
> +   si544b,
> +   si544c,
> +};
> +
> +struct clk_si544 {
> +   struct clk_hw hw;
> +   struct regmap *regmap;
> +   struct i2c_client *i2c_client;
> +   enum si544_speed_grade speed_grade;
> +};
> +#define to_clk_si544(_hw)  container_of(_hw, struct clk_si544, hw)
> +
> +/* Multiplier/divider settings */
> +struct clk_si544_muldiv {
> +   u32 fb_div_frac;  /* Integer part of feedback divider (32 bits) */
> +   u16 fb_div_int;  /* Fractional part of feedback divider (11 bits) */
> +   u16 hs_div; /* 1st divider, 5..2046, must be even when >33 */
> +

Re: [PATCH] clk: Add driver for the si544 clock generator chip

2018-03-16 Thread Stephen Boyd

Quoting Mike Looijmans (2018-03-13 01:43:59)
> diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt 
> b/Documentation/devicetree/bindings/clock/silabs,si544.txt
> new file mode 100644
> index 000..eec1787
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/silabs,si544.txt
> @@ -0,0 +1,25 @@
> +Binding for Silicon Labs 544 programmable I2C clock generator.
> +
> +Reference
> +This binding uses the common clock binding[1]. Details about the device can 
> be
> +found in the datasheet[2].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Si544 datasheet
> +https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf

Can this reference stuff go to the bottom of this document?

> +
> +Required properties:
> + - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" 
> according
> +   to the speed grade of the chip.
> + - reg: I2C device address.
> + - #clock-cells: From common clock bindings: Shall be 0.
> +
> +Optional properties:
> + - clock-output-names: From common clock bindings. Recommended to be "si544".
> +
> +Example:
> +   si544: clock-generator@55 {

I'm not sure clock-generator is in the list of node names, but we have
some of these already so alright.

> +   reg = <0x55>;
> +   #clock-cells = <0>;
> +   compatible = "silabs,si544b";
> +   };
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 98ce9fc..5c7dc8e 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -91,6 +91,16 @@ config COMMON_CLK_SI514
>   This driver supports the Silicon Labs 514 programmable clock
>   generator.
>  
> +config COMMON_CLK_SI544
> +   tristate "Clock driver for SiLabs 544 devices"
> +   depends on I2C
> +   depends on OF

Does it depend on anything in OF to build?

> +   select REGMAP_I2C
> +   help
> +   ---help---
> + This driver supports the Silicon Labs 544 programmable clock
> + generator.
> +
>  config COMMON_CLK_SI570
> tristate "Clock driver for SiLabs 570 and compatible devices"
> depends on I2C
> diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
> new file mode 100644
> index 000..1947e48
> --- /dev/null
> +++ b/drivers/clk/clk-si544.c
> @@ -0,0 +1,421 @@
> +/*
> + * Driver for Silicon Labs Si544 Programmable Oscillator
> + *
> + * Copyright (C) 2018 Topic Embedded Products
> + *
> + * Author: Mike Looijmans 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.

Can we have SPDX style license here?

> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* I2C registers (decimal as in datasheet) */

Heh.

> +#define SI544_REG_CONTROL  7
> +#define SI544_REG_OE_STATE 17
> +#define SI544_REG_HS_DIV   23
> +#define SI544_REG_LS_HS_DIV24
> +#define SI544_REG_FBDIV0   26
> +#define SI544_REG_FBDIV8   27
> +#define SI544_REG_FBDIV16  28
> +#define SI544_REG_FBDIV24  29
> +#define SI544_REG_FBDIV32  30
> +#define SI544_REG_FBDIV40  31
> +#define SI544_REG_FCAL_OVR 69
> +#define SI544_REG_ADPLL_DELTA_M0   231
> +#define SI544_REG_ADPLL_DELTA_M8   232
> +#define SI544_REG_ADPLL_DELTA_M16  233
> +#define SI544_REG_PAGE_SELECT  255
> +
> +/* Register values */
> +#define SI544_CONTROL_RESETBIT(7)
> +#define SI544_CONTROL_MS_ICAL2 BIT(3)
> +
> +#define SI544_OE_STATE_ODC_OE  BIT(0)
> +
> +/* Max freq depends on speed grade */
> +#define SI544_MIN_FREQ 20U
> +
> +/* Si544 Internal oscilator runs at 55.05 MHz */
> +#define FXO  5505U
> +
> +/* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
> +#define FVCO_MIN   108ULL
> +
> +#define HS_DIV_MAX 2046
> +#define HS_DIV_MAX_ODD 33
> +
> +enum si544_speed_grade {
> +   si544a,
> +   si544b,
> +   si544c,
> +};
> +
> +struct clk_si544 {
> +   struct clk_hw hw;
> +   struct regmap *regmap;
> +   struct i2c_client *i2c_client;
> +   enum si544_speed_grade speed_grade;
> +};
> +#define to_clk_si544(_hw)  container_of(_hw, struct clk_si544, hw)
> +
> +/* Multiplier/divider settings */
> +struct clk_si544_muldiv {
> +   u32 fb_div_frac;  /* Integer part of feedback divider (32 bits) */
> +   u16 fb_div_int;  /* Fractional part of feedback divider (11 bits) */
> +   u16 hs_div; /* 1st divider, 5..2046, must be even when >33 */
> +   u8 ls_div_bits; /*

Re: [PATCH] clk: Add driver for the si544 clock generator chip

2018-03-15 Thread Mike Looijmans


On 15-03-18 11:35, Dan Carpenter wrote:

Hi Mike,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.16-rc4]
[also build test WARNING on next-20180314]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Mike-Looijmans/clk-Add-driver-for-the-si544-clock-generator-chip/20180314-122736

smatch warnings:
drivers/clk/clk-si544.c:188 si544_calc_muldiv() warn: impossible condition '((frequency 
* tmp) >= 108) => (0-u32max >= 108)'


Indeed, there's a u64 cast missing.

I've also missed that the hs_div cannot be odd when ls_div is non-zero.

I'll compose a v2 patch fixing these issues.


# 
https://github.com/0day-ci/linux/commit/aba3d3de8751c1457bcf0b75bcc901f289a18426
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout aba3d3de8751c1457bcf0b75bcc901f289a18426
vim +188 drivers/clk/clk-si544.c

aba3d3de Mike Looijmans 2018-03-13  168
aba3d3de Mike Looijmans 2018-03-13  169  /* Calculate divider settings for a 
given frequency */
aba3d3de Mike Looijmans 2018-03-13  170  static int si544_calc_muldiv(struct 
clk_si544_muldiv *settings,
aba3d3de Mike Looijmans 2018-03-13  171 unsigned long frequency)
aba3d3de Mike Looijmans 2018-03-13  172  {
aba3d3de Mike Looijmans 2018-03-13  173 u64 vco;
aba3d3de Mike Looijmans 2018-03-13  174 u32 ls_freq;
aba3d3de Mike Looijmans 2018-03-13  175 u32 tmp;
aba3d3de Mike Looijmans 2018-03-13  176 u8 res;
aba3d3de Mike Looijmans 2018-03-13  177
aba3d3de Mike Looijmans 2018-03-13  178 /* Determine the minimum value 
of LS_DIV and resulting target freq. */
aba3d3de Mike Looijmans 2018-03-13  179 ls_freq = frequency;
aba3d3de Mike Looijmans 2018-03-13  180 settings->ls_div_bits = 0;
aba3d3de Mike Looijmans 2018-03-13  181
aba3d3de Mike Looijmans 2018-03-13  182 if (frequency >= (FVCO_MIN / 
HS_DIV_MAX))
aba3d3de Mike Looijmans 2018-03-13  183 settings->ls_div_bits = 
0;
aba3d3de Mike Looijmans 2018-03-13  184 else {
aba3d3de Mike Looijmans 2018-03-13  185 res = 1;
aba3d3de Mike Looijmans 2018-03-13  186 tmp = 2 * HS_DIV_MAX;
aba3d3de Mike Looijmans 2018-03-13  187 while (tmp <= 
(HS_DIV_MAX * 32)) {
aba3d3de Mike Looijmans 2018-03-13 @188 if ((frequency * 
tmp) >= FVCO_MIN)
aba3d3de Mike Looijmans 2018-03-13  189 break;
aba3d3de Mike Looijmans 2018-03-13  190 ++res;
aba3d3de Mike Looijmans 2018-03-13  191 tmp <<= 1;
aba3d3de Mike Looijmans 2018-03-13  192 }
aba3d3de Mike Looijmans 2018-03-13  193 settings->ls_div_bits = 
res;
aba3d3de Mike Looijmans 2018-03-13  194 ls_freq = frequency << 
res;
aba3d3de Mike Looijmans 2018-03-13  195 }
aba3d3de Mike Looijmans 2018-03-13  196
aba3d3de Mike Looijmans 2018-03-13  197 /* Determine minimum HS_DIV by 
rounding up */
aba3d3de Mike Looijmans 2018-03-13  198 vco = FVCO_MIN + ls_freq - 1;
aba3d3de Mike Looijmans 2018-03-13  199 do_div(vco, ls_freq);
aba3d3de Mike Looijmans 2018-03-13  200 settings->hs_div = vco;
aba3d3de Mike Looijmans 2018-03-13  201 /* round up to even number if 
needed */
aba3d3de Mike Looijmans 2018-03-13  202 if ((settings->hs_div > HS_DIV_MAX_ODD) 
&& (settings->hs_div & 1))
aba3d3de Mike Looijmans 2018-03-13  203 ++settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  204 /* Calculate VCO frequency (in 
10..12GHz range) */
aba3d3de Mike Looijmans 2018-03-13  205 vco = (u64)ls_freq * 
settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  206 /* Calculate the integer part 
of the feedback divider */
aba3d3de Mike Looijmans 2018-03-13  207 tmp = do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  208 settings->fb_div_int = vco;
aba3d3de Mike Looijmans 2018-03-13  209 /* And the fractional bits 
using the remainder */
aba3d3de Mike Looijmans 2018-03-13  210 vco = (u64)tmp << 32;
aba3d3de Mike Looijmans 2018-03-13  211 do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  212 settings->fb_div_frac = vco;
aba3d3de Mike Looijmans 2018-03-13  213
aba3d3de Mike Looijmans 2018-03-13  214 return 0;
aba3d3de Mike Looijmans 2018-03-13  215  }
aba3d3de Mike Looijmans 2018-03-13  216

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation





Kind regards,

Mike Looijmans
System Expert

TOPIC Products
Materiaalweg 4, NL-5681 RJ Best
Postbus 440, NL-5680 AK Best
Telefoon: +31 (0) 499 33 69 79
E-mail: mike.looijm...@topicproducts.com
Website: www.topicproducts.com

Please consider the

Re: [PATCH] clk: Add driver for the si544 clock generator chip

2018-03-15 Thread Mike Looijmans


On 15-03-18 11:35, Dan Carpenter wrote:

Hi Mike,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.16-rc4]
[also build test WARNING on next-20180314]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Mike-Looijmans/clk-Add-driver-for-the-si544-clock-generator-chip/20180314-122736

smatch warnings:
drivers/clk/clk-si544.c:188 si544_calc_muldiv() warn: impossible condition '((frequency 
* tmp) >= 108) => (0-u32max >= 108)'


Indeed, there's a u64 cast missing.

I've also missed that the hs_div cannot be odd when ls_div is non-zero.

I'll compose a v2 patch fixing these issues.


# 
https://github.com/0day-ci/linux/commit/aba3d3de8751c1457bcf0b75bcc901f289a18426
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout aba3d3de8751c1457bcf0b75bcc901f289a18426
vim +188 drivers/clk/clk-si544.c

aba3d3de Mike Looijmans 2018-03-13  168
aba3d3de Mike Looijmans 2018-03-13  169  /* Calculate divider settings for a 
given frequency */
aba3d3de Mike Looijmans 2018-03-13  170  static int si544_calc_muldiv(struct 
clk_si544_muldiv *settings,
aba3d3de Mike Looijmans 2018-03-13  171 unsigned long frequency)
aba3d3de Mike Looijmans 2018-03-13  172  {
aba3d3de Mike Looijmans 2018-03-13  173 u64 vco;
aba3d3de Mike Looijmans 2018-03-13  174 u32 ls_freq;
aba3d3de Mike Looijmans 2018-03-13  175 u32 tmp;
aba3d3de Mike Looijmans 2018-03-13  176 u8 res;
aba3d3de Mike Looijmans 2018-03-13  177
aba3d3de Mike Looijmans 2018-03-13  178 /* Determine the minimum value 
of LS_DIV and resulting target freq. */
aba3d3de Mike Looijmans 2018-03-13  179 ls_freq = frequency;
aba3d3de Mike Looijmans 2018-03-13  180 settings->ls_div_bits = 0;
aba3d3de Mike Looijmans 2018-03-13  181
aba3d3de Mike Looijmans 2018-03-13  182 if (frequency >= (FVCO_MIN / 
HS_DIV_MAX))
aba3d3de Mike Looijmans 2018-03-13  183 settings->ls_div_bits = 
0;
aba3d3de Mike Looijmans 2018-03-13  184 else {
aba3d3de Mike Looijmans 2018-03-13  185 res = 1;
aba3d3de Mike Looijmans 2018-03-13  186 tmp = 2 * HS_DIV_MAX;
aba3d3de Mike Looijmans 2018-03-13  187 while (tmp <= 
(HS_DIV_MAX * 32)) {
aba3d3de Mike Looijmans 2018-03-13 @188 if ((frequency * 
tmp) >= FVCO_MIN)
aba3d3de Mike Looijmans 2018-03-13  189 break;
aba3d3de Mike Looijmans 2018-03-13  190 ++res;
aba3d3de Mike Looijmans 2018-03-13  191 tmp <<= 1;
aba3d3de Mike Looijmans 2018-03-13  192 }
aba3d3de Mike Looijmans 2018-03-13  193 settings->ls_div_bits = 
res;
aba3d3de Mike Looijmans 2018-03-13  194 ls_freq = frequency << 
res;
aba3d3de Mike Looijmans 2018-03-13  195 }
aba3d3de Mike Looijmans 2018-03-13  196
aba3d3de Mike Looijmans 2018-03-13  197 /* Determine minimum HS_DIV by 
rounding up */
aba3d3de Mike Looijmans 2018-03-13  198 vco = FVCO_MIN + ls_freq - 1;
aba3d3de Mike Looijmans 2018-03-13  199 do_div(vco, ls_freq);
aba3d3de Mike Looijmans 2018-03-13  200 settings->hs_div = vco;
aba3d3de Mike Looijmans 2018-03-13  201 /* round up to even number if 
needed */
aba3d3de Mike Looijmans 2018-03-13  202 if ((settings->hs_div > HS_DIV_MAX_ODD) 
&& (settings->hs_div & 1))
aba3d3de Mike Looijmans 2018-03-13  203 ++settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  204 /* Calculate VCO frequency (in 
10..12GHz range) */
aba3d3de Mike Looijmans 2018-03-13  205 vco = (u64)ls_freq * 
settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  206 /* Calculate the integer part 
of the feedback divider */
aba3d3de Mike Looijmans 2018-03-13  207 tmp = do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  208 settings->fb_div_int = vco;
aba3d3de Mike Looijmans 2018-03-13  209 /* And the fractional bits 
using the remainder */
aba3d3de Mike Looijmans 2018-03-13  210 vco = (u64)tmp << 32;
aba3d3de Mike Looijmans 2018-03-13  211 do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  212 settings->fb_div_frac = vco;
aba3d3de Mike Looijmans 2018-03-13  213
aba3d3de Mike Looijmans 2018-03-13  214 return 0;
aba3d3de Mike Looijmans 2018-03-13  215  }
aba3d3de Mike Looijmans 2018-03-13  216

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation





Kind regards,

Mike Looijmans
System Expert

TOPIC Products
Materiaalweg 4, NL-5681 RJ Best
Postbus 440, NL-5680 AK Best
Telefoon: +31 (0) 499 33 69 79
E-mail: mike.looijm...@topicproducts.com
Website: www.topicproducts.com

Please consider the

Re: [PATCH] clk: Add driver for the si544 clock generator chip

2018-03-15 Thread Dan Carpenter

Hi Mike,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.16-rc4]
[also build test WARNING on next-20180314]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Mike-Looijmans/clk-Add-driver-for-the-si544-clock-generator-chip/20180314-122736

smatch warnings:
drivers/clk/clk-si544.c:188 si544_calc_muldiv() warn: impossible condition 
'((frequency * tmp) >= 108) => (0-u32max >= 108)'

# 
https://github.com/0day-ci/linux/commit/aba3d3de8751c1457bcf0b75bcc901f289a18426
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout aba3d3de8751c1457bcf0b75bcc901f289a18426
vim +188 drivers/clk/clk-si544.c

aba3d3de Mike Looijmans 2018-03-13  168  
aba3d3de Mike Looijmans 2018-03-13  169  /* Calculate divider settings for a 
given frequency */
aba3d3de Mike Looijmans 2018-03-13  170  static int si544_calc_muldiv(struct 
clk_si544_muldiv *settings,
aba3d3de Mike Looijmans 2018-03-13  171 unsigned long frequency)
aba3d3de Mike Looijmans 2018-03-13  172  {
aba3d3de Mike Looijmans 2018-03-13  173 u64 vco;
aba3d3de Mike Looijmans 2018-03-13  174 u32 ls_freq;
aba3d3de Mike Looijmans 2018-03-13  175 u32 tmp;
aba3d3de Mike Looijmans 2018-03-13  176 u8 res;
aba3d3de Mike Looijmans 2018-03-13  177  
aba3d3de Mike Looijmans 2018-03-13  178 /* Determine the minimum value 
of LS_DIV and resulting target freq. */
aba3d3de Mike Looijmans 2018-03-13  179 ls_freq = frequency;
aba3d3de Mike Looijmans 2018-03-13  180 settings->ls_div_bits = 0;
aba3d3de Mike Looijmans 2018-03-13  181  
aba3d3de Mike Looijmans 2018-03-13  182 if (frequency >= (FVCO_MIN / 
HS_DIV_MAX))
aba3d3de Mike Looijmans 2018-03-13  183 settings->ls_div_bits = 
0;
aba3d3de Mike Looijmans 2018-03-13  184 else {
aba3d3de Mike Looijmans 2018-03-13  185 res = 1;
aba3d3de Mike Looijmans 2018-03-13  186 tmp = 2 * HS_DIV_MAX;
aba3d3de Mike Looijmans 2018-03-13  187 while (tmp <= 
(HS_DIV_MAX * 32)) {
aba3d3de Mike Looijmans 2018-03-13 @188 if ((frequency 
* tmp) >= FVCO_MIN)
aba3d3de Mike Looijmans 2018-03-13  189 break;
aba3d3de Mike Looijmans 2018-03-13  190 ++res;
aba3d3de Mike Looijmans 2018-03-13  191 tmp <<= 1;
aba3d3de Mike Looijmans 2018-03-13  192 }
aba3d3de Mike Looijmans 2018-03-13  193 settings->ls_div_bits = 
res;
aba3d3de Mike Looijmans 2018-03-13  194 ls_freq = frequency << 
res;
aba3d3de Mike Looijmans 2018-03-13  195 }
aba3d3de Mike Looijmans 2018-03-13  196  
aba3d3de Mike Looijmans 2018-03-13  197 /* Determine minimum HS_DIV by 
rounding up */
aba3d3de Mike Looijmans 2018-03-13  198 vco = FVCO_MIN + ls_freq - 1;
aba3d3de Mike Looijmans 2018-03-13  199 do_div(vco, ls_freq);
aba3d3de Mike Looijmans 2018-03-13  200 settings->hs_div = vco;
aba3d3de Mike Looijmans 2018-03-13  201 /* round up to even number if 
needed */
aba3d3de Mike Looijmans 2018-03-13  202 if ((settings->hs_div > 
HS_DIV_MAX_ODD) && (settings->hs_div & 1))
aba3d3de Mike Looijmans 2018-03-13  203 ++settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  204 /* Calculate VCO frequency (in 
10..12GHz range) */
aba3d3de Mike Looijmans 2018-03-13  205 vco = (u64)ls_freq * 
settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  206 /* Calculate the integer part 
of the feedback divider */
aba3d3de Mike Looijmans 2018-03-13  207 tmp = do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  208 settings->fb_div_int = vco;
aba3d3de Mike Looijmans 2018-03-13  209 /* And the fractional bits 
using the remainder */
aba3d3de Mike Looijmans 2018-03-13  210 vco = (u64)tmp << 32;
aba3d3de Mike Looijmans 2018-03-13  211 do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  212 settings->fb_div_frac = vco;
aba3d3de Mike Looijmans 2018-03-13  213  
aba3d3de Mike Looijmans 2018-03-13  214 return 0;
aba3d3de Mike Looijmans 2018-03-13  215  }
aba3d3de Mike Looijmans 2018-03-13  216  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

Re: [PATCH] clk: Add driver for the si544 clock generator chip

2018-03-15 Thread Dan Carpenter

Hi Mike,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.16-rc4]
[also build test WARNING on next-20180314]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Mike-Looijmans/clk-Add-driver-for-the-si544-clock-generator-chip/20180314-122736

smatch warnings:
drivers/clk/clk-si544.c:188 si544_calc_muldiv() warn: impossible condition 
'((frequency * tmp) >= 108) => (0-u32max >= 108)'

# 
https://github.com/0day-ci/linux/commit/aba3d3de8751c1457bcf0b75bcc901f289a18426
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout aba3d3de8751c1457bcf0b75bcc901f289a18426
vim +188 drivers/clk/clk-si544.c

aba3d3de Mike Looijmans 2018-03-13  168  
aba3d3de Mike Looijmans 2018-03-13  169  /* Calculate divider settings for a 
given frequency */
aba3d3de Mike Looijmans 2018-03-13  170  static int si544_calc_muldiv(struct 
clk_si544_muldiv *settings,
aba3d3de Mike Looijmans 2018-03-13  171 unsigned long frequency)
aba3d3de Mike Looijmans 2018-03-13  172  {
aba3d3de Mike Looijmans 2018-03-13  173 u64 vco;
aba3d3de Mike Looijmans 2018-03-13  174 u32 ls_freq;
aba3d3de Mike Looijmans 2018-03-13  175 u32 tmp;
aba3d3de Mike Looijmans 2018-03-13  176 u8 res;
aba3d3de Mike Looijmans 2018-03-13  177  
aba3d3de Mike Looijmans 2018-03-13  178 /* Determine the minimum value 
of LS_DIV and resulting target freq. */
aba3d3de Mike Looijmans 2018-03-13  179 ls_freq = frequency;
aba3d3de Mike Looijmans 2018-03-13  180 settings->ls_div_bits = 0;
aba3d3de Mike Looijmans 2018-03-13  181  
aba3d3de Mike Looijmans 2018-03-13  182 if (frequency >= (FVCO_MIN / 
HS_DIV_MAX))
aba3d3de Mike Looijmans 2018-03-13  183 settings->ls_div_bits = 
0;
aba3d3de Mike Looijmans 2018-03-13  184 else {
aba3d3de Mike Looijmans 2018-03-13  185 res = 1;
aba3d3de Mike Looijmans 2018-03-13  186 tmp = 2 * HS_DIV_MAX;
aba3d3de Mike Looijmans 2018-03-13  187 while (tmp <= 
(HS_DIV_MAX * 32)) {
aba3d3de Mike Looijmans 2018-03-13 @188 if ((frequency 
* tmp) >= FVCO_MIN)
aba3d3de Mike Looijmans 2018-03-13  189 break;
aba3d3de Mike Looijmans 2018-03-13  190 ++res;
aba3d3de Mike Looijmans 2018-03-13  191 tmp <<= 1;
aba3d3de Mike Looijmans 2018-03-13  192 }
aba3d3de Mike Looijmans 2018-03-13  193 settings->ls_div_bits = 
res;
aba3d3de Mike Looijmans 2018-03-13  194 ls_freq = frequency << 
res;
aba3d3de Mike Looijmans 2018-03-13  195 }
aba3d3de Mike Looijmans 2018-03-13  196  
aba3d3de Mike Looijmans 2018-03-13  197 /* Determine minimum HS_DIV by 
rounding up */
aba3d3de Mike Looijmans 2018-03-13  198 vco = FVCO_MIN + ls_freq - 1;
aba3d3de Mike Looijmans 2018-03-13  199 do_div(vco, ls_freq);
aba3d3de Mike Looijmans 2018-03-13  200 settings->hs_div = vco;
aba3d3de Mike Looijmans 2018-03-13  201 /* round up to even number if 
needed */
aba3d3de Mike Looijmans 2018-03-13  202 if ((settings->hs_div > 
HS_DIV_MAX_ODD) && (settings->hs_div & 1))
aba3d3de Mike Looijmans 2018-03-13  203 ++settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  204 /* Calculate VCO frequency (in 
10..12GHz range) */
aba3d3de Mike Looijmans 2018-03-13  205 vco = (u64)ls_freq * 
settings->hs_div;
aba3d3de Mike Looijmans 2018-03-13  206 /* Calculate the integer part 
of the feedback divider */
aba3d3de Mike Looijmans 2018-03-13  207 tmp = do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  208 settings->fb_div_int = vco;
aba3d3de Mike Looijmans 2018-03-13  209 /* And the fractional bits 
using the remainder */
aba3d3de Mike Looijmans 2018-03-13  210 vco = (u64)tmp << 32;
aba3d3de Mike Looijmans 2018-03-13  211 do_div(vco, FXO);
aba3d3de Mike Looijmans 2018-03-13  212 settings->fb_div_frac = vco;
aba3d3de Mike Looijmans 2018-03-13  213  
aba3d3de Mike Looijmans 2018-03-13  214 return 0;
aba3d3de Mike Looijmans 2018-03-13  215  }
aba3d3de Mike Looijmans 2018-03-13  216  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

[PATCH] clk: Add driver for the si544 clock generator chip

2018-03-13 Thread Mike Looijmans

This patch adds the driver and devicetree documentation for the
Silicon Labs SI544 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 200kHz
to 1500MHz.

Signed-off-by: Mike Looijmans 
---
 .../devicetree/bindings/clock/silabs,si544.txt |  25 ++
 drivers/clk/Kconfig|  10 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk-si544.c| 421 +
 4 files changed, 457 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/silabs,si544.txt
 create mode 100644 drivers/clk/clk-si544.c

diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt 
b/Documentation/devicetree/bindings/clock/silabs,si544.txt
new file mode 100644
index 000..eec1787
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/silabs,si544.txt
@@ -0,0 +1,25 @@
+Binding for Silicon Labs 544 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si544 datasheet
+https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
+
+Required properties:
+ - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" 
according
+   to the speed grade of the chip.
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si544".
+
+Example:
+   si544: clock-generator@55 {
+   reg = <0x55>;
+   #clock-cells = <0>;
+   compatible = "silabs,si544b";
+   };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 98ce9fc..5c7dc8e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -91,6 +91,16 @@ config COMMON_CLK_SI514
  This driver supports the Silicon Labs 514 programmable clock
  generator.
 
+config COMMON_CLK_SI544
+   tristate "Clock driver for SiLabs 544 devices"
+   depends on I2C
+   depends on OF
+   select REGMAP_I2C
+   help
+   ---help---
+ This driver supports the Silicon Labs 544 programmable clock
+ generator.
+
 config COMMON_CLK_SI570
tristate "Clock driver for SiLabs 570 and compatible devices"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71ec41e..bde614a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_S2MPS11)  += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SCPI)   += clk-scpi.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
+obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
 obj-$(CONFIG_ARCH_STM32)   += clk-stm32f4.o
 obj-$(CONFIG_ARCH_STM32)   += clk-stm32h7.o
diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
new file mode 100644
index 000..1947e48
--- /dev/null
+++ b/drivers/clk/clk-si544.c
@@ -0,0 +1,421 @@
+/*
+ * Driver for Silicon Labs Si544 Programmable Oscillator
+ *
+ * Copyright (C) 2018 Topic Embedded Products
+ *
+ * Author: Mike Looijmans 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* I2C registers (decimal as in datasheet) */
+#define SI544_REG_CONTROL  7
+#define SI544_REG_OE_STATE 17
+#define SI544_REG_HS_DIV   23
+#define SI544_REG_LS_HS_DIV24
+#define SI544_REG_FBDIV0   26
+#define SI544_REG_FBDIV8   27
+#define SI544_REG_FBDIV16  28
+#define SI544_REG_FBDIV24  29
+#define SI544_REG_FBDIV32  30
+#define SI544_REG_FBDIV40  31
+#define SI544_REG_FCAL_OVR 69
+#define SI544_REG_ADPLL_DELTA_M0   231
+#define SI544_REG_ADPLL_DELTA_M8   232
+#define SI544_REG_ADPLL_DELTA_M16  233
+#define SI544_REG_PAGE_SELECT  255
+
+/* Register values */
+#define SI544_CONTROL_RESETBIT(7)
+#define SI544_CONTROL_MS_ICAL2 BIT(3)
+
+#define SI544_OE_STATE_ODC_OE  BIT(0)
+
+/* Max freq depends on speed grade */
+#define SI544_MIN_FREQ 20U
+
+/* Si544 Internal oscilator runs at 55.05 MHz */
+#define FXO  5505U
+
+/* VCO range is 10.8 .. 12.1 GHz, max depends on speed

[PATCH] clk: Add driver for the si544 clock generator chip

2018-03-13 Thread Mike Looijmans

This patch adds the driver and devicetree documentation for the
Silicon Labs SI544 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 200kHz
to 1500MHz.

Signed-off-by: Mike Looijmans 
---
 .../devicetree/bindings/clock/silabs,si544.txt |  25 ++
 drivers/clk/Kconfig|  10 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk-si544.c| 421 +
 4 files changed, 457 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/silabs,si544.txt
 create mode 100644 drivers/clk/clk-si544.c

diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt 
b/Documentation/devicetree/bindings/clock/silabs,si544.txt
new file mode 100644
index 000..eec1787
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/silabs,si544.txt
@@ -0,0 +1,25 @@
+Binding for Silicon Labs 544 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si544 datasheet
+https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
+
+Required properties:
+ - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" 
according
+   to the speed grade of the chip.
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si544".
+
+Example:
+   si544: clock-generator@55 {
+   reg = <0x55>;
+   #clock-cells = <0>;
+   compatible = "silabs,si544b";
+   };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 98ce9fc..5c7dc8e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -91,6 +91,16 @@ config COMMON_CLK_SI514
  This driver supports the Silicon Labs 514 programmable clock
  generator.
 
+config COMMON_CLK_SI544
+   tristate "Clock driver for SiLabs 544 devices"
+   depends on I2C
+   depends on OF
+   select REGMAP_I2C
+   help
+   ---help---
+ This driver supports the Silicon Labs 544 programmable clock
+ generator.
+
 config COMMON_CLK_SI570
tristate "Clock driver for SiLabs 570 and compatible devices"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71ec41e..bde614a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_S2MPS11)  += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SCPI)   += clk-scpi.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
+obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
 obj-$(CONFIG_ARCH_STM32)   += clk-stm32f4.o
 obj-$(CONFIG_ARCH_STM32)   += clk-stm32h7.o
diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
new file mode 100644
index 000..1947e48
--- /dev/null
+++ b/drivers/clk/clk-si544.c
@@ -0,0 +1,421 @@
+/*
+ * Driver for Silicon Labs Si544 Programmable Oscillator
+ *
+ * Copyright (C) 2018 Topic Embedded Products
+ *
+ * Author: Mike Looijmans 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* I2C registers (decimal as in datasheet) */
+#define SI544_REG_CONTROL  7
+#define SI544_REG_OE_STATE 17
+#define SI544_REG_HS_DIV   23
+#define SI544_REG_LS_HS_DIV24
+#define SI544_REG_FBDIV0   26
+#define SI544_REG_FBDIV8   27
+#define SI544_REG_FBDIV16  28
+#define SI544_REG_FBDIV24  29
+#define SI544_REG_FBDIV32  30
+#define SI544_REG_FBDIV40  31
+#define SI544_REG_FCAL_OVR 69
+#define SI544_REG_ADPLL_DELTA_M0   231
+#define SI544_REG_ADPLL_DELTA_M8   232
+#define SI544_REG_ADPLL_DELTA_M16  233
+#define SI544_REG_PAGE_SELECT  255
+
+/* Register values */
+#define SI544_CONTROL_RESETBIT(7)
+#define SI544_CONTROL_MS_ICAL2 BIT(3)
+
+#define SI544_OE_STATE_ODC_OE  BIT(0)
+
+/* Max freq depends on speed grade */
+#define SI544_MIN_FREQ 20U
+
+/* Si544 Internal oscilator runs at 55.05 MHz */
+#define FXO  5505U
+
+/* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
+#define FVCO_MIN   108ULL
+

Re: [PATCH] clk: Add driver for the si544 clock generator chip

Re: [PATCH] clk: Add driver for the si544 clock generator chip

Re: [PATCH] clk: Add driver for the si544 clock generator chip

Re: [PATCH] clk: Add driver for the si544 clock generator chip

Re: [PATCH] clk: Add driver for the si544 clock generator chip

Re: [PATCH] clk: Add driver for the si544 clock generator chip

[PATCH] clk: Add driver for the si544 clock generator chip

[PATCH] clk: Add driver for the si544 clock generator chip

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