Intel PT chapter in the new Intel Architecture SDM adds several packets
and corresponding enable bits that control packet generation. Also,
additional bits in the Intel PT CPUID leaf were added to enumerate
presence and parameters of these new packets and features.
The packets and enables are:
Intel PT chapter in the new Intel Architecture SDM adds several packets
and corresponding enable bits that control packet generation. Also,
additional bits in the Intel PT CPUID leaf were added to enumerate
presence and parameters of these new packets and features.
The packets and enables are:
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