[PATCH] x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features.

2016-10-12 Thread Piotr Luc 
AVX512_4VNNIW  - Vector instructions for deep learning enhanced word
variable precision.
AVX512_4FMAPS - Vector instructions for deep learning floating-point
single precision.

The new instructions are to be used in future Intel Xeon & Xeon Phi
processors.

The spec can be found in Intel Software Developer Manual or in
Instruction Set Extensions Programming Reference. See
https://software.intel.com/sites/default/files/managed/69/78/319433-025.pdf.

Signed-off-by: Piotr Luc 
Reviewed-by: Dave Hansen 
Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/x86/include/asm/cpufeature.h  | 7 +--
 arch/x86/include/asm/cpufeatures.h | 6 +-
 arch/x86/include/asm/disabled-features.h   | 3 ++-
 arch/x86/include/asm/required-features.h   | 3 ++-
 arch/x86/kernel/cpu/common.c   | 1 +
 arch/x86/kernel/fpu/xstate.c   | 2 ++
 tools/arch/x86/include/asm/cpufeatures.h   | 6 +-
 tools/arch/x86/include/asm/disabled-features.h | 3 ++-
 tools/arch/x86/include/asm/required-features.h | 3 ++-
 9 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h 
b/arch/x86/include/asm/cpufeature.h
index 1d2b69f..617452e 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -28,6 +28,7 @@ enum cpuid_leafs
CPUID_8000_000A_EDX,
CPUID_7_ECX,
CPUID_8000_0007_EBX,
+   CPUID_7_EDX,
 };
 
 #ifdef CONFIG_X86_FEATURE_NAMES
@@ -78,8 +79,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||\
+  CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||\
   REQUIRED_MASK_CHECK||\
-  BUILD_BUG_ON_ZERO(NCAPINTS != 18))
+  BUILD_BUG_ON_ZERO(NCAPINTS != 19))
 
 #define DISABLED_MASK_BIT_SET(feature_bit) \
 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||\
@@ -100,8 +102,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||\
+  CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||\
   DISABLED_MASK_CHECK||\
-  BUILD_BUG_ON_ZERO(NCAPINTS != 18))
+  BUILD_BUG_ON_ZERO(NCAPINTS != 19))
 
 #define cpu_has(c, bit)
\
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :  \
diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index 92a8308..309fd2d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -12,7 +12,7 @@
 /*
  * Defines x86 CPU feature bits
  */
-#define NCAPINTS   18  /* N 32-bit words worth of info */
+#define NCAPINTS   19  /* N 32-bit words worth of info */
 #define NBUGINTS   1   /* N 32-bit bug flags */
 
 /*
@@ -286,6 +286,10 @@
 #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment 
and recovery */
 #define X86_FEATURE_SMCA   (17*32+3) /* Scalable MCA */
 
+/* Intel-defined CPU features, CPUID level 0x0007:0 (edx), word 18 */
+#define X86_FEATURE_AVX512_4VNNIW  (18*32+2) /* AVX-512 Neural Network 
Instructions */
+#define X86_FEATURE_AVX512_4FMAPS  (18*32+3) /* AVX-512 Multiply Accumulation 
Single precision */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/include/asm/disabled-features.h 
b/arch/x86/include/asm/disabled-features.h
index 85599ad..8b45e08 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -57,6 +57,7 @@
 #define DISABLED_MASK150
 #define DISABLED_MASK16(DISABLE_PKU|DISABLE_OSPKE)
 #define DISABLED_MASK170
-#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
+#define DISABLED_MASK180
+#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
 
 #endif /* _ASM_X86_DISABLED_FEATURES_H */
diff --git a/arch/x86/include/asm/required-features.h 
b/arch/x86/include/asm/required-features.h
index fac9a5c..6847d85 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -100,6 +100,7 @@
 #define REQUIRED_MASK150
 #define REQUIRED_MASK160
 #define REQUIRED_MASK170
-#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
+#define REQUIRED_MASK180
+#define REQUIRED_MASK_CHECK

[PATCH] x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features.

2016-10-12 Thread Piotr Luc 
AVX512_4VNNIW  - Vector instructions for deep learning enhanced word
variable precision.
AVX512_4FMAPS - Vector instructions for deep learning floating-point
single precision.

The new instructions are to be used in future Intel Xeon & Xeon Phi
processors.

The spec can be found in Intel Software Developer Manual or in
Instruction Set Extensions Programming Reference. See
https://software.intel.com/sites/default/files/managed/69/78/319433-025.pdf.

Signed-off-by: Piotr Luc 
Reviewed-by: Dave Hansen 
Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/x86/include/asm/cpufeature.h  | 7 +--
 arch/x86/include/asm/cpufeatures.h | 6 +-
 arch/x86/include/asm/disabled-features.h   | 3 ++-
 arch/x86/include/asm/required-features.h   | 3 ++-
 arch/x86/kernel/cpu/common.c   | 1 +
 arch/x86/kernel/fpu/xstate.c   | 2 ++
 tools/arch/x86/include/asm/cpufeatures.h   | 6 +-
 tools/arch/x86/include/asm/disabled-features.h | 3 ++-
 tools/arch/x86/include/asm/required-features.h | 3 ++-
 9 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h 
b/arch/x86/include/asm/cpufeature.h
index 1d2b69f..617452e 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -28,6 +28,7 @@ enum cpuid_leafs
CPUID_8000_000A_EDX,
CPUID_7_ECX,
CPUID_8000_0007_EBX,
+   CPUID_7_EDX,
 };
 
 #ifdef CONFIG_X86_FEATURE_NAMES
@@ -78,8 +79,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||\
+  CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||\
   REQUIRED_MASK_CHECK||\
-  BUILD_BUG_ON_ZERO(NCAPINTS != 18))
+  BUILD_BUG_ON_ZERO(NCAPINTS != 19))
 
 #define DISABLED_MASK_BIT_SET(feature_bit) \
 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||\
@@ -100,8 +102,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) ||\
   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||\
+  CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||\
   DISABLED_MASK_CHECK||\
-  BUILD_BUG_ON_ZERO(NCAPINTS != 18))
+  BUILD_BUG_ON_ZERO(NCAPINTS != 19))
 
 #define cpu_has(c, bit)
\
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :  \
diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index 92a8308..309fd2d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -12,7 +12,7 @@
 /*
  * Defines x86 CPU feature bits
  */
-#define NCAPINTS   18  /* N 32-bit words worth of info */
+#define NCAPINTS   19  /* N 32-bit words worth of info */
 #define NBUGINTS   1   /* N 32-bit bug flags */
 
 /*
@@ -286,6 +286,10 @@
 #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment 
and recovery */
 #define X86_FEATURE_SMCA   (17*32+3) /* Scalable MCA */
 
+/* Intel-defined CPU features, CPUID level 0x0007:0 (edx), word 18 */
+#define X86_FEATURE_AVX512_4VNNIW  (18*32+2) /* AVX-512 Neural Network 
Instructions */
+#define X86_FEATURE_AVX512_4FMAPS  (18*32+3) /* AVX-512 Multiply Accumulation 
Single precision */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/include/asm/disabled-features.h 
b/arch/x86/include/asm/disabled-features.h
index 85599ad..8b45e08 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -57,6 +57,7 @@
 #define DISABLED_MASK150
 #define DISABLED_MASK16(DISABLE_PKU|DISABLE_OSPKE)
 #define DISABLED_MASK170
-#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
+#define DISABLED_MASK180
+#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
 
 #endif /* _ASM_X86_DISABLED_FEATURES_H */
diff --git a/arch/x86/include/asm/required-features.h 
b/arch/x86/include/asm/required-features.h
index fac9a5c..6847d85 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -100,6 +100,7 @@
 #define REQUIRED_MASK150
 #define REQUIRED_MASK160
 #define REQUIRED_MASK170
-#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
+#define REQUIRED_MASK180
+#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
 
 #endif /* _ASM_X86_REQUIRED_FEATURES_H */
diff --git