In accordance with Intel's microcode revision guidance from March 6 MCU
rev 0xc2 is cleared on both Skylake H/S and Skylake Xeon E3 processors
that share CPUID 506E3.
Signed-off-by: Alexander Sergeyev
---
arch/x86/kernel/cpu/intel.c | 3 +--
1 file changed, 1 insertion(+),
In accordance with Intel's microcode revision guidance from March 6 MCU
rev 0xc2 is cleared on both Skylake H/S and Skylake Xeon E3 processors
that share CPUID 506E3.
Signed-off-by: Alexander Sergeyev
---
arch/x86/kernel/cpu/intel.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
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