Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:46 PM, Andy Shevchenko wrote: > + pci_read_config_dword(dev, SKX_CAPID6, ); > + return bitmap_weight((unsigned long *), SKX_CHA_BIT_WIDTH); Forgot about hweight32(). Can you use that one directly? hweight32(x &

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:46 PM, Andy Shevchenko wrote: > + pci_read_config_dword(dev, SKX_CAPID6, ); > + return bitmap_weight((unsigned long *), SKX_CHA_BIT_WIDTH); Forgot about hweight32(). Can you use that one directly? hweight32(x & (BIT(_WIDTH) - 1)); ? -- With Best

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:49 PM, Andy Shevchenko wrote: > On Tue, Mar 13, 2018 at 7:46 PM, Andy Shevchenko > wrote: >> + pci_read_config_dword(dev, SKX_CAPID6, ); >> + return bitmap_weight((unsigned long *),

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:49 PM, Andy Shevchenko wrote: > On Tue, Mar 13, 2018 at 7:46 PM, Andy Shevchenko > wrote: >> + pci_read_config_dword(dev, SKX_CAPID6, ); >> + return bitmap_weight((unsigned long *), SKX_CHA_BIT_WIDTH); > > Forgot about hweight32(). Can you use that

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

+ pci_read_config_dword(dev, SKX_CAPID6, ); + return bitmap_weight((unsigned long *), SKX_CHA_BIT_WIDTH); >>> >>> >>> UB is here. >>> Fix is simple, use unsigned long and drop this ugly casting. >>> > > Just noticed that we have to do casting anyway. No. >

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

+ pci_read_config_dword(dev, SKX_CAPID6, ); + return bitmap_weight((unsigned long *), SKX_CHA_BIT_WIDTH); >>> >>> >>> UB is here. >>> Fix is simple, use unsigned long and drop this ugly casting. >>> > > Just noticed that we have to do casting anyway. No. >

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 1:16 PM, Liang, Kan wrote: On 3/13/2018 11:58 AM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c +#define SKX_CHA_BIT_WIDTH  28 +   static int skx_count_chabox(void)   { +  

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 1:16 PM, Liang, Kan wrote: On 3/13/2018 11:58 AM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c +#define SKX_CHA_BIT_WIDTH  28 +   static int skx_count_chabox(void)   { +   struct pci_dev *dev = NULL;

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:28 PM, Liang, Kan wrote: >> +#define SKX_CAPID6 0x9c ^^^ This needs a comment. >>> It looks it doesn't use capability. > $ lspci -nk -vvv -xx -s 16:1e.3 > 16:1e.3 0880: 8086:2083 (rev 04) > Subsystem: 8086: >

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:28 PM, Liang, Kan wrote: >> +#define SKX_CAPID6 0x9c ^^^ This needs a comment. >>> It looks it doesn't use capability. > $ lspci -nk -vvv -xx -s 16:1e.3 > 16:1e.3 0880: 8086:2083 (rev 04) > Subsystem: 8086: > Control: I/O- Mem-

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 1:22 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 7:15 PM, Liang, Kan wrote: On 3/13/2018 12:00 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM,

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 1:22 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 7:15 PM, Liang, Kan wrote: On 3/13/2018 12:00 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:15 PM, Liang, Kan wrote: > On 3/13/2018 12:00 PM, Andy Shevchenko wrote: >> On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko >> wrote: >>> On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan >>>

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 7:15 PM, Liang, Kan wrote: > On 3/13/2018 12:00 PM, Andy Shevchenko wrote: >> On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko >> wrote: >>> On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan >>> wrote: +#define SKX_CAPID6 0x9c +

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 11:58 AM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c +#define SKX_CHA_BIT_WIDTH 28 + static int skx_count_chabox(void) { + struct pci_dev *dev = NULL; + u32 val =

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 11:58 AM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c +#define SKX_CHA_BIT_WIDTH 28 + static int skx_count_chabox(void) { + struct pci_dev *dev = NULL; + u32 val = 0; + dev =

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 12:00 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c + pci_read_config_dword(dev,

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/13/2018 12:00 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko wrote: On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: +#define SKX_CAPID6 0x9c + pci_read_config_dword(dev, SKX_CAPID6, ); Moreover, this is too non-flexible. Can't

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko wrote: > On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: > >> +#define SKX_CAPID6 0x9c >> + pci_read_config_dword(dev, SKX_CAPID6, ); Moreover, this is too non-flexible.

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko wrote: > On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: > >> +#define SKX_CAPID6 0x9c >> + pci_read_config_dword(dev, SKX_CAPID6, ); Moreover, this is too non-flexible. Can't you find a capability based on CAP ID + offset?

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: > +#define SKX_CAPID6 0x9c > +#define SKX_CHA_BIT_WIDTH 28 > + > static int skx_count_chabox(void) > { > + struct pci_dev *dev = NULL; > + u32 val = 0; > > + dev =

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan wrote: > +#define SKX_CAPID6 0x9c > +#define SKX_CHA_BIT_WIDTH 28 > + > static int skx_count_chabox(void) > { > + struct pci_dev *dev = NULL; > + u32 val = 0; > > + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083,

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

kernel.org; linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci- segment arches On 3/7/2018 3:33 PM, Kroening, Gary wrote: For systems with a single PCI segment, it is sufficient to look for the bus number to change in order to determine that all of

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

kernel.org; linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci- segment arches On 3/7/2018 3:33 PM, Kroening, Gary wrote: For systems with a single PCI segment, it is sufficient to look for the bus number to change in order to determine that all of

RE: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

; Cc: Travis, Mike; Banman, Andrew; Sivanich, Dimitri; Anderson, Russ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: RE: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci- > segment arches > > Thanks, Kan -- your patch looks good, and cleaner than the pr

RE: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

; Cc: Travis, Mike; Banman, Andrew; Sivanich, Dimitri; Anderson, Russ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: RE: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci- > segment arches > > Thanks, Kan -- your patch looks good, and cleaner than the pr

RE: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

, March 12, 2018 8:43 PM > To: Kroening, Gary; mi...@redhat.com; h...@zytor.com; t...@linutronix.de; > pet...@infradead.org > Cc: Travis, Mike; Banman, Andrew; Sivanich, Dimitri; Anderson, Russ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/1] x86/platform/x86:

RE: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

, March 12, 2018 8:43 PM > To: Kroening, Gary; mi...@redhat.com; h...@zytor.com; t...@linutronix.de; > pet...@infradead.org > Cc: Travis, Mike; Banman, Andrew; Sivanich, Dimitri; Anderson, Russ; > x...@kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/1] x86/platform/x86:

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/7/2018 3:33 PM, Kroening, Gary wrote: For systems with a single PCI segment, it is sufficient to look for the bus number to change in order to determine that all of the CHa's have been counted for a single socket. However, for multi PCI segment systems, each socket is given a new segment

Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

On 3/7/2018 3:33 PM, Kroening, Gary wrote: For systems with a single PCI segment, it is sufficient to look for the bus number to change in order to determine that all of the CHa's have been counted for a single socket. However, for multi PCI segment systems, each socket is given a new segment

[PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

For systems with a single PCI segment, it is sufficient to look for the bus number to change in order to determine that all of the CHa's have been counted for a single socket. However, for multi PCI segment systems, each socket is given a new segment and the bus number does NOT change. So

[PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

For systems with a single PCI segment, it is sufficient to look for the bus number to change in order to determine that all of the CHa's have been counted for a single socket. However, for multi PCI segment systems, each socket is given a new segment and the bus number does NOT change. So