Re: [PATCH 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
On 02/19/2018 02:51 AM, Rob Herring wrote:
> On Mon, Feb 12, 2018 at 01:35:28PM +0100, Amelie Delaunay wrote:
>> This patch adds the device tree bindings description for STM32 USBPHYC
>> (USB PHY Controller).
>>
>> Signed-off-by: Amelie Delaunay
>> ---
>> .../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46
>> ++
>> 1 file changed, 46 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>> b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>> new file mode 100644
>> index 000..1e65e0a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>> @@ -0,0 +1,46 @@
>> +STMicroelectronics STM32 USB HS PHY controller
>> +
>> +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
>> +switch. It controls PHY configuration and status, and the UTMI+ switch that
>> +selects either OTG or HOST controller for the second PHY port. It also sets
>> +PLL configuration.
>> +
>> +USBPHYC
>> + |_ PLL
>> + |
>> + |_ PHY port#1 _ HOST controller
>> + | |
>> + |_ PHY port#2___ |
>> + | |_ |
>> + |_ UTMI switch_/ 1||
>> +| |
>> + \_0||
>> + OTG controller
>> +
>> +Required properties:
>> +- compatible: must be "st,stm32mp1-usbphyc"
>> +- reg: address and length of the usb phy control register set
>> +- clocks: phandle + clock specifier for the PLL phy clock
>> +- phy-supply: from the generic phy bindings, phandle to the regulator
>> + providing 3V3 power to the PHY, see phy-bindings.txt
>> +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
>> +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
>> +
>> +Optional properties:
>> +- assigned-clocks: phandle + clock specifier for the PLL phy clock
>> +- assigned-clock-parents: the PLL phy clock parent
>> +- resets: phandle + reset specifier
>> +- st,port2-switch-to-host: select HOST controller on UTMI switch for port#2
>
> This one seems very specific. If another device had the mux on a
> different port number you'd need a new property for example.
>
You're right. I will update the scheme with the following:
USBPHYC
|_ PLL
|
|_ PHY port#1 _ HOST controller
|_ |
| / 1||
|_ PHY port#2 | |
| \_0||
|_ UTMI switch___| OTG controller
This way would be more generic:
st,utmi-switch = <0>; //To select the controller connected to UTMI
switch #0 output.
st,utmi-switch = <1>; //To select the controller connected to UTMI
switch #1 output.
> But really I think this should be determined by either a USB connector
> node (a binding is in the works) or cable detection.
>
This needs to be further studied. Could it be an upcoming evolution ?
Thanks for review,
Amelie
>> +
>> +
>> +Example:
>> +usbphyc: usbphyc@5a006000 {
>
> usb-phy@...
>
>> +compatible = "st,stm32mp1-usbphyc";
>> +reg = <0x5a006000 0x1000>;
>> +clocks = <&rcc_clk USBPHY_K>;
>> +resets = <&rcc_rst USBPHY_R>;
>> +st,port2-switch-to-host;
>> +phy-supply = <&vdd_usb>;
>> +vdda1v1-supply = <®11>;
>> +vdda1v8-supply = <®18>
>> +};
>> --
>> 2.7.4
>>
Re: [PATCH 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
On Mon, Feb 12, 2018 at 01:35:28PM +0100, Amelie Delaunay wrote:
> This patch adds the device tree bindings description for STM32 USBPHYC
> (USB PHY Controller).
>
> Signed-off-by: Amelie Delaunay
> ---
> .../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46
> ++
> 1 file changed, 46 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> new file mode 100644
> index 000..1e65e0a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> @@ -0,0 +1,46 @@
> +STMicroelectronics STM32 USB HS PHY controller
> +
> +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
> +switch. It controls PHY configuration and status, and the UTMI+ switch that
> +selects either OTG or HOST controller for the second PHY port. It also sets
> +PLL configuration.
> +
> +USBPHYC
> + |_ PLL
> + |
> + |_ PHY port#1 _ HOST controller
> + | |
> + |_ PHY port#2___ |
> + | |_ |
> + |_ UTMI switch_/ 1||
> +| |
> + \_0||
> + OTG controller
> +
> +Required properties:
> +- compatible: must be "st,stm32mp1-usbphyc"
> +- reg: address and length of the usb phy control register set
> +- clocks: phandle + clock specifier for the PLL phy clock
> +- phy-supply: from the generic phy bindings, phandle to the regulator
> + providing 3V3 power to the PHY, see phy-bindings.txt
> +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
> +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
> +
> +Optional properties:
> +- assigned-clocks: phandle + clock specifier for the PLL phy clock
> +- assigned-clock-parents: the PLL phy clock parent
> +- resets: phandle + reset specifier
> +- st,port2-switch-to-host: select HOST controller on UTMI switch for port#2
This one seems very specific. If another device had the mux on a
different port number you'd need a new property for example.
But really I think this should be determined by either a USB connector
node (a binding is in the works) or cable detection.
> +
> +
> +Example:
> + usbphyc: usbphyc@5a006000 {
usb-phy@...
> + compatible = "st,stm32mp1-usbphyc";
> + reg = <0x5a006000 0x1000>;
> + clocks = <&rcc_clk USBPHY_K>;
> + resets = <&rcc_rst USBPHY_R>;
> + st,port2-switch-to-host;
> + phy-supply = <&vdd_usb>;
> + vdda1v1-supply = <®11>;
> + vdda1v8-supply = <®18>
> + };
> --
> 2.7.4
>
[PATCH 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
This patch adds the device tree bindings description for STM32 USBPHYC
(USB PHY Controller).
Signed-off-by: Amelie Delaunay
---
.../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
new file mode 100644
index 000..1e65e0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STM32 USB HS PHY controller
+
+The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+switch. It controls PHY configuration and status, and the UTMI+ switch that
+selects either OTG or HOST controller for the second PHY port. It also sets
+PLL configuration.
+
+USBPHYC
+ |_ PLL
+ |
+ |_ PHY port#1 _ HOST controller
+ | |
+ |_ PHY port#2___ |
+ | |_ |
+ |_ UTMI switch_/ 1||
+| |
+ \_0||
+ OTG controller
+
+Required properties:
+- compatible: must be "st,stm32mp1-usbphyc"
+- reg: address and length of the usb phy control register set
+- clocks: phandle + clock specifier for the PLL phy clock
+- phy-supply: from the generic phy bindings, phandle to the regulator
+ providing 3V3 power to the PHY, see phy-bindings.txt
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
+
+Optional properties:
+- assigned-clocks: phandle + clock specifier for the PLL phy clock
+- assigned-clock-parents: the PLL phy clock parent
+- resets: phandle + reset specifier
+- st,port2-switch-to-host: select HOST controller on UTMI switch for port#2
+
+
+Example:
+ usbphyc: usbphyc@5a006000 {
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc_clk USBPHY_K>;
+ resets = <&rcc_rst USBPHY_R>;
+ st,port2-switch-to-host;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>
+ };
--
2.7.4
