[PATCH 1/3] arm64: dts: zx: support cpu-freq for zx296718

[Baoyou Xie]

This patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Signed-off-by: Baoyou Xie 
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 37 +++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi 
b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 7a1aed7..16f7d5e 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -44,6 +44,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "zte,zx296718";
@@ -81,6 +82,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+   clocks = < A53_GATE>;
+   operating-points-v2 = <_opp>;
};
 
cpu1: cpu@1 {
@@ -88,6 +91,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu2: cpu@2 {
@@ -95,6 +99,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu3: cpu@3 {
@@ -102,6 +107,38 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
+   };
+   };
+
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@64800 {
+   opp-hz = /bits/ 64 <64800>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@8 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <882000>;
+   clock-latency-ns = <50>;
+   };
+   opp@10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <892000>;
+   clock-latency-ns = <50>;
+   };
+   opp@118800 {
+   opp-hz = /bits/ 64 <118800>;
+   opp-microvolt = <1009000>;
+   clock-latency-ns = <50>;
};
};
 
-- 
2.7.4

[PATCH 1/3] arm64: dts: zx: support cpu-freq for zx296718

[Baoyou Xie]

This patch adds the CPU clock phandle in CPU's node
and uses operating-points-v2 to register operating points.

So it can be used by cpufreq-dt driver.

Signed-off-by: Baoyou Xie 
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 37 +++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi 
b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 7a1aed7..16f7d5e 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -44,6 +44,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "zte,zx296718";
@@ -81,6 +82,8 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+   clocks = < A53_GATE>;
+   operating-points-v2 = <_opp>;
};
 
cpu1: cpu@1 {
@@ -88,6 +91,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu2: cpu@2 {
@@ -95,6 +99,7 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
};
 
cpu3: cpu@3 {
@@ -102,6 +107,38 @@
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+   operating-points-v2 = <_opp>;
+   };
+   };
+
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@64800 {
+   opp-hz = /bits/ 64 <64800>;
+   opp-microvolt = <857000>;
+   clock-latency-ns = <50>;
+   };
+   opp@8 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <882000>;
+   clock-latency-ns = <50>;
+   };
+   opp@10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <892000>;
+   clock-latency-ns = <50>;
+   };
+   opp@118800 {
+   opp-hz = /bits/ 64 <118800>;
+   opp-microvolt = <1009000>;
+   clock-latency-ns = <50>;
};
};
 
-- 
2.7.4