Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote: > Ls1088a platform, the i2c input clock is actually platform pll CLK / 8 > (this is the hardware connection), other clock divider can not get the > correct i2c clock, resulting in the output of SCL pin clock is not > accurate. > > Signed-off-by: Chuanhua Han Applied all, thanks.
RE: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
> -Original Message- > From: Shawn Guo > Sent: Monday, August 12, 2019 9:17 AM > To: Chuanhua Han > Cc: Leo Li ; robh...@kernel.org; > mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider > > On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote: > > Ls1088a platform, the i2c input clock is actually platform pll CLK / 8 > > (this is the hardware connection), other clock divider can not get the > > correct i2c clock, resulting in the output of SCL pin clock is not > > accurate. > > > > Signed-off-by: Chuanhua Han > > @Leo, looks good? Yes. Acked-by: Li Yang > > Shawn > > > --- > > arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > > index 20f5ebd..30b760e 100644 > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > > @@ -324,7 +324,7 @@ > > #size-cells = <0>; > > reg = <0x0 0x200 0x0 0x1>; > > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = < 4 3>; > > + clocks = < 4 7>; > > status = "disabled"; > > }; > > > > @@ -334,7 +334,7 @@ > > #size-cells = <0>; > > reg = <0x0 0x201 0x0 0x1>; > > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = < 4 3>; > > + clocks = < 4 7>; > > status = "disabled"; > > }; > > > > @@ -344,7 +344,7 @@ > > #size-cells = <0>; > > reg = <0x0 0x202 0x0 0x1>; > > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = < 4 3>; > > + clocks = < 4 7>; > > status = "disabled"; > > }; > > > > @@ -354,7 +354,7 @@ > > #size-cells = <0>; > > reg = <0x0 0x203 0x0 0x1>; > > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = < 4 3>; > > + clocks = < 4 7>; > > status = "disabled"; > > }; > > > > -- > > 2.9.5 > >
Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote: > Ls1088a platform, the i2c input clock is actually platform pll CLK / 8 > (this is the hardware connection), other clock divider can not get the > correct i2c clock, resulting in the output of SCL pin clock is not > accurate. > > Signed-off-by: Chuanhua Han @Leo, looks good? Shawn > --- > arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > index 20f5ebd..30b760e 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > @@ -324,7 +324,7 @@ > #size-cells = <0>; > reg = <0x0 0x200 0x0 0x1>; > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; > - clocks = < 4 3>; > + clocks = < 4 7>; > status = "disabled"; > }; > > @@ -334,7 +334,7 @@ > #size-cells = <0>; > reg = <0x0 0x201 0x0 0x1>; > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; > - clocks = < 4 3>; > + clocks = < 4 7>; > status = "disabled"; > }; > > @@ -344,7 +344,7 @@ > #size-cells = <0>; > reg = <0x0 0x202 0x0 0x1>; > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; > - clocks = < 4 3>; > + clocks = < 4 7>; > status = "disabled"; > }; > > @@ -354,7 +354,7 @@ > #size-cells = <0>; > reg = <0x0 0x203 0x0 0x1>; > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; > - clocks = < 4 3>; > + clocks = < 4 7>; > status = "disabled"; > }; > > -- > 2.9.5 >
[PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
Ls1088a platform, the i2c input clock is actually platform pll CLK / 8 (this is the hardware connection), other clock divider can not get the correct i2c clock, resulting in the output of SCL pin clock is not accurate. Signed-off-by: Chuanhua Han --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 20f5ebd..30b760e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -324,7 +324,7 @@ #size-cells = <0>; reg = <0x0 0x200 0x0 0x1>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = < 4 3>; + clocks = < 4 7>; status = "disabled"; }; @@ -334,7 +334,7 @@ #size-cells = <0>; reg = <0x0 0x201 0x0 0x1>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = < 4 3>; + clocks = < 4 7>; status = "disabled"; }; @@ -344,7 +344,7 @@ #size-cells = <0>; reg = <0x0 0x202 0x0 0x1>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = < 4 3>; + clocks = < 4 7>; status = "disabled"; }; @@ -354,7 +354,7 @@ #size-cells = <0>; reg = <0x0 0x203 0x0 0x1>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = < 4 3>; + clocks = < 4 7>; status = "disabled"; }; -- 2.9.5
