[PATCH 11/17] RISC-V: Generic library routines and assembly
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt--- arch/riscv/include/asm/asm.h| 76 + arch/riscv/include/asm/csr.h| 125 arch/riscv/include/asm/linkage.h| 20 ++ arch/riscv/include/asm/string.h | 26 ++ arch/riscv/include/asm/uaccess.h| 513 arch/riscv/include/asm/word-at-a-time.h | 55 arch/riscv/kernel/stacktrace.c | 177 +++ arch/riscv/lib/memcpy.S | 115 +++ arch/riscv/lib/memset.S | 120 arch/riscv/lib/uaccess.S| 117 arch/riscv/lib/udivdi3.S| 38 +++ 11 files changed, 1382 insertions(+) create mode 100644 arch/riscv/include/asm/asm.h create mode 100644 arch/riscv/include/asm/csr.h create mode 100644 arch/riscv/include/asm/linkage.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/uaccess.h create mode 100644 arch/riscv/include/asm/word-at-a-time.h create mode 100644 arch/riscv/kernel/stacktrace.c create mode 100644 arch/riscv/lib/memcpy.S create mode 100644 arch/riscv/lib/memset.S create mode 100644 arch/riscv/lib/uaccess.S create mode 100644 arch/riscv/lib/udivdi3.S diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h new file mode 100644 index ..6cbbb6a68d76 --- /dev/null +++ b/arch/riscv/include/asm/asm.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b)__ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b)__ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ == 8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR8 +#define RISCV_LGPTR3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR"8" +#define RISCV_LGPTR"3" +#endif +#elif __SIZEOF_POINTER__ == 4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR4 +#define RISCV_LGPTR2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR"4" +#define RISCV_LGPTR"2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ == 4) +#define INT__ASM_STR(.word) +#define SZINT __ASM_STR(4) +#define LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ == 2) +#define SHORT __ASM_STR(.half) +#define SZSHORT__ASM_STR(2) +#define LGSHORT__ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index ..387d0dbf0073 --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#include + +/* Status register flags */ +#define SR_IE _AC(0x0002, UL) /* Interrupt Enable */ +#define SR_PIE _AC(0x0020, UL) /* Previous IE */ +#define SR_PS _AC(0x0100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x0004, UL) /* Supervisor may access User Memory */ + +#define SR_FS _AC(0x6000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x, UL) +#define SR_FS_INITIAL
[PATCH 11/17] RISC-V: Generic library routines and assembly
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/asm.h| 76 + arch/riscv/include/asm/csr.h| 125 arch/riscv/include/asm/linkage.h| 20 ++ arch/riscv/include/asm/string.h | 26 ++ arch/riscv/include/asm/uaccess.h| 513 arch/riscv/include/asm/word-at-a-time.h | 55 arch/riscv/kernel/stacktrace.c | 177 +++ arch/riscv/lib/memcpy.S | 115 +++ arch/riscv/lib/memset.S | 120 arch/riscv/lib/uaccess.S| 117 arch/riscv/lib/udivdi3.S| 38 +++ 11 files changed, 1382 insertions(+) create mode 100644 arch/riscv/include/asm/asm.h create mode 100644 arch/riscv/include/asm/csr.h create mode 100644 arch/riscv/include/asm/linkage.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/uaccess.h create mode 100644 arch/riscv/include/asm/word-at-a-time.h create mode 100644 arch/riscv/kernel/stacktrace.c create mode 100644 arch/riscv/lib/memcpy.S create mode 100644 arch/riscv/lib/memset.S create mode 100644 arch/riscv/lib/uaccess.S create mode 100644 arch/riscv/lib/udivdi3.S diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h new file mode 100644 index ..6cbbb6a68d76 --- /dev/null +++ b/arch/riscv/include/asm/asm.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b)__ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b)__ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ == 8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR8 +#define RISCV_LGPTR3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR"8" +#define RISCV_LGPTR"3" +#endif +#elif __SIZEOF_POINTER__ == 4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR4 +#define RISCV_LGPTR2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR"4" +#define RISCV_LGPTR"2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ == 4) +#define INT__ASM_STR(.word) +#define SZINT __ASM_STR(4) +#define LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ == 2) +#define SHORT __ASM_STR(.half) +#define SZSHORT__ASM_STR(2) +#define LGSHORT__ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index ..387d0dbf0073 --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#include + +/* Status register flags */ +#define SR_IE _AC(0x0002, UL) /* Interrupt Enable */ +#define SR_PIE _AC(0x0020, UL) /* Previous IE */ +#define SR_PS _AC(0x0100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x0004, UL) /* Supervisor may access User Memory */ + +#define SR_FS _AC(0x6000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x, UL) +#define SR_FS_INITIAL _AC(0x2000, UL)
[PATCH 11/17] RISC-V: Generic library routines and assembly
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt--- arch/riscv/include/asm/asm.h| 76 + arch/riscv/include/asm/csr.h| 125 arch/riscv/include/asm/linkage.h| 20 ++ arch/riscv/include/asm/string.h | 26 ++ arch/riscv/include/asm/uaccess.h| 513 arch/riscv/include/asm/word-at-a-time.h | 55 arch/riscv/kernel/stacktrace.c | 177 +++ arch/riscv/lib/memcpy.S | 115 +++ arch/riscv/lib/memset.S | 120 arch/riscv/lib/uaccess.S| 117 arch/riscv/lib/udivdi3.S| 38 +++ 11 files changed, 1382 insertions(+) create mode 100644 arch/riscv/include/asm/asm.h create mode 100644 arch/riscv/include/asm/csr.h create mode 100644 arch/riscv/include/asm/linkage.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/uaccess.h create mode 100644 arch/riscv/include/asm/word-at-a-time.h create mode 100644 arch/riscv/kernel/stacktrace.c create mode 100644 arch/riscv/lib/memcpy.S create mode 100644 arch/riscv/lib/memset.S create mode 100644 arch/riscv/lib/uaccess.S create mode 100644 arch/riscv/lib/udivdi3.S diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h new file mode 100644 index ..6cbbb6a68d76 --- /dev/null +++ b/arch/riscv/include/asm/asm.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b)__ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b)__ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ == 8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR8 +#define RISCV_LGPTR3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR"8" +#define RISCV_LGPTR"3" +#endif +#elif __SIZEOF_POINTER__ == 4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR4 +#define RISCV_LGPTR2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR"4" +#define RISCV_LGPTR"2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ == 4) +#define INT__ASM_STR(.word) +#define SZINT __ASM_STR(4) +#define LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ == 2) +#define SHORT __ASM_STR(.half) +#define SZSHORT__ASM_STR(2) +#define LGSHORT__ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index ..387d0dbf0073 --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#include + +/* Status register flags */ +#define SR_IE _AC(0x0002, UL) /* Interrupt Enable */ +#define SR_PIE _AC(0x0020, UL) /* Previous IE */ +#define SR_PS _AC(0x0100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x0004, UL) /* Supervisor may access User Memory */ + +#define SR_FS _AC(0x6000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x, UL) +#define SR_FS_INITIAL
[PATCH 11/17] RISC-V: Generic library routines and assembly
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/asm.h| 76 + arch/riscv/include/asm/csr.h| 125 arch/riscv/include/asm/linkage.h| 20 ++ arch/riscv/include/asm/string.h | 26 ++ arch/riscv/include/asm/uaccess.h| 513 arch/riscv/include/asm/word-at-a-time.h | 55 arch/riscv/kernel/stacktrace.c | 177 +++ arch/riscv/lib/memcpy.S | 115 +++ arch/riscv/lib/memset.S | 120 arch/riscv/lib/uaccess.S| 117 arch/riscv/lib/udivdi3.S| 38 +++ 11 files changed, 1382 insertions(+) create mode 100644 arch/riscv/include/asm/asm.h create mode 100644 arch/riscv/include/asm/csr.h create mode 100644 arch/riscv/include/asm/linkage.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/uaccess.h create mode 100644 arch/riscv/include/asm/word-at-a-time.h create mode 100644 arch/riscv/kernel/stacktrace.c create mode 100644 arch/riscv/lib/memcpy.S create mode 100644 arch/riscv/lib/memset.S create mode 100644 arch/riscv/lib/uaccess.S create mode 100644 arch/riscv/lib/udivdi3.S diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h new file mode 100644 index ..6cbbb6a68d76 --- /dev/null +++ b/arch/riscv/include/asm/asm.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b)__ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b)__ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ == 8 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR8 +#define RISCV_LGPTR3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR"8" +#define RISCV_LGPTR"3" +#endif +#elif __SIZEOF_POINTER__ == 4 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR4 +#define RISCV_LGPTR2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR"4" +#define RISCV_LGPTR"2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ == 4) +#define INT__ASM_STR(.word) +#define SZINT __ASM_STR(4) +#define LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ == 2) +#define SHORT __ASM_STR(.half) +#define SZSHORT__ASM_STR(2) +#define LGSHORT__ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#endif /* _ASM_RISCV_ASM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index ..387d0dbf0073 --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2015 Regents of the University of California + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#include + +/* Status register flags */ +#define SR_IE _AC(0x0002, UL) /* Interrupt Enable */ +#define SR_PIE _AC(0x0020, UL) /* Previous IE */ +#define SR_PS _AC(0x0100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x0004, UL) /* Supervisor may access User Memory */ + +#define SR_FS _AC(0x6000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x, UL) +#define SR_FS_INITIAL _AC(0x2000, UL)