Re: [PATCH 11/83] hsa/radeon: Add scheduler code
On 11/07/14 21:25, Jerome Glisse wrote: On Fri, Jul 11, 2014 at 12:50:11AM +0300, Oded Gabbay wrote: This patch adds the code base of the scheduler, which handles queue creation, deletion and scheduling on the CP of the GPU. Signed-off-by: Oded Gabbay I would rather see all this squashed, this gave feeling that driver can access register which is latter remove. I know jungling with patch squashing can be daunting but really it makes reviewing hard here because i have to jump back and forth to see if thing i am looking at really matter in the final version. Cheers, Jérôme Squashed and restructured in v2 of the patchset. Oded --- drivers/gpu/hsa/radeon/Makefile | 3 +- drivers/gpu/hsa/radeon/cik_regs.h | 213 +++ drivers/gpu/hsa/radeon/kfd_device.c | 1 + drivers/gpu/hsa/radeon/kfd_registers.c| 50 ++ drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 800 ++ drivers/gpu/hsa/radeon/kfd_vidmem.c | 61 ++ 6 files changed, 1127 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/hsa/radeon/cik_regs.h create mode 100644 drivers/gpu/hsa/radeon/kfd_registers.c create mode 100644 drivers/gpu/hsa/radeon/kfd_sched_cik_static.c create mode 100644 drivers/gpu/hsa/radeon/kfd_vidmem.c diff --git a/drivers/gpu/hsa/radeon/Makefile b/drivers/gpu/hsa/radeon/Makefile index 989518a..28da10c 100644 --- a/drivers/gpu/hsa/radeon/Makefile +++ b/drivers/gpu/hsa/radeon/Makefile @@ -4,6 +4,7 @@ radeon_kfd-y := kfd_module.o kfd_device.o kfd_chardev.o \ kfd_pasid.o kfd_topology.o kfd_process.o \ - kfd_doorbell.o + kfd_doorbell.o kfd_sched_cik_static.o kfd_registers.o \ + kfd_vidmem.o obj-$(CONFIG_HSA_RADEON) += radeon_kfd.o diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h new file mode 100644 index 000..d0cdc57 --- /dev/null +++ b/drivers/gpu/hsa/radeon/cik_regs.h @@ -0,0 +1,213 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef CIK_REGS_H +#define CIK_REGS_H + +#define BIF_DOORBELL_CNTL 0x530Cu + +#defineSRBM_GFX_CNTL 0xE44 +#definePIPEID(x) ((x) << 0) +#defineMEID(x) ((x) << 2) +#defineVMID(x) ((x) << 4) +#defineQUEUEID(x) ((x) << 8) + +#defineSQ_CONFIG 0x8C00 + +#defineSH_MEM_BASES0x8C28 +/* if PTR32, these are the bases for scratch and lds */ +#definePRIVATE_BASE(x) ((x) << 0) /* scratch */ +#defineSHARED_BASE(x) ((x) << 16) /* LDS */ +#defineSH_MEM_APE1_BASE0x8C2C +/* if PTR32, this is the base location of GPUVM */ +#defineSH_MEM_APE1_LIMIT 0x8C30 +/* if PTR32, this is the upper limit of GPUVM */ +#defineSH_MEM_CONFIG 0x8C34 +#definePTR32 (1 << 0) +#defineALIGNMENT_MODE(x) ((x) << 2) +#defineSH_MEM_ALIGNMENT_MODE_DWORD 0 +#defineSH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 +#defineSH_MEM_ALIGNMENT_MODE_STRICT2 +#defineSH_MEM_ALIGNMENT_MODE_UNALIGNED 3 +#defineDEFAULT_MTYPE(x)((x) << 4) +#defineAPE1_MTYPE(x) ((x) << 7) + +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#defineMTYPE_NONCACHED
Re: [PATCH 11/83] hsa/radeon: Add scheduler code
On 11/07/14 21:25, Jerome Glisse wrote: On Fri, Jul 11, 2014 at 12:50:11AM +0300, Oded Gabbay wrote: This patch adds the code base of the scheduler, which handles queue creation, deletion and scheduling on the CP of the GPU. Signed-off-by: Oded Gabbay oded.gab...@amd.com I would rather see all this squashed, this gave feeling that driver can access register which is latter remove. I know jungling with patch squashing can be daunting but really it makes reviewing hard here because i have to jump back and forth to see if thing i am looking at really matter in the final version. Cheers, Jérôme Squashed and restructured in v2 of the patchset. Oded --- drivers/gpu/hsa/radeon/Makefile | 3 +- drivers/gpu/hsa/radeon/cik_regs.h | 213 +++ drivers/gpu/hsa/radeon/kfd_device.c | 1 + drivers/gpu/hsa/radeon/kfd_registers.c| 50 ++ drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 800 ++ drivers/gpu/hsa/radeon/kfd_vidmem.c | 61 ++ 6 files changed, 1127 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/hsa/radeon/cik_regs.h create mode 100644 drivers/gpu/hsa/radeon/kfd_registers.c create mode 100644 drivers/gpu/hsa/radeon/kfd_sched_cik_static.c create mode 100644 drivers/gpu/hsa/radeon/kfd_vidmem.c diff --git a/drivers/gpu/hsa/radeon/Makefile b/drivers/gpu/hsa/radeon/Makefile index 989518a..28da10c 100644 --- a/drivers/gpu/hsa/radeon/Makefile +++ b/drivers/gpu/hsa/radeon/Makefile @@ -4,6 +4,7 @@ radeon_kfd-y := kfd_module.o kfd_device.o kfd_chardev.o \ kfd_pasid.o kfd_topology.o kfd_process.o \ - kfd_doorbell.o + kfd_doorbell.o kfd_sched_cik_static.o kfd_registers.o \ + kfd_vidmem.o obj-$(CONFIG_HSA_RADEON) += radeon_kfd.o diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h new file mode 100644 index 000..d0cdc57 --- /dev/null +++ b/drivers/gpu/hsa/radeon/cik_regs.h @@ -0,0 +1,213 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef CIK_REGS_H +#define CIK_REGS_H + +#define BIF_DOORBELL_CNTL 0x530Cu + +#defineSRBM_GFX_CNTL 0xE44 +#definePIPEID(x) ((x) 0) +#defineMEID(x) ((x) 2) +#defineVMID(x) ((x) 4) +#defineQUEUEID(x) ((x) 8) + +#defineSQ_CONFIG 0x8C00 + +#defineSH_MEM_BASES0x8C28 +/* if PTR32, these are the bases for scratch and lds */ +#definePRIVATE_BASE(x) ((x) 0) /* scratch */ +#defineSHARED_BASE(x) ((x) 16) /* LDS */ +#defineSH_MEM_APE1_BASE0x8C2C +/* if PTR32, this is the base location of GPUVM */ +#defineSH_MEM_APE1_LIMIT 0x8C30 +/* if PTR32, this is the upper limit of GPUVM */ +#defineSH_MEM_CONFIG 0x8C34 +#definePTR32 (1 0) +#defineALIGNMENT_MODE(x) ((x) 2) +#defineSH_MEM_ALIGNMENT_MODE_DWORD 0 +#defineSH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 +#defineSH_MEM_ALIGNMENT_MODE_STRICT2 +#defineSH_MEM_ALIGNMENT_MODE_UNALIGNED 3 +#defineDEFAULT_MTYPE(x)((x) 4) +#defineAPE1_MTYPE(x) ((x) 7) + +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#defineMTYPE_NONCACHED
Re: [PATCH 11/83] hsa/radeon: Add scheduler code
On Fri, Jul 11, 2014 at 12:50:11AM +0300, Oded Gabbay wrote: > This patch adds the code base of the scheduler, which handles queue > creation, deletion and scheduling on the CP of the GPU. > > Signed-off-by: Oded Gabbay I would rather see all this squashed, this gave feeling that driver can access register which is latter remove. I know jungling with patch squashing can be daunting but really it makes reviewing hard here because i have to jump back and forth to see if thing i am looking at really matter in the final version. Cheers, Jérôme > --- > drivers/gpu/hsa/radeon/Makefile | 3 +- > drivers/gpu/hsa/radeon/cik_regs.h | 213 +++ > drivers/gpu/hsa/radeon/kfd_device.c | 1 + > drivers/gpu/hsa/radeon/kfd_registers.c| 50 ++ > drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 800 > ++ > drivers/gpu/hsa/radeon/kfd_vidmem.c | 61 ++ > 6 files changed, 1127 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/hsa/radeon/cik_regs.h > create mode 100644 drivers/gpu/hsa/radeon/kfd_registers.c > create mode 100644 drivers/gpu/hsa/radeon/kfd_sched_cik_static.c > create mode 100644 drivers/gpu/hsa/radeon/kfd_vidmem.c > > diff --git a/drivers/gpu/hsa/radeon/Makefile b/drivers/gpu/hsa/radeon/Makefile > index 989518a..28da10c 100644 > --- a/drivers/gpu/hsa/radeon/Makefile > +++ b/drivers/gpu/hsa/radeon/Makefile > @@ -4,6 +4,7 @@ > > radeon_kfd-y := kfd_module.o kfd_device.o kfd_chardev.o \ > kfd_pasid.o kfd_topology.o kfd_process.o \ > - kfd_doorbell.o > + kfd_doorbell.o kfd_sched_cik_static.o kfd_registers.o \ > + kfd_vidmem.o > > obj-$(CONFIG_HSA_RADEON) += radeon_kfd.o > diff --git a/drivers/gpu/hsa/radeon/cik_regs.h > b/drivers/gpu/hsa/radeon/cik_regs.h > new file mode 100644 > index 000..d0cdc57 > --- /dev/null > +++ b/drivers/gpu/hsa/radeon/cik_regs.h > @@ -0,0 +1,213 @@ > +/* > + * Copyright 2014 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#ifndef CIK_REGS_H > +#define CIK_REGS_H > + > +#define BIF_DOORBELL_CNTL0x530Cu > + > +#define SRBM_GFX_CNTL 0xE44 > +#define PIPEID(x) ((x) << 0) > +#define MEID(x) ((x) << 2) > +#define VMID(x) ((x) << 4) > +#define QUEUEID(x) ((x) << 8) > + > +#define SQ_CONFIG 0x8C00 > + > +#define SH_MEM_BASES0x8C28 > +/* if PTR32, these are the bases for scratch and lds */ > +#define PRIVATE_BASE(x) ((x) << 0) /* > scratch */ > +#define SHARED_BASE(x) ((x) << 16) /* > LDS */ > +#define SH_MEM_APE1_BASE0x8C2C > +/* if PTR32, this is the base location of GPUVM */ > +#define SH_MEM_APE1_LIMIT 0x8C30 > +/* if PTR32, this is the upper limit of GPUVM */ > +#define SH_MEM_CONFIG 0x8C34 > +#define PTR32 (1 << 0) > +#define ALIGNMENT_MODE(x) ((x) << 2) > +#define SH_MEM_ALIGNMENT_MODE_DWORD 0 > +#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 > +#define SH_MEM_ALIGNMENT_MODE_STRICT2 > +#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 > +#define DEFAULT_MTYPE(x)((x) << 4) > +#define APE1_MTYPE(x) ((x) << 7) > + > +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ > +#define
Re: [PATCH 11/83] hsa/radeon: Add scheduler code
On Fri, Jul 11, 2014 at 12:50:11AM +0300, Oded Gabbay wrote: This patch adds the code base of the scheduler, which handles queue creation, deletion and scheduling on the CP of the GPU. Signed-off-by: Oded Gabbay oded.gab...@amd.com I would rather see all this squashed, this gave feeling that driver can access register which is latter remove. I know jungling with patch squashing can be daunting but really it makes reviewing hard here because i have to jump back and forth to see if thing i am looking at really matter in the final version. Cheers, Jérôme --- drivers/gpu/hsa/radeon/Makefile | 3 +- drivers/gpu/hsa/radeon/cik_regs.h | 213 +++ drivers/gpu/hsa/radeon/kfd_device.c | 1 + drivers/gpu/hsa/radeon/kfd_registers.c| 50 ++ drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 800 ++ drivers/gpu/hsa/radeon/kfd_vidmem.c | 61 ++ 6 files changed, 1127 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/hsa/radeon/cik_regs.h create mode 100644 drivers/gpu/hsa/radeon/kfd_registers.c create mode 100644 drivers/gpu/hsa/radeon/kfd_sched_cik_static.c create mode 100644 drivers/gpu/hsa/radeon/kfd_vidmem.c diff --git a/drivers/gpu/hsa/radeon/Makefile b/drivers/gpu/hsa/radeon/Makefile index 989518a..28da10c 100644 --- a/drivers/gpu/hsa/radeon/Makefile +++ b/drivers/gpu/hsa/radeon/Makefile @@ -4,6 +4,7 @@ radeon_kfd-y := kfd_module.o kfd_device.o kfd_chardev.o \ kfd_pasid.o kfd_topology.o kfd_process.o \ - kfd_doorbell.o + kfd_doorbell.o kfd_sched_cik_static.o kfd_registers.o \ + kfd_vidmem.o obj-$(CONFIG_HSA_RADEON) += radeon_kfd.o diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h new file mode 100644 index 000..d0cdc57 --- /dev/null +++ b/drivers/gpu/hsa/radeon/cik_regs.h @@ -0,0 +1,213 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef CIK_REGS_H +#define CIK_REGS_H + +#define BIF_DOORBELL_CNTL0x530Cu + +#define SRBM_GFX_CNTL 0xE44 +#define PIPEID(x) ((x) 0) +#define MEID(x) ((x) 2) +#define VMID(x) ((x) 4) +#define QUEUEID(x) ((x) 8) + +#define SQ_CONFIG 0x8C00 + +#define SH_MEM_BASES0x8C28 +/* if PTR32, these are the bases for scratch and lds */ +#define PRIVATE_BASE(x) ((x) 0) /* scratch */ +#define SHARED_BASE(x) ((x) 16) /* LDS */ +#define SH_MEM_APE1_BASE0x8C2C +/* if PTR32, this is the base location of GPUVM */ +#define SH_MEM_APE1_LIMIT 0x8C30 +/* if PTR32, this is the upper limit of GPUVM */ +#define SH_MEM_CONFIG 0x8C34 +#define PTR32 (1 0) +#define ALIGNMENT_MODE(x) ((x) 2) +#define SH_MEM_ALIGNMENT_MODE_DWORD 0 +#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 +#define SH_MEM_ALIGNMENT_MODE_STRICT2 +#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 +#define DEFAULT_MTYPE(x)((x) 4) +#define APE1_MTYPE(x) ((x) 7) + +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#define MTYPE_NONCACHED 3 + + +#define SH_STATIC_MEM_CONFIG
[PATCH 11/83] hsa/radeon: Add scheduler code
This patch adds the code base of the scheduler, which handles queue creation, deletion and scheduling on the CP of the GPU. Signed-off-by: Oded Gabbay --- drivers/gpu/hsa/radeon/Makefile | 3 +- drivers/gpu/hsa/radeon/cik_regs.h | 213 +++ drivers/gpu/hsa/radeon/kfd_device.c | 1 + drivers/gpu/hsa/radeon/kfd_registers.c| 50 ++ drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 800 ++ drivers/gpu/hsa/radeon/kfd_vidmem.c | 61 ++ 6 files changed, 1127 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/hsa/radeon/cik_regs.h create mode 100644 drivers/gpu/hsa/radeon/kfd_registers.c create mode 100644 drivers/gpu/hsa/radeon/kfd_sched_cik_static.c create mode 100644 drivers/gpu/hsa/radeon/kfd_vidmem.c diff --git a/drivers/gpu/hsa/radeon/Makefile b/drivers/gpu/hsa/radeon/Makefile index 989518a..28da10c 100644 --- a/drivers/gpu/hsa/radeon/Makefile +++ b/drivers/gpu/hsa/radeon/Makefile @@ -4,6 +4,7 @@ radeon_kfd-y := kfd_module.o kfd_device.o kfd_chardev.o \ kfd_pasid.o kfd_topology.o kfd_process.o \ - kfd_doorbell.o + kfd_doorbell.o kfd_sched_cik_static.o kfd_registers.o \ + kfd_vidmem.o obj-$(CONFIG_HSA_RADEON) += radeon_kfd.o diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h new file mode 100644 index 000..d0cdc57 --- /dev/null +++ b/drivers/gpu/hsa/radeon/cik_regs.h @@ -0,0 +1,213 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef CIK_REGS_H +#define CIK_REGS_H + +#define BIF_DOORBELL_CNTL 0x530Cu + +#defineSRBM_GFX_CNTL 0xE44 +#definePIPEID(x) ((x) << 0) +#defineMEID(x) ((x) << 2) +#defineVMID(x) ((x) << 4) +#defineQUEUEID(x) ((x) << 8) + +#defineSQ_CONFIG 0x8C00 + +#defineSH_MEM_BASES0x8C28 +/* if PTR32, these are the bases for scratch and lds */ +#definePRIVATE_BASE(x) ((x) << 0) /* scratch */ +#defineSHARED_BASE(x) ((x) << 16) /* LDS */ +#defineSH_MEM_APE1_BASE0x8C2C +/* if PTR32, this is the base location of GPUVM */ +#defineSH_MEM_APE1_LIMIT 0x8C30 +/* if PTR32, this is the upper limit of GPUVM */ +#defineSH_MEM_CONFIG 0x8C34 +#definePTR32 (1 << 0) +#defineALIGNMENT_MODE(x) ((x) << 2) +#defineSH_MEM_ALIGNMENT_MODE_DWORD 0 +#defineSH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 +#defineSH_MEM_ALIGNMENT_MODE_STRICT2 +#defineSH_MEM_ALIGNMENT_MODE_UNALIGNED 3 +#defineDEFAULT_MTYPE(x)((x) << 4) +#defineAPE1_MTYPE(x) ((x) << 7) + +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#defineMTYPE_NONCACHED 3 + + +#define SH_STATIC_MEM_CONFIG 0x9604u + +#defineTC_CFG_L1_LOAD_POLICY0 0xAC68 +#defineTC_CFG_L1_LOAD_POLICY1 0xAC6C +#defineTC_CFG_L1_STORE_POLICY 0xAC70 +#defineTC_CFG_L2_LOAD_POLICY0 0xAC74 +#defineTC_CFG_L2_LOAD_POLICY1 0xAC78 +#defineTC_CFG_L2_STORE_POLICY0
[PATCH 11/83] hsa/radeon: Add scheduler code
This patch adds the code base of the scheduler, which handles queue creation, deletion and scheduling on the CP of the GPU. Signed-off-by: Oded Gabbay oded.gab...@amd.com --- drivers/gpu/hsa/radeon/Makefile | 3 +- drivers/gpu/hsa/radeon/cik_regs.h | 213 +++ drivers/gpu/hsa/radeon/kfd_device.c | 1 + drivers/gpu/hsa/radeon/kfd_registers.c| 50 ++ drivers/gpu/hsa/radeon/kfd_sched_cik_static.c | 800 ++ drivers/gpu/hsa/radeon/kfd_vidmem.c | 61 ++ 6 files changed, 1127 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/hsa/radeon/cik_regs.h create mode 100644 drivers/gpu/hsa/radeon/kfd_registers.c create mode 100644 drivers/gpu/hsa/radeon/kfd_sched_cik_static.c create mode 100644 drivers/gpu/hsa/radeon/kfd_vidmem.c diff --git a/drivers/gpu/hsa/radeon/Makefile b/drivers/gpu/hsa/radeon/Makefile index 989518a..28da10c 100644 --- a/drivers/gpu/hsa/radeon/Makefile +++ b/drivers/gpu/hsa/radeon/Makefile @@ -4,6 +4,7 @@ radeon_kfd-y := kfd_module.o kfd_device.o kfd_chardev.o \ kfd_pasid.o kfd_topology.o kfd_process.o \ - kfd_doorbell.o + kfd_doorbell.o kfd_sched_cik_static.o kfd_registers.o \ + kfd_vidmem.o obj-$(CONFIG_HSA_RADEON) += radeon_kfd.o diff --git a/drivers/gpu/hsa/radeon/cik_regs.h b/drivers/gpu/hsa/radeon/cik_regs.h new file mode 100644 index 000..d0cdc57 --- /dev/null +++ b/drivers/gpu/hsa/radeon/cik_regs.h @@ -0,0 +1,213 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef CIK_REGS_H +#define CIK_REGS_H + +#define BIF_DOORBELL_CNTL 0x530Cu + +#defineSRBM_GFX_CNTL 0xE44 +#definePIPEID(x) ((x) 0) +#defineMEID(x) ((x) 2) +#defineVMID(x) ((x) 4) +#defineQUEUEID(x) ((x) 8) + +#defineSQ_CONFIG 0x8C00 + +#defineSH_MEM_BASES0x8C28 +/* if PTR32, these are the bases for scratch and lds */ +#definePRIVATE_BASE(x) ((x) 0) /* scratch */ +#defineSHARED_BASE(x) ((x) 16) /* LDS */ +#defineSH_MEM_APE1_BASE0x8C2C +/* if PTR32, this is the base location of GPUVM */ +#defineSH_MEM_APE1_LIMIT 0x8C30 +/* if PTR32, this is the upper limit of GPUVM */ +#defineSH_MEM_CONFIG 0x8C34 +#definePTR32 (1 0) +#defineALIGNMENT_MODE(x) ((x) 2) +#defineSH_MEM_ALIGNMENT_MODE_DWORD 0 +#defineSH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 +#defineSH_MEM_ALIGNMENT_MODE_STRICT2 +#defineSH_MEM_ALIGNMENT_MODE_UNALIGNED 3 +#defineDEFAULT_MTYPE(x)((x) 4) +#defineAPE1_MTYPE(x) ((x) 7) + +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#defineMTYPE_NONCACHED 3 + + +#define SH_STATIC_MEM_CONFIG 0x9604u + +#defineTC_CFG_L1_LOAD_POLICY0 0xAC68 +#defineTC_CFG_L1_LOAD_POLICY1 0xAC6C +#defineTC_CFG_L1_STORE_POLICY 0xAC70 +#defineTC_CFG_L2_LOAD_POLICY0 0xAC74 +#defineTC_CFG_L2_LOAD_POLICY1 0xAC78 +#defineTC_CFG_L2_STORE_POLICY0
