[PATCH 16/26] drm/rockchip: dw-mipi-dsi: configure bias and bandgap before enable

[John Keeping]

We should configure these functions before enabling them.

Signed-off-by: John Keeping 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 73c28e205fc5..f824c99b872e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -421,6 +421,11 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 HIGH_PROGRAM_EN);
 
+   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
+BIASEXTR_SEL(BIASEXTR_127_7));
+   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
+BANDGAP_SEL(BANDGAP_96_10));
+
dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 BIAS_BLOCK_ON | BANDGAP_ON);
 
@@ -430,10 +435,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 SETRD_MAX | POWER_MANAGE |
 TER_RESISTORS_ON);
 
-   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-BIASEXTR_SEL(BIASEXTR_127_7));
-   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-BANDGAP_SEL(BANDGAP_96_10));
 
dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
-- 
2.10.0.278.g4f427b1.dirty

[PATCH 16/26] drm/rockchip: dw-mipi-dsi: configure bias and bandgap before enable

[John Keeping]

We should configure these functions before enabling them.

Signed-off-by: John Keeping 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 73c28e205fc5..f824c99b872e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -421,6 +421,11 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 HIGH_PROGRAM_EN);
 
+   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
+BIASEXTR_SEL(BIASEXTR_127_7));
+   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
+BANDGAP_SEL(BANDGAP_96_10));
+
dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 BIAS_BLOCK_ON | BANDGAP_ON);
 
@@ -430,10 +435,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 SETRD_MAX | POWER_MANAGE |
 TER_RESISTORS_ON);
 
-   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-BIASEXTR_SEL(BIASEXTR_127_7));
-   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-BANDGAP_SEL(BANDGAP_96_10));
 
dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
-- 
2.10.0.278.g4f427b1.dirty