[PATCH 20/27] drm/rockchip: dw-mipi-dsi: properly configure PHY timing

These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock

[PATCH 20/27] drm/rockchip: dw-mipi-dsi: properly configure PHY timing

These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock