[PATCH 4.15 113/168] x86/microcode/intel: Check microcode revision before updating sibling threads

[Greg Kroah-Hartman]

4.15-stable review patch.  If anyone has any objections, please let me know.

--

From: Ashok Raj 

commit c182d2b7d0ca48e0d6ff16f7d883161238c447ed upstream.

After updating microcode on one of the threads of a core, the other
thread sibling automatically gets the update since the microcode
resources on a hyperthreaded core are shared between the two threads.

Check the microcode revision on the CPU before performing a microcode
update and thus save us the WRMSR 0x79 because it is a particularly
expensive operation.

[ Borislav: Massage changelog and coding style. ]

Signed-off-by: Ashok Raj 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Tested-by: Tom Lendacky 
Tested-by: Ashok Raj 
Cc: Arjan Van De Ven 
Link: 
http://lkml.kernel.org/r/1519352533-15992-2-git-send-email-ashok@intel.com
Link: https://lkml.kernel.org/r/20180228102846.13447-3...@alien8.de
Signed-off-by: Greg Kroah-Hartman 

---
 arch/x86/kernel/cpu/microcode/intel.c |   27 ---
 1 file changed, 24 insertions(+), 3 deletions(-)

--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -589,6 +589,17 @@ static int apply_microcode_early(struct
if (!mc)
return 0;
 
+   /*
+* Save us the MSR write below - which is a particular expensive
+* operation - when the other hyperthread has updated the microcode
+* already.
+*/
+   rev = intel_get_microcode_revision();
+   if (rev >= mc->hdr.rev) {
+   uci->cpu_sig.rev = rev;
+   return UCODE_OK;
+   }
+
/* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
@@ -776,7 +787,7 @@ static enum ucode_state apply_microcode_
 {
struct microcode_intel *mc;
struct ucode_cpu_info *uci;
-   struct cpuinfo_x86 *c;
+   struct cpuinfo_x86 *c = _data(cpu);
static int prev_rev;
u32 rev;
 
@@ -793,6 +804,18 @@ static enum ucode_state apply_microcode_
return UCODE_NFOUND;
}
 
+   /*
+* Save us the MSR write below - which is a particular expensive
+* operation - when the other hyperthread has updated the microcode
+* already.
+*/
+   rev = intel_get_microcode_revision();
+   if (rev >= mc->hdr.rev) {
+   uci->cpu_sig.rev = rev;
+   c->microcode = rev;
+   return UCODE_OK;
+   }
+
/* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
@@ -813,8 +836,6 @@ static enum ucode_state apply_microcode_
prev_rev = rev;
}
 
-   c = _data(cpu);
-
uci->cpu_sig.rev = rev;
c->microcode = rev;
 

[PATCH 4.15 113/168] x86/microcode/intel: Check microcode revision before updating sibling threads

[Greg Kroah-Hartman]

4.15-stable review patch.  If anyone has any objections, please let me know.

--

From: Ashok Raj 

commit c182d2b7d0ca48e0d6ff16f7d883161238c447ed upstream.

After updating microcode on one of the threads of a core, the other
thread sibling automatically gets the update since the microcode
resources on a hyperthreaded core are shared between the two threads.

Check the microcode revision on the CPU before performing a microcode
update and thus save us the WRMSR 0x79 because it is a particularly
expensive operation.

[ Borislav: Massage changelog and coding style. ]

Signed-off-by: Ashok Raj 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Tested-by: Tom Lendacky 
Tested-by: Ashok Raj 
Cc: Arjan Van De Ven 
Link: 
http://lkml.kernel.org/r/1519352533-15992-2-git-send-email-ashok@intel.com
Link: https://lkml.kernel.org/r/20180228102846.13447-3...@alien8.de
Signed-off-by: Greg Kroah-Hartman 

---
 arch/x86/kernel/cpu/microcode/intel.c |   27 ---
 1 file changed, 24 insertions(+), 3 deletions(-)

--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -589,6 +589,17 @@ static int apply_microcode_early(struct
if (!mc)
return 0;
 
+   /*
+* Save us the MSR write below - which is a particular expensive
+* operation - when the other hyperthread has updated the microcode
+* already.
+*/
+   rev = intel_get_microcode_revision();
+   if (rev >= mc->hdr.rev) {
+   uci->cpu_sig.rev = rev;
+   return UCODE_OK;
+   }
+
/* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
@@ -776,7 +787,7 @@ static enum ucode_state apply_microcode_
 {
struct microcode_intel *mc;
struct ucode_cpu_info *uci;
-   struct cpuinfo_x86 *c;
+   struct cpuinfo_x86 *c = _data(cpu);
static int prev_rev;
u32 rev;
 
@@ -793,6 +804,18 @@ static enum ucode_state apply_microcode_
return UCODE_NFOUND;
}
 
+   /*
+* Save us the MSR write below - which is a particular expensive
+* operation - when the other hyperthread has updated the microcode
+* already.
+*/
+   rev = intel_get_microcode_revision();
+   if (rev >= mc->hdr.rev) {
+   uci->cpu_sig.rev = rev;
+   c->microcode = rev;
+   return UCODE_OK;
+   }
+
/* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
@@ -813,8 +836,6 @@ static enum ucode_state apply_microcode_
prev_rev = rev;
}
 
-   c = _data(cpu);
-
uci->cpu_sig.rev = rev;
c->microcode = rev;