[PATCH 4.4 060/118] bus: arm-ccn: Fix XP watchpoint settings bitmask

[Greg Kroah-Hartman]

4.4-stable review patch.  If anyone has any objections, please let me know.

--

From: Pawel Moll 

commit b928466b2169e061822daad48ecf55b005445547 upstream.

The code setting XP watchpoint comparator and mask registers should, in
order to be fully compliant with specification, zero one or more most
significant bits of each field. In both L cases it means zeroing bit 63.
The bitmask doing this was wrong, though, zeroing bit 60 instead.
Fortunately, due to a lucky coincidence, this turned out to be fairly
innocent with the existing hardware.

Fixed now.

Signed-off-by: Pawel Moll 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/bus/arm-ccn.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/drivers/bus/arm-ccn.c
+++ b/drivers/bus/arm-ccn.c
@@ -1001,7 +1001,7 @@ static void arm_ccn_pmu_xp_watchpoint_co
 
/* Comparison values */
writel(cmp_l & 0x, source->base + CCN_XP_DT_CMP_VAL_L(wp));
-   writel((cmp_l >> 32) & 0xefff,
+   writel((cmp_l >> 32) & 0x7fff,
source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
writel(cmp_h & 0x, source->base + CCN_XP_DT_CMP_VAL_H(wp));
writel((cmp_h >> 32) & 0x0fff,
@@ -1009,7 +1009,7 @@ static void arm_ccn_pmu_xp_watchpoint_co
 
/* Mask */
writel(mask_l & 0x, source->base + CCN_XP_DT_CMP_MASK_L(wp));
-   writel((mask_l >> 32) & 0xefff,
+   writel((mask_l >> 32) & 0x7fff,
source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
writel(mask_h & 0x, source->base + CCN_XP_DT_CMP_MASK_H(wp));
writel((mask_h >> 32) & 0x0fff,

[PATCH 4.4 060/118] bus: arm-ccn: Fix XP watchpoint settings bitmask

[Greg Kroah-Hartman]

4.4-stable review patch.  If anyone has any objections, please let me know.

--

From: Pawel Moll 

commit b928466b2169e061822daad48ecf55b005445547 upstream.

The code setting XP watchpoint comparator and mask registers should, in
order to be fully compliant with specification, zero one or more most
significant bits of each field. In both L cases it means zeroing bit 63.
The bitmask doing this was wrong, though, zeroing bit 60 instead.
Fortunately, due to a lucky coincidence, this turned out to be fairly
innocent with the existing hardware.

Fixed now.

Signed-off-by: Pawel Moll 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/bus/arm-ccn.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/drivers/bus/arm-ccn.c
+++ b/drivers/bus/arm-ccn.c
@@ -1001,7 +1001,7 @@ static void arm_ccn_pmu_xp_watchpoint_co
 
/* Comparison values */
writel(cmp_l & 0x, source->base + CCN_XP_DT_CMP_VAL_L(wp));
-   writel((cmp_l >> 32) & 0xefff,
+   writel((cmp_l >> 32) & 0x7fff,
source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
writel(cmp_h & 0x, source->base + CCN_XP_DT_CMP_VAL_H(wp));
writel((cmp_h >> 32) & 0x0fff,
@@ -1009,7 +1009,7 @@ static void arm_ccn_pmu_xp_watchpoint_co
 
/* Mask */
writel(mask_l & 0x, source->base + CCN_XP_DT_CMP_MASK_L(wp));
-   writel((mask_l >> 32) & 0xefff,
+   writel((mask_l >> 32) & 0x7fff,
source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
writel(mask_h & 0x, source->base + CCN_XP_DT_CMP_MASK_H(wp));
writel((mask_h >> 32) & 0x0fff,