Re: [PATCH 5/7] igb: eliminate duplicate barriers on weakly-ordered archs

On Tue, Mar 13, 2018 at 8:20 PM, Sinan Kaya wrote: > Code includes wmb() followed by writel(). writel() already has a barrier > on some architectures like arm64. > > This ends up CPU observing two barriers back to back before executing the > register write. > > Since code

Re: [PATCH 5/7] igb: eliminate duplicate barriers on weakly-ordered archs

On Tue, Mar 13, 2018 at 8:20 PM, Sinan Kaya wrote: > Code includes wmb() followed by writel(). writel() already has a barrier > on some architectures like arm64. > > This ends up CPU observing two barriers back to back before executing the > register write. > > Since code already has an explicit

[PATCH 5/7] igb: eliminate duplicate barriers on weakly-ordered archs

Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed().

[PATCH 5/7] igb: eliminate duplicate barriers on weakly-ordered archs

Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed().