[PATCH AUTOSEL for 3.18 055/101] MIPS: CPS: Prevent multi-core with dcache aliasing

From: Paul Burton [ Upstream commit 5570ba2ee920de4e7760a2802b842771845b2c32 ] Systems using the MIPS Coherence Manager (CM) cannot support multi-core SMP with dcache aliasing. This is because CPU caches are VIPT, but interventions in CM-based systems provide only the

[PATCH AUTOSEL for 3.18 055/101] MIPS: CPS: Prevent multi-core with dcache aliasing

From: Paul Burton [ Upstream commit 5570ba2ee920de4e7760a2802b842771845b2c32 ] Systems using the MIPS Coherence Manager (CM) cannot support multi-core SMP with dcache aliasing. This is because CPU caches are VIPT, but interventions in CM-based systems provide only the physical address to remote